1 /* $NetBSD: i80312_pci.c,v 1.13 2012/10/14 14:20:57 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80312 Companion I/O chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.13 2012/10/14 14:20:57 msaitoh Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/extent.h> 49 #include <sys/malloc.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <sys/bus.h> 54 55 #include <arm/xscale/i80312reg.h> 56 #include <arm/xscale/i80312var.h> 57 58 #include <dev/pci/ppbreg.h> 59 #include <dev/pci/pciconf.h> 60 61 #include "opt_pci.h" 62 #include "pci.h" 63 64 void i80312_pci_attach_hook(device_t, device_t, 65 struct pcibus_attach_args *); 66 int i80312_pci_bus_maxdevs(void *, int); 67 pcitag_t i80312_pci_make_tag(void *, int, int, int); 68 void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *, 69 int *); 70 pcireg_t i80312_pci_conf_read(void *, pcitag_t, int); 71 void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t); 72 void i80312_pci_conf_interrupt(void *, int, int, int, int, int *); 73 74 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 75 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 76 77 void 78 i80312_pci_init(pci_chipset_tag_t pc, void *cookie) 79 { 80 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 81 struct i80312_softc *sc = cookie; 82 struct extent *ioext, *memext; 83 pcireg_t binfo; 84 int pbus, sbus; 85 #endif 86 87 pc->pc_conf_v = cookie; 88 pc->pc_attach_hook = i80312_pci_attach_hook; 89 pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs; 90 pc->pc_make_tag = i80312_pci_make_tag; 91 pc->pc_decompose_tag = i80312_pci_decompose_tag; 92 pc->pc_conf_read = i80312_pci_conf_read; 93 pc->pc_conf_write = i80312_pci_conf_write; 94 pc->pc_conf_interrupt = i80312_pci_conf_interrupt; 95 96 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 97 /* 98 * Configure the PCI bus. 99 * 100 * XXX We need to revisit this. We only configure the Secondary 101 * bus (and its children). The bus configure code needs changes 102 * to support how the busses are arranged on this chip. We also 103 * need to only configure devices in the private device space on 104 * the Secondary bus. 105 */ 106 107 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 108 pbus = PPB_BUSINFO_PRIMARY(binfo); 109 sbus = PPB_BUSINFO_SECONDARY(binfo); 110 111 ioext = extent_create("pciio", sc->sc_sioout_base, 112 sc->sc_sioout_base + sc->sc_sioout_size - 1, 113 NULL, 0, EX_NOWAIT); 114 memext = extent_create("pcimem", sc->sc_smemout_base, 115 sc->sc_smemout_base + sc->sc_smemout_size - 1, 116 NULL, 0, EX_NOWAIT); 117 118 aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n"); 119 pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align); 120 121 extent_destroy(ioext); 122 extent_destroy(memext); 123 #endif 124 } 125 126 void 127 i80312_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 128 { 129 } 130 131 void 132 i80312_pci_attach_hook(device_t parent, device_t self, 133 struct pcibus_attach_args *pba) 134 { 135 136 /* Nothing to do. */ 137 } 138 139 int 140 i80312_pci_bus_maxdevs(void *v, int busno) 141 { 142 143 return (32); 144 } 145 146 pcitag_t 147 i80312_pci_make_tag(void *v, int b, int d, int f) 148 { 149 150 return ((b << 16) | (d << 11) | (f << 8)); 151 } 152 153 void 154 i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 155 { 156 157 if (bp != NULL) 158 *bp = (tag >> 16) & 0xff; 159 if (dp != NULL) 160 *dp = (tag >> 11) & 0x1f; 161 if (fp != NULL) 162 *fp = (tag >> 8) & 0x7; 163 } 164 165 struct pciconf_state { 166 bus_addr_t ps_addr_reg; 167 bus_addr_t ps_data_reg; 168 bus_addr_t ps_csr_reg; 169 uint32_t ps_addr_val; 170 171 int ps_b, ps_d, ps_f; 172 }; 173 174 static int 175 i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset, 176 struct pciconf_state *ps) 177 { 178 pcireg_t binfo; 179 int pbus, sbus; 180 181 i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 182 183 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO); 184 pbus = PPB_BUSINFO_PRIMARY(binfo); 185 sbus = PPB_BUSINFO_SECONDARY(binfo); 186 187 /* 188 * If the bus # is the Primary bus #, use the Primary 189 * Address/Data registers, otherwise use the Secondary 190 * Address/Data registers. 191 */ 192 if (ps->ps_b == pbus) { 193 ps->ps_addr_reg = I80312_ATU_POCCA; 194 ps->ps_data_reg = I80312_ATU_POCCD; 195 ps->ps_csr_reg = PCI_COMMAND_STATUS_REG; 196 } else { 197 ps->ps_addr_reg = I80312_ATU_SOCCA; 198 ps->ps_data_reg = I80312_ATU_SOCCD; 199 ps->ps_csr_reg = I80312_ATU_SACS; 200 } 201 202 /* 203 * If the bus # is the Primary or Secondary bus #, then use 204 * Type 0 cycles, else use Type 1. 205 * 206 * XXX We should filter out all non-private devices here! 207 * XXX How does private space interact with PCI-PCI bridges? 208 */ 209 if (ps->ps_b == pbus || ps->ps_b == sbus) { 210 if (ps->ps_d > (31 - 11)) 211 return (1); 212 ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) | 213 offset; 214 } else { 215 /* The tag is already in the correct format. */ 216 ps->ps_addr_val = tag | offset | 1; 217 } 218 219 return (0); 220 } 221 222 pcireg_t 223 i80312_pci_conf_read(void *v, pcitag_t tag, int offset) 224 { 225 struct i80312_softc *sc = v; 226 struct pciconf_state ps; 227 vaddr_t va; 228 pcireg_t rv; 229 u_int s; 230 231 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 232 return ((pcireg_t) -1); 233 234 PCI_CONF_LOCK(s); 235 236 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 237 ps.ps_addr_val); 238 239 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 240 if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) { 241 /* 242 * Clear the Master Abort by reading the PCI 243 * Status Register. 244 */ 245 (void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 246 ps.ps_csr_reg); 247 #if 0 248 printf("conf_read: %d/%d/%d bad address\n", 249 ps.ps_b, ps.ps_d, ps.ps_f); 250 #endif 251 rv = (pcireg_t) -1; 252 } 253 254 PCI_CONF_UNLOCK(s); 255 256 return (rv); 257 } 258 259 void 260 i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 261 { 262 struct i80312_softc *sc = v; 263 struct pciconf_state ps; 264 u_int s; 265 266 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 267 return; 268 269 PCI_CONF_LOCK(s); 270 271 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 272 ps.ps_addr_val); 273 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val); 274 275 PCI_CONF_UNLOCK(s); 276 } 277