1 /* $NetBSD: i80312_pci.c,v 1.19 2020/07/07 03:38:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * PCI configuration support for i80312 Companion I/O chip. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.19 2020/07/07 03:38:46 thorpej Exp $"); 44 45 #include "opt_pci.h" 46 #include "pci.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/malloc.h> 52 #include <sys/bus.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pciconf.h> 58 #include <dev/pci/ppbreg.h> 59 60 #include <arm/locore.h> 61 62 #include <arm/xscale/i80312reg.h> 63 #include <arm/xscale/i80312var.h> 64 65 void i80312_pci_attach_hook(device_t, device_t, 66 struct pcibus_attach_args *); 67 int i80312_pci_bus_maxdevs(void *, int); 68 pcitag_t i80312_pci_make_tag(void *, int, int, int); 69 void i80312_pci_decompose_tag(void *, pcitag_t, int *, int *, 70 int *); 71 pcireg_t i80312_pci_conf_read(void *, pcitag_t, int); 72 void i80312_pci_conf_write(void *, pcitag_t, int, pcireg_t); 73 void i80312_pci_conf_interrupt(void *, int, int, int, int, int *); 74 75 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 76 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 77 78 void 79 i80312_pci_init(pci_chipset_tag_t pc, void *cookie) 80 { 81 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 82 struct i80312_softc *sc = cookie; 83 struct pciconf_resources *pcires; 84 pcireg_t binfo; 85 int sbus; 86 #endif 87 88 pc->pc_conf_v = cookie; 89 pc->pc_attach_hook = i80312_pci_attach_hook; 90 pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs; 91 pc->pc_make_tag = i80312_pci_make_tag; 92 pc->pc_decompose_tag = i80312_pci_decompose_tag; 93 pc->pc_conf_read = i80312_pci_conf_read; 94 pc->pc_conf_write = i80312_pci_conf_write; 95 pc->pc_conf_interrupt = i80312_pci_conf_interrupt; 96 97 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE) 98 /* 99 * Configure the PCI bus. 100 * 101 * XXX We need to revisit this. We only configure the Secondary 102 * bus (and its children). The bus configure code needs changes 103 * to support how the busses are arranged on this chip. We also 104 * need to only configure devices in the private device space on 105 * the Secondary bus. 106 */ 107 108 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG); 109 /* pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo); */ 110 sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo); 111 112 pcires = pciconf_resource_init(); 113 114 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 115 sc->sc_sioout_base, sc->sc_sioout_size); 116 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 117 sc->sc_smemout_base, sc->sc_smemout_size); 118 119 aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n"); 120 pci_configure_bus(pc, pcires, sbus, arm_dcache_align); 121 122 pciconf_resource_fini(pcires); 123 #endif 124 } 125 126 void 127 i80312_pci_conf_interrupt(void *v, int a, int b, int c, int d, int *p) 128 { 129 } 130 131 void 132 i80312_pci_attach_hook(device_t parent, device_t self, 133 struct pcibus_attach_args *pba) 134 { 135 136 /* Nothing to do. */ 137 } 138 139 int 140 i80312_pci_bus_maxdevs(void *v, int busno) 141 { 142 143 return (32); 144 } 145 146 pcitag_t 147 i80312_pci_make_tag(void *v, int b, int d, int f) 148 { 149 150 return ((b << 16) | (d << 11) | (f << 8)); 151 } 152 153 void 154 i80312_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 155 { 156 157 if (bp != NULL) 158 *bp = (tag >> 16) & 0xff; 159 if (dp != NULL) 160 *dp = (tag >> 11) & 0x1f; 161 if (fp != NULL) 162 *fp = (tag >> 8) & 0x7; 163 } 164 165 struct pciconf_state { 166 bus_addr_t ps_addr_reg; 167 bus_addr_t ps_data_reg; 168 bus_addr_t ps_csr_reg; 169 uint32_t ps_addr_val; 170 171 int ps_b, ps_d, ps_f; 172 }; 173 174 static int 175 i80312_pci_conf_setup(struct i80312_softc *sc, pcitag_t tag, int offset, 176 struct pciconf_state *ps) 177 { 178 pcireg_t binfo; 179 int pbus, sbus; 180 181 if ((unsigned int)offset >= PCI_CONF_SIZE) 182 return (1); 183 184 i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f); 185 186 binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG); 187 pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo); 188 sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo); 189 190 /* 191 * If the bus # is the Primary bus #, use the Primary 192 * Address/Data registers, otherwise use the Secondary 193 * Address/Data registers. 194 */ 195 if (ps->ps_b == pbus) { 196 ps->ps_addr_reg = I80312_ATU_POCCA; 197 ps->ps_data_reg = I80312_ATU_POCCD; 198 ps->ps_csr_reg = PCI_COMMAND_STATUS_REG; 199 } else { 200 ps->ps_addr_reg = I80312_ATU_SOCCA; 201 ps->ps_data_reg = I80312_ATU_SOCCD; 202 ps->ps_csr_reg = I80312_ATU_SACS; 203 } 204 205 /* 206 * If the bus # is the Primary or Secondary bus #, then use 207 * Type 0 cycles, else use Type 1. 208 * 209 * XXX We should filter out all non-private devices here! 210 * XXX How does private space interact with PCI-PCI bridges? 211 */ 212 if (ps->ps_b == pbus || ps->ps_b == sbus) { 213 if (ps->ps_d > (31 - 11)) 214 return (1); 215 ps->ps_addr_val = (1U << (ps->ps_d + 11)) | (ps->ps_f << 8) | 216 offset; 217 } else { 218 /* The tag is already in the correct format. */ 219 ps->ps_addr_val = tag | offset | 1; 220 } 221 222 return (0); 223 } 224 225 pcireg_t 226 i80312_pci_conf_read(void *v, pcitag_t tag, int offset) 227 { 228 struct i80312_softc *sc = v; 229 struct pciconf_state ps; 230 vaddr_t va; 231 pcireg_t rv; 232 u_int s; 233 234 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 235 return ((pcireg_t) -1); 236 237 PCI_CONF_LOCK(s); 238 239 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 240 ps.ps_addr_val); 241 242 va = (vaddr_t) bus_space_vaddr(sc->sc_st, sc->sc_atu_sh); 243 if (badaddr_read((void *) (va + ps.ps_data_reg), sizeof(rv), &rv)) { 244 /* 245 * Clear the Master Abort by reading the PCI 246 * Status Register. 247 */ 248 (void) bus_space_read_4(sc->sc_st, sc->sc_atu_sh, 249 ps.ps_csr_reg); 250 #if 0 251 printf("conf_read: %d/%d/%d bad address\n", 252 ps.ps_b, ps.ps_d, ps.ps_f); 253 #endif 254 rv = (pcireg_t) -1; 255 } 256 257 PCI_CONF_UNLOCK(s); 258 259 return (rv); 260 } 261 262 void 263 i80312_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 264 { 265 struct i80312_softc *sc = v; 266 struct pciconf_state ps; 267 u_int s; 268 269 if (i80312_pci_conf_setup(sc, tag, offset, &ps)) 270 return; 271 272 PCI_CONF_LOCK(s); 273 274 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_addr_reg, 275 ps.ps_addr_val); 276 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ps.ps_data_reg, val); 277 278 PCI_CONF_UNLOCK(s); 279 } 280