xref: /netbsd-src/sys/arch/arm/xscale/becc_pci.c (revision b1c86f5f087524e68db12794ee9c3e3da1ab17a0)
1 /*	$NetBSD: becc_pci.c,v 1.8 2005/12/24 20:06:52 perry Exp $	*/
2 
3 /*
4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * PCI configuration support for the ADI Engineering Big Endian Companion
40  * Chip.
41  */
42 
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: becc_pci.c,v 1.8 2005/12/24 20:06:52 perry Exp $");
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/extent.h>
50 #include <sys/malloc.h>
51 
52 #include <uvm/uvm_extern.h>
53 
54 #include <machine/bus.h>
55 
56 #include <arm/xscale/beccreg.h>
57 #include <arm/xscale/beccvar.h>
58 
59 #include <dev/pci/ppbreg.h>
60 #include <dev/pci/pciconf.h>
61 
62 #include "opt_pci.h"
63 #include "pci.h"
64 
65 void		becc_pci_attach_hook(struct device *, struct device *,
66 		    struct pcibus_attach_args *);
67 int		becc_pci_bus_maxdevs(void *, int);
68 pcitag_t	becc_pci_make_tag(void *, int, int, int);
69 void		becc_pci_decompose_tag(void *, pcitag_t, int *, int *,
70 		    int *);
71 pcireg_t	becc_pci_conf_read(void *, pcitag_t, int);
72 void		becc_pci_conf_write(void *, pcitag_t, int, pcireg_t);
73 
74 int		becc_pci_intr_map(struct pci_attach_args *,
75 		    pci_intr_handle_t *);
76 const char	*becc_pci_intr_string(void *, pci_intr_handle_t);
77 const struct evcnt *becc_pci_intr_evcnt(void *, pci_intr_handle_t);
78 void		*becc_pci_intr_establish(void *, pci_intr_handle_t,
79 		    int, int (*)(void *), void *);
80 void		becc_pci_intr_disestablish(void *, void *);
81 
82 #define	PCI_CONF_LOCK(s)	(s) = disable_interrupts(I32_bit)
83 #define	PCI_CONF_UNLOCK(s)	restore_interrupts((s))
84 
85 #if 0
86 #define DPRINTF(x) printf(x)
87 #else
88 #define DPRINTF(x)
89 #endif
90 
91 void
92 becc_pci_init(pci_chipset_tag_t pc, void *cookie)
93 {
94 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
95 	struct becc_softc *sc = cookie;
96 	struct extent *ioext, *memext;
97 #endif
98 
99 	pc->pc_conf_v = cookie;
100 	pc->pc_attach_hook = becc_pci_attach_hook;
101 	pc->pc_bus_maxdevs = becc_pci_bus_maxdevs;
102 	pc->pc_make_tag = becc_pci_make_tag;
103 	pc->pc_decompose_tag = becc_pci_decompose_tag;
104 	pc->pc_conf_read = becc_pci_conf_read;
105 	pc->pc_conf_write = becc_pci_conf_write;
106 
107 	pc->pc_intr_v = cookie;
108 	pc->pc_intr_map = becc_pci_intr_map;
109 	pc->pc_intr_string = becc_pci_intr_string;
110 	pc->pc_intr_evcnt = becc_pci_intr_evcnt;
111 	pc->pc_intr_establish = becc_pci_intr_establish;
112 	pc->pc_intr_disestablish = becc_pci_intr_disestablish;
113 
114 #if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
115 	/*
116 	 * Configure the PCI bus.
117 	 *
118 	 * XXX We need to revisit this.  We only configure the Secondary
119 	 * bus (and its children).  The bus configure code needs changes
120 	 * to support how the busses are arranged on this chip.  We also
121 	 * need to only configure devices in the private device space on
122 	 * the Secondary bus.
123 	 */
124 
125 	/* Reserve the bottom 32K of the PCI address space. */
126 	ioext  = extent_create("pciio", sc->sc_ioout_xlate + (32 * 1024),
127 	    sc->sc_ioout_xlate + (64 * 1024) - 1,
128 	    M_DEVBUF, NULL, 0, EX_NOWAIT);
129 	memext = extent_create("pcimem", sc->sc_owin_xlate[0],
130 	    sc->sc_owin_xlate[0] + BECC_PCI_MEM1_SIZE - 1,
131 	    M_DEVBUF, NULL, 0, EX_NOWAIT);
132 
133 	aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
134 	pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
135 
136 	extent_destroy(ioext);
137 	extent_destroy(memext);
138 #endif
139 }
140 
141 void
142 pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
143 {
144 }
145 
146 void
147 becc_pci_attach_hook(struct device *parent, struct device *self,
148     struct pcibus_attach_args *pba)
149 {
150 
151 	/* Nothing to do. */
152 }
153 
154 int
155 becc_pci_bus_maxdevs(void *v, int busno)
156 {
157 
158 	return (32);
159 }
160 
161 pcitag_t
162 becc_pci_make_tag(void *v, int b, int d, int f)
163 {
164 
165 	return ((b << 16) | (d << 11) | (f << 8));
166 }
167 
168 void
169 becc_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
170 {
171 
172 	if (bp != NULL)
173 		*bp = (tag >> 16) & 0xff;
174 	if (dp != NULL)
175 		*dp = (tag >> 11) & 0x1f;
176 	if (fp != NULL)
177 		*fp = (tag >> 8) & 0x7;
178 }
179 
180 struct pciconf_state {
181 	uint32_t ps_offset;
182 
183 	int ps_b, ps_d, ps_f;
184 	int ps_type;
185 };
186 
187 static int
188 becc_pci_conf_setup(struct becc_softc *sc, pcitag_t tag, int offset,
189     struct pciconf_state *ps)
190 {
191 
192 	becc_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
193 
194 	/*
195 	 * If the bus # is the same as our own, then use Type 0 cycles,
196 	 * else use Type 1.
197 	 */
198 	if (ps->ps_b == 0) {
199 		/* XXX This is a platform-specific parameter. */
200 		if (ps->ps_d > (14 - BECC_IDSEL_BIT))
201 			return (1);
202 		ps->ps_offset = (1U << (ps->ps_d + BECC_IDSEL_BIT)) |
203 		    (ps->ps_f << 8) | offset;
204 		ps->ps_type = 0;
205 	} else {
206 		/* The tag is already in the correct format. */
207 		ps->ps_offset = tag | offset | 1;
208 		ps->ps_type = 1;
209 	}
210 
211 	return (0);
212 }
213 
214 static int becc_pci_conf_cleanup(struct becc_softc *sc);
215 static int
216 becc_pci_conf_cleanup(struct becc_softc *sc)
217 {
218 	uint32_t reg;
219 	int	err=0;
220 
221 	BECC_CSR_WRITE(BECC_POCR, 0);
222 
223 	reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
224 	if (reg & 0xf9000000) {
225 		DPRINTF((" ** pci status error: %08x (%08x) **\n",
226 		    reg, reg & 0xf9000000));
227 
228 		err = 1;
229 		becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG,
230 		    reg & 0xf900ffff);
231 		reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
232 
233 		DPRINTF((" ** pci status after clearing: %08x (%08x) **\n",
234 		    reg, reg & 0xf9000000));
235 	}
236 	reg = BECC_CSR_READ(BECC_PMISR);
237 	if (reg & 0x000f000d) {
238 		DPRINTF((" ** pci master isr: %08x (%08x) **\n",
239 		    reg, reg & 0x000f000d));
240 
241 		err = 1;
242 		BECC_CSR_WRITE(BECC_PMISR, reg & 0x000f000d);
243 		reg = BECC_CSR_READ(BECC_PMISR);
244 
245 		DPRINTF((" ** pci master isr after clearing: %08x (%08x) **\n",
246 		    reg, reg & 0x000f000d));
247 	}
248 	reg = BECC_CSR_READ(BECC_PSISR);
249 	if (reg & 0x000f0210) {
250 		DPRINTF((" ** pci slave isr: %08x (%08x) **\n",
251 		    reg, reg & 0x000f0210));
252 
253 		err = 1;
254 		BECC_CSR_WRITE(BECC_PSISR, reg & 0x000f0210);
255 		reg = BECC_CSR_READ(BECC_PSISR);
256 
257 		DPRINTF((" ** pci slave isr after clearing: %08x (%08x) **\n",
258 		    reg, reg & 0x000f0210));
259 	}
260 
261 	return err;
262 }
263 
264 pcireg_t
265 becc_pci_conf_read(void *v, pcitag_t tag, int offset)
266 {
267 	struct becc_softc *sc = v;
268 	struct pciconf_state ps;
269 	vaddr_t va;
270 	pcireg_t rv;
271 	u_int s;
272 
273 	if (becc_pci_conf_setup(sc, tag, offset, &ps))
274 		return ((pcireg_t) -1);
275 
276 	/*
277 	 * Skip device 0 (the BECC itself).  We don't want it
278 	 * to appear as part of the PCI device space.
279 	 */
280 	if (ps.ps_b == 0 && ps.ps_d == 0)
281 		return ((pcireg_t) -1);
282 
283 	PCI_CONF_LOCK(s);
284 
285 	va = sc->sc_pci_cfg_base + ps.ps_offset;
286 	BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
287 
288 	if (badaddr_read((void *) va, sizeof(rv), &rv)) {
289 		/* XXX Check master/target abort? */
290 #if 0
291 		printf("conf_read: %d/%d/%d bad address\n",
292 		    ps.ps_b, ps.ps_d, ps.ps_f);
293 #endif
294 		rv = (pcireg_t) -1;
295 	}
296 
297 	if (becc_pci_conf_cleanup(sc))
298 		rv = (pcireg_t) -1;
299 
300 	PCI_CONF_UNLOCK(s);
301 
302 	return (rv);
303 }
304 
305 void
306 becc_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
307 {
308 	struct becc_softc *sc = v;
309 	struct pciconf_state ps;
310 	vaddr_t va;
311 	u_int s;
312 
313 	if (becc_pci_conf_setup(sc, tag, offset, &ps))
314 		return;
315 
316 	PCI_CONF_LOCK(s);
317 	BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
318 
319 	va = sc->sc_pci_cfg_base + ps.ps_offset;
320 
321 	*(volatile pcireg_t *)va = val;
322 
323 	becc_pci_conf_cleanup(sc);
324 
325 	PCI_CONF_UNLOCK(s);
326 }
327 
328 int
329 becc_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
330 {
331 	int irq;
332 
333 	if (pa->pa_bus == 0) {
334 		switch (pa->pa_device) {
335 		case 1: irq = ICU_PCI_INTB; break; /* Ethernet #0 */
336 		case 2: irq = ICU_PCI_INTC; break; /* Ethernet #1 */
337 		case 3:				   /* Card slot */
338 			switch (pa->pa_intrpin) {
339 			case 1:		irq = ICU_PCI_INTA; break;
340 			case 2:		irq = ICU_PCI_INTB; break;
341 			case 3:		irq = ICU_PCI_INTC; break;
342 			case 4:		irq = ICU_PCI_INTD; break;
343 			default:
344 				printf("becc_pci_intr_map: bogus pin: %d\n",
345 				    pa->pa_intrpin);
346 				return (1);
347 			}
348 			break;
349 		default:
350 			printf("becc_pci_intr_map: bogus device: %d\n",
351 			    pa->pa_device);
352 			return (1);
353 		}
354 	} else {
355 		switch (pa->pa_intrpin) {
356 		case 1:		irq = ICU_PCI_INTA; break;
357 		case 2:		irq = ICU_PCI_INTB; break;
358 		case 3:		irq = ICU_PCI_INTC; break;
359 		case 4:		irq = ICU_PCI_INTD; break;
360 		default:
361 			printf("becc_pci_intr_map: bogus pin: %d\n",
362 			    pa->pa_intrpin);
363 			return (1);
364 		}
365 	}
366 
367 	*ihp = irq;
368 	return (0);
369 }
370 
371 const char *
372 becc_pci_intr_string(void *v, pci_intr_handle_t ih)
373 {
374 
375 	return (becc_irqnames[ih]);
376 }
377 
378 const struct evcnt *
379 becc_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
380 {
381 
382 	/* XXX For now. */
383 	return (NULL);
384 }
385 
386 void *
387 becc_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
388     int (*func)(void *), void *arg)
389 {
390 
391 	return (becc_intr_establish(ih, ipl, func, arg));
392 }
393 
394 void
395 becc_pci_intr_disestablish(void *v, void *cookie)
396 {
397 
398 	becc_intr_disestablish(cookie);
399 }
400