1 /* $NetBSD: zynq_usb.c,v 1.1 2019/06/11 13:01:48 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: zynq_usb.c,v 1.1 2019/06/11 13:01:48 skrll Exp $"); 31 32 #include "opt_soc.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/kernel.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 42 #include <dev/usb/usb.h> 43 #include <dev/usb/usbdi.h> 44 #include <dev/usb/usbdivar.h> 45 #include <dev/usb/usb_mem.h> 46 47 #include <dev/usb/ehcireg.h> 48 #include <dev/usb/ehcivar.h> 49 #include <dev/usb/ulpireg.h> 50 51 #include <arm/xilinx/zynq_usbreg.h> 52 #include <arm/xilinx/zynq_usbvar.h> 53 54 #include "locators.h" 55 56 static uint8_t ulpi_read(struct zynqehci_softc *sc, int addr); 57 static void ulpi_write(struct zynqehci_softc *sc, int addr, uint8_t data); 58 static void ulpi_reset(struct zynqehci_softc *sc); 59 60 static void zynqusb_select_interface(struct zynqehci_softc *, enum zynq_usb_if); 61 static void zynqusb_init(struct ehci_softc *); 62 static void zynqusb_reset(struct zynqehci_softc *); 63 64 void 65 zynqusb_attach_common(device_t parent, device_t self, bus_space_tag_t iot, 66 bus_dma_tag_t dmat, paddr_t iobase, size_t size, int flags, 67 enum zynq_usb_if type, enum zynq_usb_role role) 68 { 69 struct zynqehci_softc *sc = device_private(self); 70 ehci_softc_t *hsc = &sc->sc_hsc; 71 uint16_t hcirev; 72 uint32_t id, hwhost, hwdevice; 73 const char *comma; 74 75 sc->sc_hsc.sc_dev = self; 76 sc->sc_iot = sc->sc_hsc.iot = iot; 77 sc->sc_iftype = type; 78 sc->sc_role = role; 79 80 hsc->sc_bus.ub_hcpriv = sc; 81 hsc->sc_bus.ub_revision = USBREV_2_0; 82 hsc->sc_flags |= EHCIF_ETTF; 83 hsc->sc_vendor_init = zynqusb_init; 84 85 aprint_normal("\n"); 86 87 if (bus_space_map(iot, iobase, size, 0, &sc->sc_ioh)) { 88 89 aprint_error_dev(self, "unable to map device\n"); 90 return; 91 } 92 93 if (bus_space_subregion(iot, sc->sc_ioh, 94 ZYNQUSB_EHCIREGS, ZYNQUSB_EHCI_SIZE - ZYNQUSB_EHCIREGS, 95 &sc->sc_hsc.ioh)) { 96 97 aprint_error_dev(self, "unable to map subregion\n"); 98 return; 99 } 100 101 id = bus_space_read_4(iot, sc->sc_ioh, ZYNQUSB_ID); 102 hcirev = bus_space_read_2(iot, sc->sc_hsc.ioh, EHCI_HCIVERSION); 103 104 aprint_normal_dev(self, 105 "Zynq USB Controller id=%d revision=%d version=%d\n", 106 (int)__SHIFTOUT(id, ZYNQUSB_ID_ID), 107 (int)__SHIFTOUT(id, ZYNQUSB_ID_REVISION), 108 (int)__SHIFTOUT(id, ZYNQUSB_ID_VERSION)); 109 aprint_normal_dev(self, "HCI revision=0x%x\n", hcirev); 110 111 hwhost = bus_space_read_4(iot, sc->sc_ioh, ZYNQUSB_HWHOST); 112 hwdevice = bus_space_read_4(iot, sc->sc_ioh, ZYNQUSB_HWDEVICE); 113 114 aprint_normal_dev(self, ""); 115 116 comma = ""; 117 if (hwhost & HWHOST_HC) { 118 int n_ports = 1 + __SHIFTOUT(hwhost, HWHOST_NPORT); 119 aprint_normal("%d host port%s", 120 n_ports, n_ports > 1 ? "s" : ""); 121 comma = ", "; 122 } 123 124 if (hwdevice & HWDEVICE_DC) { 125 int n_endpoints = __SHIFTOUT(hwdevice, HWDEVICE_DEVEP); 126 aprint_normal("%sdevice capable, %d endpoint%s", 127 comma, 128 n_endpoints, n_endpoints > 1 ? "s" : ""); 129 } 130 aprint_normal("\n"); 131 132 sc->sc_hsc.sc_bus.ub_dmatag = dmat; 133 134 sc->sc_hsc.sc_offs = bus_space_read_1(iot, sc->sc_hsc.ioh, 135 EHCI_CAPLENGTH); 136 137 zynqusb_reset(sc); 138 zynqusb_select_interface(sc, sc->sc_iftype); 139 140 if (sc->sc_iftype == ZYNQUSBC_IF_ULPI) { 141 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, 0); 142 143 aprint_normal_dev(hsc->sc_dev, 144 "ULPI phy VID 0x%04x PID 0x%04x\n", 145 (ulpi_read(sc, ULPI_VENDOR_ID_LOW) | 146 ulpi_read(sc, ULPI_VENDOR_ID_HIGH) << 8), 147 (ulpi_read(sc, ULPI_PRODUCT_ID_LOW) | 148 ulpi_read(sc, ULPI_PRODUCT_ID_HIGH) << 8)); 149 150 ulpi_reset(sc); 151 } 152 153 if (sc->sc_iftype == ZYNQUSBC_IF_ULPI) { 154 if (hsc->sc_bus.ub_revision == USBREV_2_0) { 155 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR, 156 FUNCTION_CONTROL_XCVRSELECT); 157 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, 158 FUNCTION_CONTROL_TERMSELECT); 159 } else { 160 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, 161 XCVRSELECT_FSLS); 162 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_CLEAR, 163 FUNCTION_CONTROL_TERMSELECT); 164 } 165 166 ulpi_write(sc, ULPI_OTG_CONTROL + ULPI_REG_SET, 167 OTG_CONTROL_USEEXTVBUSIND | 168 OTG_CONTROL_DRVVBUSEXT | 169 OTG_CONTROL_DRVVBUS | 170 OTG_CONTROL_CHRGVBUS); 171 } 172 173 /* Disable interrupts, so we don't get any spurious ones. */ 174 EOWRITE4(hsc, EHCI_USBINTR, 0); 175 176 /*intr_establish(intr, IPL_USB, IST_LEVEL, ehci_intr, hsc);*/ 177 178 int err = ehci_init(hsc); 179 if (err) { 180 aprint_error_dev(self, "init failed, error = %d\n", err); 181 return; 182 } 183 184 /* Attach usb device. */ 185 hsc->sc_child = config_found(self, &hsc->sc_bus, usbctlprint); 186 } 187 188 static void 189 zynqusb_select_interface(struct zynqehci_softc *sc, enum zynq_usb_if interface) 190 { 191 uint32_t reg; 192 struct ehci_softc *hsc = &sc->sc_hsc; 193 194 reg = EOREAD4(hsc, EHCI_PORTSC(1)); 195 reg &= ~(PORTSC_PTS | PORTSC_PTW); 196 switch (interface) { 197 case ZYNQUSBC_IF_UTMI_WIDE: 198 reg |= PORTSC_PTW_16; 199 case ZYNQUSBC_IF_UTMI: 200 reg |= PORTSC_PTS_UTMI; 201 break; 202 case ZYNQUSBC_IF_PHILIPS: 203 reg |= PORTSC_PTS_PHILIPS; 204 break; 205 case ZYNQUSBC_IF_ULPI: 206 reg |= PORTSC_PTS_ULPI; 207 break; 208 case ZYNQUSBC_IF_SERIAL: 209 reg |= PORTSC_PTS_SERIAL; 210 break; 211 } 212 EOWRITE4(hsc, EHCI_PORTSC(1), reg); 213 } 214 215 static uint32_t 216 ulpi_wakeup(struct zynqehci_softc *sc, int tout) 217 { 218 uint32_t ulpi_view; 219 int i = 0; 220 ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW); 221 222 if ( !(ulpi_view & ULPI_SS) ) { 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 224 ZYNQUSB_ULPIVIEW, ULPI_WU); 225 for (i = 0; (tout < 0) || (i < tout); i++) { 226 ulpi_view = bus_space_read_4(sc->sc_iot, 227 sc->sc_ioh, ZYNQUSB_ULPIVIEW); 228 if ( !(ulpi_view & ULPI_WU) ) 229 break; 230 delay(1); 231 }; 232 } 233 234 if ((tout > 0) && (i >= tout)) { 235 aprint_error_dev(sc->sc_hsc.sc_dev, "%s: timeout\n", __func__); 236 } 237 238 return ulpi_view; 239 } 240 241 static uint32_t 242 ulpi_wait(struct zynqehci_softc *sc, int tout) 243 { 244 uint32_t ulpi_view; 245 int i; 246 ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW); 247 248 for (i = 0; (tout < 0) | (i < tout); i++) { 249 ulpi_view = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 250 ZYNQUSB_ULPIVIEW); 251 if (!(ulpi_view & ULPI_RUN)) 252 break; 253 delay(1); 254 } 255 256 if ((tout > 0) && (i >= tout)) { 257 aprint_error_dev(sc->sc_hsc.sc_dev, "%s: timeout\n", __func__); 258 } 259 260 return ulpi_view; 261 } 262 263 #define TIMEOUT 100000 264 265 static uint8_t 266 ulpi_read(struct zynqehci_softc *sc, int addr) 267 { 268 uint32_t data; 269 270 ulpi_wakeup(sc, TIMEOUT); 271 272 data = ULPI_RUN | __SHIFTIN(addr, ULPI_ADDR); 273 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, data); 274 275 data = ulpi_wait(sc, TIMEOUT); 276 277 return __SHIFTOUT(data, ULPI_DATRD); 278 } 279 280 static void 281 ulpi_write(struct zynqehci_softc *sc, int addr, uint8_t data) 282 { 283 uint32_t reg; 284 285 ulpi_wakeup(sc, TIMEOUT); 286 287 reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR); 288 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_ULPIVIEW, reg); 289 290 ulpi_wait(sc, TIMEOUT); 291 292 return; 293 } 294 295 static void 296 ulpi_reset(struct zynqehci_softc *sc) 297 { 298 uint8_t data; 299 int timo = 1000 * 1000; /* XXXX: 1sec */ 300 301 ulpi_write(sc, ULPI_FUNCTION_CONTROL + ULPI_REG_SET, 302 FUNCTION_CONTROL_RESET /*0x20*/); 303 do { 304 data = ulpi_read(sc, ULPI_FUNCTION_CONTROL); 305 if (!(data & FUNCTION_CONTROL_RESET)) 306 break; 307 delay(100); 308 timo -= 100; 309 } while (timo > 0); 310 if (timo <= 0) { 311 aprint_error_dev(sc->sc_hsc.sc_dev, "%s: reset failed!!\n", 312 __func__); 313 return; 314 } 315 316 return; 317 } 318 319 static void 320 zynqusb_reset(struct zynqehci_softc *sc) 321 { 322 uint32_t reg; 323 int i; 324 struct ehci_softc *hsc = &sc->sc_hsc; 325 #define RESET_TIMEOUT 100 326 reg = EOREAD4(hsc, EHCI_USBCMD); 327 reg &= ~EHCI_CMD_RS; 328 EOWRITE4(hsc, EHCI_USBCMD, reg); 329 330 for (i=0; i < RESET_TIMEOUT; ++i) { 331 reg = EOREAD4(hsc, EHCI_USBCMD); 332 if ((reg & EHCI_CMD_RS) == 0) 333 break; 334 usb_delay_ms(&hsc->sc_bus, 1); 335 } 336 337 EOWRITE4(hsc, EHCI_USBCMD, reg | EHCI_CMD_HCRESET); 338 for (i = 0; i < RESET_TIMEOUT; i++) { 339 reg = EOREAD4(hsc, EHCI_USBCMD); 340 if ((reg & EHCI_CMD_HCRESET) == 0) 341 break; 342 usb_delay_ms(&hsc->sc_bus, 1); 343 } 344 if (i >= RESET_TIMEOUT) { 345 aprint_error_dev(hsc->sc_dev, "reset timeout (%x)\n", reg); 346 } 347 348 usb_delay_ms(&hsc->sc_bus, 100); 349 } 350 351 static void 352 zynqusb_init(struct ehci_softc *hsc) 353 { 354 struct zynqehci_softc *sc = device_private(hsc->sc_dev); 355 uint32_t reg; 356 357 reg = EOREAD4(hsc, EHCI_PORTSC(1)); 358 reg &= ~(EHCI_PS_CSC | EHCI_PS_PEC | EHCI_PS_OCC); 359 reg |= EHCI_PS_PP | EHCI_PS_PE; 360 EOWRITE4(hsc, EHCI_PORTSC(1), reg); 361 362 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC); 363 reg |= OTGSC_IDPU; 364 reg |= OTGSC_DPIE | OTGSC_IDIE; 365 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_OTGSC, reg); 366 367 reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE); 368 reg &= ~USBMODE_CM; 369 reg |= USBMODE_CM_HOST; 370 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ZYNQUSB_USBMODE, reg); 371 } 372