1 /* $NetBSD: vfp_init.c,v 1.62 2019/04/06 08:48:53 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2008 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 25 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "opt_cputypes.h" 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.62 2019/04/06 08:48:53 skrll Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/types.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/proc.h> 42 #include <sys/cpu.h> 43 44 #include <arm/locore.h> 45 #include <arm/pcb.h> 46 #include <arm/undefined.h> 47 #include <arm/vfpreg.h> 48 #include <arm/mcontext.h> 49 50 #include <uvm/uvm_extern.h> /* for pmap.h */ 51 52 #ifdef FPU_VFP 53 54 #ifdef CPU_CORTEX 55 #define SETFPU __asm(".fpu\tvfpv4") 56 #else 57 #define SETFPU __asm(".fpu\tvfp") 58 #endif 59 SETFPU; 60 61 /* FLDMD <X>, {d0-d15} */ 62 static inline void 63 load_vfpregs_lo(const uint64_t *p) 64 { 65 SETFPU; 66 __asm __volatile("vldmia\t%0, {d0-d15}" :: "r" (p) : "memory"); 67 } 68 69 /* FSTMD <X>, {d0-d15} */ 70 static inline void 71 save_vfpregs_lo(uint64_t *p) 72 { 73 SETFPU; 74 __asm __volatile("vstmia\t%0, {d0-d15}" :: "r" (p) : "memory"); 75 } 76 77 #ifdef CPU_CORTEX 78 /* FLDMD <X>, {d16-d31} */ 79 static inline void 80 load_vfpregs_hi(const uint64_t *p) 81 { 82 SETFPU; 83 __asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory"); 84 } 85 86 /* FLDMD <X>, {d16-d31} */ 87 static inline void 88 save_vfpregs_hi(uint64_t *p) 89 { 90 SETFPU; 91 __asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory"); 92 } 93 #endif 94 95 static inline void 96 load_vfpregs(const struct vfpreg *fregs) 97 { 98 load_vfpregs_lo(fregs->vfp_regs); 99 #ifdef CPU_CORTEX 100 #ifdef CPU_ARM11 101 switch (curcpu()->ci_vfp_id) { 102 case FPU_VFP_CORTEXA5: 103 case FPU_VFP_CORTEXA7: 104 case FPU_VFP_CORTEXA8: 105 case FPU_VFP_CORTEXA9: 106 case FPU_VFP_CORTEXA15: 107 case FPU_VFP_CORTEXA15_QEMU: 108 case FPU_VFP_CORTEXA53: 109 case FPU_VFP_CORTEXA57: 110 #endif 111 load_vfpregs_hi(fregs->vfp_regs); 112 #ifdef CPU_ARM11 113 break; 114 } 115 #endif 116 #endif 117 } 118 119 static inline void 120 save_vfpregs(struct vfpreg *fregs) 121 { 122 save_vfpregs_lo(fregs->vfp_regs); 123 #ifdef CPU_CORTEX 124 #ifdef CPU_ARM11 125 switch (curcpu()->ci_vfp_id) { 126 case FPU_VFP_CORTEXA5: 127 case FPU_VFP_CORTEXA7: 128 case FPU_VFP_CORTEXA8: 129 case FPU_VFP_CORTEXA9: 130 case FPU_VFP_CORTEXA15: 131 case FPU_VFP_CORTEXA15_QEMU: 132 case FPU_VFP_CORTEXA53: 133 case FPU_VFP_CORTEXA57: 134 #endif 135 save_vfpregs_hi(fregs->vfp_regs); 136 #ifdef CPU_ARM11 137 break; 138 } 139 #endif 140 #endif 141 } 142 143 /* The real handler for VFP bounces. */ 144 static int vfp_handler(u_int, u_int, trapframe_t *, int); 145 #ifdef CPU_CORTEX 146 static int neon_handler(u_int, u_int, trapframe_t *, int); 147 #endif 148 149 static void vfp_state_load(lwp_t *, u_int); 150 static void vfp_state_save(lwp_t *); 151 static void vfp_state_release(lwp_t *); 152 153 const pcu_ops_t arm_vfp_ops = { 154 .pcu_id = PCU_FPU, 155 .pcu_state_save = vfp_state_save, 156 .pcu_state_load = vfp_state_load, 157 .pcu_state_release = vfp_state_release, 158 }; 159 160 /* determine what bits can be changed */ 161 uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM; 162 /* default to run fast */ 163 uint32_t vfp_fpscr_default = (VFP_FPSCR_DN | VFP_FPSCR_FZ | VFP_FPSCR_RN); 164 165 /* 166 * Used to test for a VFP. The following function is installed as a coproc10 167 * handler on the undefined instruction vector and then we issue a VFP 168 * instruction. If undefined_test is non zero then the VFP did not handle 169 * the instruction so must be absent, or disabled. 170 */ 171 172 static int undefined_test; 173 174 static int 175 vfp_test(u_int address, u_int insn, trapframe_t *frame, int fault_code) 176 { 177 178 frame->tf_pc += INSN_SIZE; 179 ++undefined_test; 180 return 0; 181 } 182 183 #else 184 /* determine what bits can be changed */ 185 uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM|VFP_FPSCR_RMODE; 186 #endif /* FPU_VFP */ 187 188 static int 189 vfp_fpscr_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 190 { 191 struct lwp * const l = curlwp; 192 const u_int regno = (insn >> 12) & 0xf; 193 /* 194 * Only match move to/from the FPSCR register and we 195 * can't be using the SP,LR,PC as a source. 196 */ 197 if ((insn & 0xffef0fff) != 0xeee10a10 || regno > 12) 198 return 1; 199 200 struct pcb * const pcb = lwp_getpcb(l); 201 202 #ifdef FPU_VFP 203 /* 204 * If FPU is valid somewhere, let's just reenable VFP and 205 * retry the instruction (only safe thing to do since the 206 * pcb has a stale copy). 207 */ 208 if (pcb->pcb_vfp.vfp_fpexc & VFP_FPEXC_EN) 209 return 1; 210 211 if (__predict_false(!vfp_used_p(l))) { 212 pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default; 213 } 214 #endif 215 216 /* 217 * We now know the pcb has the saved copy. 218 */ 219 register_t * const regp = &frame->tf_r0 + regno; 220 if (insn & 0x00100000) { 221 *regp = pcb->pcb_vfp.vfp_fpscr; 222 } else { 223 pcb->pcb_vfp.vfp_fpscr &= ~vfp_fpscr_changable; 224 pcb->pcb_vfp.vfp_fpscr |= *regp & vfp_fpscr_changable; 225 } 226 227 curcpu()->ci_vfp_evs[0].ev_count++; 228 229 frame->tf_pc += INSN_SIZE; 230 return 0; 231 } 232 233 #ifndef FPU_VFP 234 /* 235 * If we don't want VFP support, we still need to handle emulating VFP FPSCR 236 * instructions. 237 */ 238 void 239 vfp_attach(struct cpu_info *ci) 240 { 241 if (CPU_IS_PRIMARY(ci)) { 242 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 243 } 244 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_TRAP, NULL, 245 ci->ci_cpuname, "vfp fpscr traps"); 246 } 247 248 #else 249 void 250 vfp_attach(struct cpu_info *ci) 251 { 252 const char *model = NULL; 253 254 if (CPU_ID_ARM11_P(ci->ci_arm_cpuid) 255 || CPU_ID_MV88SV58XX_P(ci->ci_arm_cpuid) 256 || CPU_ID_CORTEX_P(ci->ci_arm_cpuid)) { 257 #if 0 258 const uint32_t nsacr = armreg_nsacr_read(); 259 const uint32_t nsacr_vfp = __BITS(VFP_COPROC,VFP_COPROC2); 260 if ((nsacr & nsacr_vfp) != nsacr_vfp) { 261 aprint_normal_dev(ci->ci_dev, 262 "VFP access denied (NSACR=%#x)\n", nsacr); 263 if (CPU_IS_PRIMARY(ci)) 264 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 265 ci->ci_vfp_id = 0; 266 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], 267 EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname, 268 "vfp fpscr traps"); 269 return; 270 } 271 #endif 272 const uint32_t cpacr_vfp = CPACR_CPn(VFP_COPROC); 273 const uint32_t cpacr_vfp2 = CPACR_CPn(VFP_COPROC2); 274 275 /* 276 * We first need to enable access to the coprocessors. 277 */ 278 uint32_t cpacr = armreg_cpacr_read(); 279 cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp); 280 cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2); 281 armreg_cpacr_write(cpacr); 282 283 arm_isb(); 284 285 /* 286 * If we could enable them, then they exist. 287 */ 288 cpacr = armreg_cpacr_read(); 289 bool vfp_p = __SHIFTOUT(cpacr, cpacr_vfp2) == CPACR_ALL 290 && __SHIFTOUT(cpacr, cpacr_vfp) == CPACR_ALL; 291 if (!vfp_p) { 292 aprint_normal_dev(ci->ci_dev, 293 "VFP access denied (CPACR=%#x)\n", cpacr); 294 if (CPU_IS_PRIMARY(ci)) 295 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 296 ci->ci_vfp_id = 0; 297 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], 298 EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname, 299 "vfp fpscr traps"); 300 return; 301 } 302 } 303 304 void *uh = install_coproc_handler(VFP_COPROC, vfp_test); 305 306 undefined_test = 0; 307 308 const uint32_t fpsid = armreg_fpsid_read(); 309 310 remove_coproc_handler(uh); 311 312 if (undefined_test != 0) { 313 aprint_normal_dev(ci->ci_dev, "No VFP detected\n"); 314 if (CPU_IS_PRIMARY(ci)) 315 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 316 ci->ci_vfp_id = 0; 317 return; 318 } 319 320 ci->ci_vfp_id = fpsid; 321 switch (fpsid & ~ VFP_FPSID_REV_MSK) { 322 case FPU_VFP10_ARM10E: 323 model = "VFP10 R1"; 324 break; 325 case FPU_VFP11_ARM11: 326 model = "VFP11"; 327 break; 328 case FPU_VFP_MV88SV58XX: 329 model = "VFP3"; 330 break; 331 case FPU_VFP_CORTEXA5: 332 case FPU_VFP_CORTEXA7: 333 case FPU_VFP_CORTEXA8: 334 case FPU_VFP_CORTEXA9: 335 case FPU_VFP_CORTEXA15: 336 case FPU_VFP_CORTEXA15_QEMU: 337 case FPU_VFP_CORTEXA53: 338 case FPU_VFP_CORTEXA57: 339 if (armreg_cpacr_read() & CPACR_V7_ASEDIS) { 340 model = "VFP 4.0+"; 341 } else { 342 model = "NEON MPE (VFP 3.0+)"; 343 cpu_neon_present = 1; 344 } 345 break; 346 default: 347 aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %#x\n", 348 fpsid); 349 if (CPU_IS_PRIMARY(ci)) 350 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 351 vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM 352 |VFP_FPSCR_RMODE; 353 vfp_fpscr_default = 0; 354 return; 355 } 356 357 cpu_fpu_present = 1; 358 cpu_media_and_vfp_features[0] = armreg_mvfr0_read(); 359 cpu_media_and_vfp_features[1] = armreg_mvfr1_read(); 360 if (fpsid != 0) { 361 uint32_t f0 = armreg_mvfr0_read(); 362 uint32_t f1 = armreg_mvfr1_read(); 363 aprint_normal("vfp%d at %s: %s%s%s%s%s\n", 364 device_unit(ci->ci_dev), 365 device_xname(ci->ci_dev), 366 model, 367 ((f0 & ARM_MVFR0_ROUNDING_MASK) ? ", rounding" : ""), 368 ((f0 & ARM_MVFR0_EXCEPT_MASK) ? ", exceptions" : ""), 369 ((f1 & ARM_MVFR1_D_NAN_MASK) ? ", NaN propagation" : ""), 370 ((f1 & ARM_MVFR1_FTZ_MASK) ? ", denormals" : "")); 371 aprint_debug("vfp%d: mvfr: [0]=%#x [1]=%#x\n", 372 device_unit(ci->ci_dev), f0, f1); 373 if (CPU_IS_PRIMARY(ci)) { 374 if (f0 & ARM_MVFR0_ROUNDING_MASK) { 375 vfp_fpscr_changable |= VFP_FPSCR_RMODE; 376 } 377 if (f1 & ARM_MVFR0_EXCEPT_MASK) { 378 vfp_fpscr_changable |= VFP_FPSCR_ESUM; 379 } 380 // If hardware supports propagation of NaNs, select it. 381 if (f1 & ARM_MVFR1_D_NAN_MASK) { 382 vfp_fpscr_default &= ~VFP_FPSCR_DN; 383 vfp_fpscr_changable |= VFP_FPSCR_DN; 384 } 385 // If hardware supports denormalized numbers, use it. 386 if (cpu_media_and_vfp_features[1] & ARM_MVFR1_FTZ_MASK) { 387 vfp_fpscr_default &= ~VFP_FPSCR_FZ; 388 vfp_fpscr_changable |= VFP_FPSCR_FZ; 389 } 390 } 391 } 392 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_MISC, NULL, 393 ci->ci_cpuname, "vfp coproc use"); 394 evcnt_attach_dynamic(&ci->ci_vfp_evs[1], EVCNT_TYPE_MISC, NULL, 395 ci->ci_cpuname, "vfp coproc re-use"); 396 evcnt_attach_dynamic(&ci->ci_vfp_evs[2], EVCNT_TYPE_TRAP, NULL, 397 ci->ci_cpuname, "vfp coproc fault"); 398 if (CPU_IS_PRIMARY(ci)) { 399 install_coproc_handler(VFP_COPROC, vfp_handler); 400 install_coproc_handler(VFP_COPROC2, vfp_handler); 401 #ifdef CPU_CORTEX 402 if (cpu_neon_present) 403 install_coproc_handler(CORE_UNKNOWN_HANDLER, neon_handler); 404 #endif 405 } 406 } 407 408 /* The real handler for VFP bounces. */ 409 static int 410 vfp_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 411 { 412 struct cpu_info * const ci = curcpu(); 413 414 /* This shouldn't ever happen. */ 415 if (fault_code != FAULT_USER) 416 panic("VFP fault at %#x in non-user mode", frame->tf_pc); 417 418 if (ci->ci_vfp_id == 0) { 419 /* No VFP detected, just fault. */ 420 return 1; 421 } 422 423 /* 424 * If we already own the FPU and it's enabled (and no exception), raise 425 * SIGILL. If there is an exception, drop through to raise a SIGFPE. 426 */ 427 if (curcpu()->ci_pcu_curlwp[PCU_FPU] == curlwp 428 && (armreg_fpexc_read() & (VFP_FPEXC_EX|VFP_FPEXC_EN)) == VFP_FPEXC_EN) 429 return 1; 430 431 /* 432 * Make sure we own the FP. 433 */ 434 pcu_load(&arm_vfp_ops); 435 436 uint32_t fpexc = armreg_fpexc_read(); 437 if (fpexc & VFP_FPEXC_EX) { 438 ksiginfo_t ksi; 439 KASSERT(fpexc & VFP_FPEXC_EN); 440 441 curcpu()->ci_vfp_evs[2].ev_count++; 442 443 /* 444 * Need the clear the exception condition so any signal 445 * and future use can proceed. 446 */ 447 armreg_fpexc_write(fpexc & ~(VFP_FPEXC_EX|VFP_FPEXC_FSUM)); 448 449 pcu_save(&arm_vfp_ops, curlwp); 450 451 /* 452 * XXX Need to emulate bounce instructions here to get correct 453 * XXX exception codes, etc. 454 */ 455 KSI_INIT_TRAP(&ksi); 456 ksi.ksi_signo = SIGFPE; 457 if (fpexc & VFP_FPEXC_IXF) 458 ksi.ksi_code = FPE_FLTRES; 459 else if (fpexc & VFP_FPEXC_UFF) 460 ksi.ksi_code = FPE_FLTUND; 461 else if (fpexc & VFP_FPEXC_OFF) 462 ksi.ksi_code = FPE_FLTOVF; 463 else if (fpexc & VFP_FPEXC_DZF) 464 ksi.ksi_code = FPE_FLTDIV; 465 else if (fpexc & VFP_FPEXC_IOF) 466 ksi.ksi_code = FPE_FLTINV; 467 ksi.ksi_addr = (uint32_t *)address; 468 ksi.ksi_trap = 0; 469 trapsignal(curlwp, &ksi); 470 return 0; 471 } 472 473 /* Need to restart the faulted instruction. */ 474 // frame->tf_pc -= INSN_SIZE; 475 return 0; 476 } 477 478 #ifdef CPU_CORTEX 479 /* The real handler for NEON bounces. */ 480 static int 481 neon_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 482 { 483 struct cpu_info * const ci = curcpu(); 484 485 if (ci->ci_vfp_id == 0) 486 /* No VFP detected, just fault. */ 487 return 1; 488 489 if ((insn & 0xfe000000) != 0xf2000000 490 && (insn & 0xfe000000) != 0xf4000000) 491 /* Not NEON instruction, just fault. */ 492 return 1; 493 494 /* This shouldn't ever happen. */ 495 if (fault_code != FAULT_USER) 496 panic("NEON fault in non-user mode"); 497 498 /* if we already own the FPU and it's enabled, raise SIGILL */ 499 if (curcpu()->ci_pcu_curlwp[PCU_FPU] == curlwp 500 && (armreg_fpexc_read() & VFP_FPEXC_EN) != 0) 501 return 1; 502 503 pcu_load(&arm_vfp_ops); 504 505 /* Need to restart the faulted instruction. */ 506 // frame->tf_pc -= INSN_SIZE; 507 return 0; 508 } 509 #endif 510 511 static void 512 vfp_state_load(lwp_t *l, u_int flags) 513 { 514 struct pcb * const pcb = lwp_getpcb(l); 515 struct vfpreg * const fregs = &pcb->pcb_vfp; 516 517 /* 518 * Instrument VFP usage -- if a process has not previously 519 * used the VFP, mark it as having used VFP for the first time, 520 * and count this event. 521 * 522 * If a process has used the VFP, count a "used VFP, and took 523 * a trap to use it again" event. 524 */ 525 if (__predict_false((flags & PCU_VALID) == 0)) { 526 curcpu()->ci_vfp_evs[0].ev_count++; 527 pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default; 528 } else { 529 curcpu()->ci_vfp_evs[1].ev_count++; 530 } 531 532 KASSERT((armreg_fpexc_read() & VFP_FPEXC_EN) == 0); 533 /* 534 * If the VFP is already enabled we must be bouncing an instruction. 535 */ 536 if (flags & PCU_REENABLE) { 537 uint32_t fpexc = armreg_fpexc_read(); 538 armreg_fpexc_write(fpexc | VFP_FPEXC_EN); 539 fregs->vfp_fpexc |= VFP_FPEXC_EN; 540 return; 541 } 542 KASSERT((fregs->vfp_fpexc & VFP_FPEXC_EN) == 0); 543 544 /* 545 * Load and Enable the VFP (so that we can write the registers). 546 */ 547 fregs->vfp_fpexc |= VFP_FPEXC_EN; 548 armreg_fpexc_write(fregs->vfp_fpexc); 549 KASSERT(curcpu()->ci_pcu_curlwp[PCU_FPU] == NULL); 550 KASSERT(l->l_pcu_cpu[PCU_FPU] == NULL); 551 552 load_vfpregs(fregs); 553 armreg_fpscr_write(fregs->vfp_fpscr); 554 555 if (fregs->vfp_fpexc & VFP_FPEXC_EX) { 556 /* Need to restore the exception handling state. */ 557 armreg_fpinst_write(fregs->vfp_fpinst); 558 if (fregs->vfp_fpexc & VFP_FPEXC_FP2V) 559 armreg_fpinst2_write(fregs->vfp_fpinst2); 560 } 561 } 562 563 void 564 vfp_state_save(lwp_t *l) 565 { 566 struct pcb * const pcb = lwp_getpcb(l); 567 struct vfpreg * const fregs = &pcb->pcb_vfp; 568 uint32_t fpexc = armreg_fpexc_read(); 569 570 KASSERT(curcpu()->ci_pcu_curlwp[PCU_FPU] == l); 571 KASSERT(curcpu() == l->l_pcu_cpu[PCU_FPU]); 572 KASSERT(curlwp == l || curlwp->l_pcu_cpu[PCU_FPU] != curcpu()); 573 /* 574 * Enable the VFP (so we can read the registers). 575 * Make sure the exception bit is cleared so that we can 576 * safely dump the registers. 577 */ 578 armreg_fpexc_write((fpexc | VFP_FPEXC_EN) & ~VFP_FPEXC_EX); 579 580 fregs->vfp_fpexc = fpexc; 581 if (fpexc & VFP_FPEXC_EX) { 582 /* Need to save the exception handling state */ 583 fregs->vfp_fpinst = armreg_fpinst_read(); 584 if (fpexc & VFP_FPEXC_FP2V) 585 fregs->vfp_fpinst2 = armreg_fpinst2_read(); 586 } 587 fregs->vfp_fpscr = armreg_fpscr_read(); 588 save_vfpregs(fregs); 589 590 /* Disable the VFP. */ 591 armreg_fpexc_write(fpexc & ~VFP_FPEXC_EN); 592 } 593 594 void 595 vfp_state_release(lwp_t *l) 596 { 597 struct pcb * const pcb = lwp_getpcb(l); 598 599 /* 600 * Now mark the VFP as disabled (and our state 601 * has been already saved or is being discarded). 602 */ 603 pcb->pcb_vfp.vfp_fpexc &= ~VFP_FPEXC_EN; 604 605 /* 606 * Turn off the FPU so the next time a VFP instruction is issued 607 * an exception happens. We don't know if this LWP's state was 608 * loaded but if we turned off the FPU for some other LWP, when 609 * pcu_load invokes vfp_state_load it will see that VFP_FPEXC_EN 610 * is still set so it just restore fpexc and return since its 611 * contents are still sitting in the VFP. 612 */ 613 armreg_fpexc_write(armreg_fpexc_read() & ~VFP_FPEXC_EN); 614 } 615 616 void 617 vfp_savecontext(lwp_t *l) 618 { 619 pcu_save(&arm_vfp_ops, l); 620 } 621 622 void 623 vfp_discardcontext(lwp_t *l, bool used_p) 624 { 625 pcu_discard(&arm_vfp_ops, l, used_p); 626 } 627 628 bool 629 vfp_used_p(const lwp_t *l) 630 { 631 return pcu_valid_p(&arm_vfp_ops, l); 632 } 633 634 void 635 vfp_getcontext(struct lwp *l, mcontext_t *mcp, int *flagsp) 636 { 637 if (vfp_used_p(l)) { 638 const struct pcb * const pcb = lwp_getpcb(l); 639 640 pcu_save(&arm_vfp_ops, l); 641 mcp->__fpu.__vfpregs.__vfp_fpscr = pcb->pcb_vfp.vfp_fpscr; 642 memcpy(mcp->__fpu.__vfpregs.__vfp_fstmx, pcb->pcb_vfp.vfp_regs, 643 sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx)); 644 *flagsp |= _UC_FPU|_UC_ARM_VFP; 645 } 646 } 647 648 void 649 vfp_setcontext(struct lwp *l, const mcontext_t *mcp) 650 { 651 struct pcb * const pcb = lwp_getpcb(l); 652 653 pcu_discard(&arm_vfp_ops, l, true); 654 pcb->pcb_vfp.vfp_fpscr = mcp->__fpu.__vfpregs.__vfp_fpscr; 655 memcpy(pcb->pcb_vfp.vfp_regs, mcp->__fpu.__vfpregs.__vfp_fstmx, 656 sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx)); 657 } 658 659 #endif /* FPU_VFP */ 660