xref: /netbsd-src/sys/arch/arm/vfp/vfp_init.c (revision 6cf6fe02a981b55727c49c3d37b0d8191a98c0ee)
1 /*      $NetBSD: vfp_init.c,v 1.41 2014/07/18 22:54:53 matt Exp $ */
2 
3 /*
4  * Copyright (c) 2008 ARM Ltd
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The name of the company may not be used to endorse or promote
16  *    products derived from this software without specific prior written
17  *    permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR
20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY
23  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
25  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/systm.h>
35 #include <sys/device.h>
36 #include <sys/proc.h>
37 #include <sys/cpu.h>
38 
39 #include <arm/locore.h>
40 #include <arm/pcb.h>
41 #include <arm/undefined.h>
42 #include <arm/vfpreg.h>
43 #include <arm/mcontext.h>
44 
45 #include <uvm/uvm_extern.h>		/* for pmap.h */
46 
47 #ifdef FPU_VFP
48 
49 #ifdef CPU_CORTEX
50 __asm(".fpu\tvfpv4");
51 #else
52 __asm(".fpu\tvfp");
53 #endif
54 
55 /* FLDMD <X>, {d0-d15} */
56 static inline void
57 load_vfpregs_lo(const uint64_t *p)
58 {
59 	__asm __volatile("vldmia %0, {d0-d15}" :: "r" (p) : "memory");
60 }
61 
62 /* FSTMD <X>, {d0-d15} */
63 static inline void
64 save_vfpregs_lo(uint64_t *p)
65 {
66 	__asm __volatile("vstmia %0, {d0-d15}" :: "r" (p) : "memory");
67 }
68 
69 #ifdef CPU_CORTEX
70 /* FLDMD <X>, {d16-d31} */
71 static inline void
72 load_vfpregs_hi(const uint64_t *p)
73 {
74 	__asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
75 }
76 
77 /* FLDMD <X>, {d16-d31} */
78 static inline void
79 save_vfpregs_hi(uint64_t *p)
80 {
81 	__asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
82 }
83 #endif
84 
85 static inline void
86 load_vfpregs(const struct vfpreg *fregs)
87 {
88 	load_vfpregs_lo(fregs->vfp_regs);
89 #ifdef CPU_CORTEX
90 #ifdef CPU_ARM11
91 	switch (curcpu()->ci_vfp_id) {
92 	case FPU_VFP_CORTEXA5:
93 	case FPU_VFP_CORTEXA7:
94 	case FPU_VFP_CORTEXA8:
95 	case FPU_VFP_CORTEXA9:
96 	case FPU_VFP_CORTEXA15:
97 #endif
98 		load_vfpregs_hi(fregs->vfp_regs);
99 #ifdef CPU_ARM11
100 		break;
101 	}
102 #endif
103 #endif
104 }
105 
106 static inline void
107 save_vfpregs(struct vfpreg *fregs)
108 {
109 	save_vfpregs_lo(fregs->vfp_regs);
110 #ifdef CPU_CORTEX
111 #ifdef CPU_ARM11
112 	switch (curcpu()->ci_vfp_id) {
113 	case FPU_VFP_CORTEXA5:
114 	case FPU_VFP_CORTEXA7:
115 	case FPU_VFP_CORTEXA8:
116 	case FPU_VFP_CORTEXA9:
117 	case FPU_VFP_CORTEXA15:
118 #endif
119 		save_vfpregs_hi(fregs->vfp_regs);
120 #ifdef CPU_ARM11
121 		break;
122 	}
123 #endif
124 #endif
125 }
126 
127 /* The real handler for VFP bounces.  */
128 static int vfp_handler(u_int, u_int, trapframe_t *, int);
129 #ifdef CPU_CORTEX
130 static int neon_handler(u_int, u_int, trapframe_t *, int);
131 #endif
132 
133 static void vfp_state_load(lwp_t *, u_int);
134 static void vfp_state_save(lwp_t *);
135 static void vfp_state_release(lwp_t *);
136 
137 const pcu_ops_t arm_vfp_ops = {
138 	.pcu_id = PCU_FPU,
139 	.pcu_state_save = vfp_state_save,
140 	.pcu_state_load = vfp_state_load,
141 	.pcu_state_release = vfp_state_release,
142 };
143 
144 /* determine what bits can be changed */
145 uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM;
146 /* default to run fast */
147 uint32_t vfp_fpscr_default = (VFP_FPSCR_DN | VFP_FPSCR_FZ | VFP_FPSCR_RN);
148 
149 /*
150  * Used to test for a VFP. The following function is installed as a coproc10
151  * handler on the undefined instruction vector and then we issue a VFP
152  * instruction. If undefined_test is non zero then the VFP did not handle
153  * the instruction so must be absent, or disabled.
154  */
155 
156 static int undefined_test;
157 
158 static int
159 vfp_test(u_int address, u_int insn, trapframe_t *frame, int fault_code)
160 {
161 
162 	frame->tf_pc += INSN_SIZE;
163 	++undefined_test;
164 	return 0;
165 }
166 
167 #else
168 /* determine what bits can be changed */
169 uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM|VFP_FPSCR_RMODE;
170 #endif /* FPU_VFP */
171 
172 static int
173 vfp_fpscr_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code)
174 {
175 	struct lwp * const l = curlwp;
176 	const u_int regno = (insn >> 12) & 0xf;
177 	/*
178 	 * Only match move to/from the FPSCR register and we
179 	 * can't be using the SP,LR,PC as a source.
180 	 */
181 	if ((insn & 0xffef0fff) != 0xeee10a10 || regno > 12)
182 		return 1;
183 
184 	struct pcb * const pcb = lwp_getpcb(l);
185 
186 #ifdef FPU_VFP
187 	/*
188 	 * If FPU is valid somewhere, let's just reenable VFP and
189 	 * retry the instruction (only safe thing to do since the
190 	 * pcb has a stale copy).
191 	 */
192 	if (pcb->pcb_vfp.vfp_fpexc & VFP_FPEXC_EN)
193 		return 1;
194 
195 	if (__predict_false(!vfp_used_p())) {
196 		pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default;
197 	}
198 #endif
199 
200 	/*
201 	 * We now know the pcb has the saved copy.
202 	 */
203 	register_t * const regp = &frame->tf_r0 + regno;
204 	if (insn & 0x00100000) {
205 		*regp = pcb->pcb_vfp.vfp_fpscr;
206 	} else {
207 		pcb->pcb_vfp.vfp_fpscr &= ~vfp_fpscr_changable;
208 		pcb->pcb_vfp.vfp_fpscr |= *regp & vfp_fpscr_changable;
209 	}
210 
211 	curcpu()->ci_vfp_evs[0].ev_count++;
212 
213 	frame->tf_pc += INSN_SIZE;
214 	return 0;
215 }
216 
217 #ifndef FPU_VFP
218 /*
219  * If we don't want VFP support, we still need to handle emulating VFP FPSCR
220  * instructions.
221  */
222 void
223 vfp_attach(struct cpu_info *ci)
224 {
225 	if (CPU_IS_PRIMARY(ci)) {
226 		install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
227 	}
228 	evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_TRAP, NULL,
229 	    ci->ci_cpuname, "vfp fpscr traps");
230 }
231 
232 #else
233 void
234 vfp_attach(struct cpu_info *ci)
235 {
236 	const char *model = NULL;
237 
238 	if (CPU_ID_ARM11_P(ci->ci_arm_cpuid)
239 	    || CPU_ID_MV88SV58XX_P(ci->ci_arm_cpuid)
240 	    || CPU_ID_CORTEX_P(ci->ci_arm_cpuid)) {
241 #if 0
242 		const uint32_t nsacr = armreg_nsacr_read();
243 		const uint32_t nsacr_vfp = __BITS(VFP_COPROC,VFP_COPROC2);
244 		if ((nsacr & nsacr_vfp) != nsacr_vfp) {
245 			aprint_normal_dev(ci->ci_dev,
246 			    "VFP access denied (NSACR=%#x)\n", nsacr);
247 			install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
248 			ci->ci_vfp_id = 0;
249 			evcnt_attach_dynamic(&ci->ci_vfp_evs[0],
250 			    EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname,
251 			    "vfp fpscr traps");
252 			return;
253 		}
254 #endif
255 		const uint32_t cpacr_vfp = CPACR_CPn(VFP_COPROC);
256 		const uint32_t cpacr_vfp2 = CPACR_CPn(VFP_COPROC2);
257 
258 		/*
259 		 * We first need to enable access to the coprocessors.
260 		 */
261 		uint32_t cpacr = armreg_cpacr_read();
262 		cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp);
263 		cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2);
264 		armreg_cpacr_write(cpacr);
265 
266 		/*
267 		 * If we could enable them, then they exist.
268 		 */
269 		cpacr = armreg_cpacr_read();
270 		bool vfp_p = __SHIFTOUT(cpacr, cpacr_vfp2) == CPACR_ALL
271 		    && __SHIFTOUT(cpacr, cpacr_vfp) == CPACR_ALL;
272 		if (!vfp_p) {
273 			aprint_normal_dev(ci->ci_dev,
274 			    "VFP access denied (CPACR=%#x)\n", cpacr);
275 			install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
276 			ci->ci_vfp_id = 0;
277 			evcnt_attach_dynamic(&ci->ci_vfp_evs[0],
278 			    EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname,
279 			    "vfp fpscr traps");
280 			return;
281 		}
282 	}
283 
284 	void *uh = install_coproc_handler(VFP_COPROC, vfp_test);
285 
286 	undefined_test = 0;
287 
288 	const uint32_t fpsid = armreg_fpsid_read();
289 
290 	remove_coproc_handler(uh);
291 
292 	if (undefined_test != 0) {
293 		aprint_normal_dev(ci->ci_dev, "No VFP detected\n");
294 		install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
295 		ci->ci_vfp_id = 0;
296 		return;
297 	}
298 
299 	ci->ci_vfp_id = fpsid;
300 	switch (fpsid & ~ VFP_FPSID_REV_MSK) {
301 	case FPU_VFP10_ARM10E:
302 		model = "VFP10 R1";
303 		break;
304 	case FPU_VFP11_ARM11:
305 		model = "VFP11";
306 		break;
307 	case FPU_VFP_MV88SV58XX:
308 		model = "VFP3";
309 		break;
310 	case FPU_VFP_CORTEXA5:
311 	case FPU_VFP_CORTEXA7:
312 	case FPU_VFP_CORTEXA8:
313 	case FPU_VFP_CORTEXA9:
314 	case FPU_VFP_CORTEXA15:
315 		if (armreg_cpacr_read() & CPACR_V7_ASEDIS) {
316 			model = "VFP 4.0+";
317 		} else {
318 			model = "NEON MPE (VFP 3.0+)";
319 			cpu_neon_present = 1;
320 		}
321 		break;
322 	default:
323 		aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %#x\n",
324 		    fpsid);
325 		install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
326 		vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM
327 		    |VFP_FPSCR_RMODE;
328 		vfp_fpscr_default = 0;
329 		return;
330 	}
331 
332 	cpu_fpu_present = 1;
333 	cpu_media_and_vfp_features[0] = armreg_mvfr0_read();
334 	cpu_media_and_vfp_features[1] = armreg_mvfr1_read();
335 	if (fpsid != 0) {
336 		uint32_t f0 = armreg_mvfr0_read();
337 		uint32_t f1 = armreg_mvfr1_read();
338 		aprint_normal("vfp%d at %s: %s%s%s%s%s\n",
339 		    device_unit(ci->ci_dev),
340 		    device_xname(ci->ci_dev),
341 		    model,
342 		    ((f0 & ARM_MVFR0_ROUNDING_MASK) ? ", rounding" : ""),
343 		    ((f0 & ARM_MVFR0_EXCEPT_MASK) ? ", exceptions" : ""),
344 		    ((f1 & ARM_MVFR1_D_NAN_MASK) ? ", NaN propagation" : ""),
345 		    ((f1 & ARM_MVFR1_FTZ_MASK) ? ", denormals" : ""));
346 		aprint_verbose("vfp%d: mvfr: [0]=%#x [1]=%#x\n",
347 		    device_unit(ci->ci_dev), f0, f1);
348 		if (CPU_IS_PRIMARY(ci)) {
349 			if (f0 & ARM_MVFR0_ROUNDING_MASK) {
350 				vfp_fpscr_changable |= VFP_FPSCR_RMODE;
351 			}
352 			if (f1 & ARM_MVFR0_EXCEPT_MASK) {
353 				vfp_fpscr_changable |= VFP_FPSCR_ESUM;
354 			}
355 			// If hardware supports propagation of NaNs, select it.
356 			if (f1 & ARM_MVFR1_D_NAN_MASK) {
357 				vfp_fpscr_default &= ~VFP_FPSCR_DN;
358 				vfp_fpscr_changable |= VFP_FPSCR_DN;
359 			}
360 			// If hardware supports denormalized numbers, use it.
361 			if (cpu_media_and_vfp_features[1] & ARM_MVFR1_FTZ_MASK) {
362 				vfp_fpscr_default &= ~VFP_FPSCR_FZ;
363 				vfp_fpscr_changable |= VFP_FPSCR_FZ;
364 			}
365 		}
366 	}
367 	evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_MISC, NULL,
368 	    ci->ci_cpuname, "vfp coproc use");
369 	evcnt_attach_dynamic(&ci->ci_vfp_evs[1], EVCNT_TYPE_MISC, NULL,
370 	    ci->ci_cpuname, "vfp coproc re-use");
371 	evcnt_attach_dynamic(&ci->ci_vfp_evs[2], EVCNT_TYPE_TRAP, NULL,
372 	    ci->ci_cpuname, "vfp coproc fault");
373 	install_coproc_handler(VFP_COPROC, vfp_handler);
374 	install_coproc_handler(VFP_COPROC2, vfp_handler);
375 #ifdef CPU_CORTEX
376 	install_coproc_handler(CORE_UNKNOWN_HANDLER, neon_handler);
377 #endif
378 }
379 
380 /* The real handler for VFP bounces.  */
381 static int
382 vfp_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code)
383 {
384 	struct cpu_info * const ci = curcpu();
385 
386 	/* This shouldn't ever happen.  */
387 	if (fault_code != FAULT_USER)
388 		panic("VFP fault at %#x in non-user mode", frame->tf_pc);
389 
390 	if (ci->ci_vfp_id == 0) {
391 		/* No VFP detected, just fault.  */
392 		return 1;
393 	}
394 
395 	/*
396 	 * If we are just changing/fetching FPSCR, don't bother loading it.
397 	 */
398 	if (!vfp_fpscr_handler(address, insn, frame, fault_code))
399 		return 0;
400 
401 	/*
402 	 * Make sure we own the FP.
403 	 */
404 	pcu_load(&arm_vfp_ops);
405 
406 	uint32_t fpexc = armreg_fpexc_read();
407 	if (fpexc & VFP_FPEXC_EX) {
408 		ksiginfo_t ksi;
409 		KASSERT(fpexc & VFP_FPEXC_EN);
410 
411 		curcpu()->ci_vfp_evs[2].ev_count++;
412 
413 		/*
414 		 * Need the clear the exception condition so any signal
415 		 * and future use can proceed.
416 		 */
417 		armreg_fpexc_write(fpexc & ~(VFP_FPEXC_EX|VFP_FPEXC_FSUM));
418 
419 		pcu_save(&arm_vfp_ops);
420 
421 		/*
422 		 * XXX Need to emulate bounce instructions here to get correct
423 		 * XXX exception codes, etc.
424 		 */
425 		KSI_INIT_TRAP(&ksi);
426 		ksi.ksi_signo = SIGFPE;
427 		if (fpexc & VFP_FPEXC_IXF)
428 			ksi.ksi_code = FPE_FLTRES;
429 		else if (fpexc & VFP_FPEXC_UFF)
430 			ksi.ksi_code = FPE_FLTUND;
431 		else if (fpexc & VFP_FPEXC_OFF)
432 			ksi.ksi_code = FPE_FLTOVF;
433 		else if (fpexc & VFP_FPEXC_DZF)
434 			ksi.ksi_code = FPE_FLTDIV;
435 		else if (fpexc & VFP_FPEXC_IOF)
436 			ksi.ksi_code = FPE_FLTINV;
437 		ksi.ksi_addr = (uint32_t *)address;
438 		ksi.ksi_trap = 0;
439 		trapsignal(curlwp, &ksi);
440 		return 0;
441 	}
442 
443 	/* Need to restart the faulted instruction.  */
444 //	frame->tf_pc -= INSN_SIZE;
445 	return 0;
446 }
447 
448 #ifdef CPU_CORTEX
449 /* The real handler for NEON bounces.  */
450 static int
451 neon_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code)
452 {
453 	struct cpu_info * const ci = curcpu();
454 
455 	if (ci->ci_vfp_id == 0)
456 		/* No VFP detected, just fault.  */
457 		return 1;
458 
459 	if ((insn & 0xfe000000) != 0xf2000000
460 	    && (insn & 0xfe000000) != 0xf4000000)
461 		/* Not NEON instruction, just fault.  */
462 		return 1;
463 
464 	/* This shouldn't ever happen.  */
465 	if (fault_code != FAULT_USER)
466 		panic("NEON fault in non-user mode");
467 
468 	pcu_load(&arm_vfp_ops);
469 
470 	/* Need to restart the faulted instruction.  */
471 //	frame->tf_pc -= INSN_SIZE;
472 	return 0;
473 }
474 #endif
475 
476 static void
477 vfp_state_load(lwp_t *l, u_int flags)
478 {
479 	struct pcb * const pcb = lwp_getpcb(l);
480 	struct vfpreg * const fregs = &pcb->pcb_vfp;
481 
482 	/*
483 	 * Instrument VFP usage -- if a process has not previously
484 	 * used the VFP, mark it as having used VFP for the first time,
485 	 * and count this event.
486 	 *
487 	 * If a process has used the VFP, count a "used VFP, and took
488 	 * a trap to use it again" event.
489 	 */
490 	if (__predict_false((flags & PCU_VALID) == 0)) {
491 		curcpu()->ci_vfp_evs[0].ev_count++;
492 		pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default;
493 	} else {
494 		curcpu()->ci_vfp_evs[1].ev_count++;
495 	}
496 
497 	/*
498 	 * If the VFP is already enabled we must be bouncing an instruction.
499 	 */
500 	if (flags & PCU_REENABLE) {
501 		uint32_t fpexc = armreg_fpexc_read();
502 		armreg_fpexc_write(fpexc | VFP_FPEXC_EN);
503 		return;
504 	}
505 
506 	/*
507 	 * Load and Enable the VFP (so that we can write the registers).
508 	 */
509 	bool enabled = fregs->vfp_fpexc & VFP_FPEXC_EN;
510 	fregs->vfp_fpexc |= VFP_FPEXC_EN;
511 	armreg_fpexc_write(fregs->vfp_fpexc);
512 	if (enabled) {
513 		/*
514 		 * If we think the VFP is enabled, it must have be
515 		 * disabled by vfp_state_release for another LWP so
516 		 * we can now just return.
517 		 */
518 		return;
519 	}
520 
521 	load_vfpregs(fregs);
522 	armreg_fpscr_write(fregs->vfp_fpscr);
523 
524 	if (fregs->vfp_fpexc & VFP_FPEXC_EX) {
525 		/* Need to restore the exception handling state.  */
526 		armreg_fpinst2_write(fregs->vfp_fpinst2);
527 		if (fregs->vfp_fpexc & VFP_FPEXC_FP2V)
528 			armreg_fpinst_write(fregs->vfp_fpinst);
529 	}
530 }
531 
532 void
533 vfp_state_save(lwp_t *l)
534 {
535 	struct pcb * const pcb = lwp_getpcb(l);
536 	struct vfpreg * const fregs = &pcb->pcb_vfp;
537 	uint32_t fpexc = armreg_fpexc_read();
538 
539 	/*
540 	 * Enable the VFP (so we can read the registers).
541 	 * Make sure the exception bit is cleared so that we can
542 	 * safely dump the registers.
543 	 */
544 	armreg_fpexc_write((fpexc | VFP_FPEXC_EN) & ~VFP_FPEXC_EX);
545 
546 	fregs->vfp_fpexc = fpexc;
547 	if (fpexc & VFP_FPEXC_EX) {
548 		/* Need to save the exception handling state */
549 		fregs->vfp_fpinst = armreg_fpinst_read();
550 		if (fpexc & VFP_FPEXC_FP2V)
551 			fregs->vfp_fpinst2 = armreg_fpinst2_read();
552 	}
553 	fregs->vfp_fpscr = armreg_fpscr_read();
554 	save_vfpregs(fregs);
555 
556 	/* Disable the VFP.  */
557 	armreg_fpexc_write(fpexc & ~VFP_FPEXC_EN);
558 }
559 
560 void
561 vfp_state_release(lwp_t *l)
562 {
563 	struct pcb * const pcb = lwp_getpcb(l);
564 
565 	/*
566 	 * Now mark the VFP as disabled (and our state
567 	 * has been already saved or is being discarded).
568 	 */
569 	pcb->pcb_vfp.vfp_fpexc &= ~VFP_FPEXC_EN;
570 
571 	/*
572 	 * Turn off the FPU so the next time a VFP instruction is issued
573 	 * an exception happens.  We don't know if this LWP's state was
574 	 * loaded but if we turned off the FPU for some other LWP, when
575 	 * pcu_load invokes vfp_state_load it will see that VFP_FPEXC_EN
576 	 * is still set so it just restore fpexc and return since its
577 	 * contents are still sitting in the VFP.
578 	 */
579 	armreg_fpexc_write(armreg_fpexc_read() & ~VFP_FPEXC_EN);
580 }
581 
582 void
583 vfp_savecontext(void)
584 {
585 	pcu_save(&arm_vfp_ops);
586 }
587 
588 void
589 vfp_discardcontext(bool used_p)
590 {
591 	pcu_discard(&arm_vfp_ops, used_p);
592 }
593 
594 bool
595 vfp_used_p(void)
596 {
597 	return pcu_valid_p(&arm_vfp_ops);
598 }
599 
600 void
601 vfp_getcontext(struct lwp *l, mcontext_t *mcp, int *flagsp)
602 {
603 	if (vfp_used_p()) {
604 		const struct pcb * const pcb = lwp_getpcb(l);
605 		pcu_save(&arm_vfp_ops);
606 		mcp->__fpu.__vfpregs.__vfp_fpscr = pcb->pcb_vfp.vfp_fpscr;
607 		memcpy(mcp->__fpu.__vfpregs.__vfp_fstmx, pcb->pcb_vfp.vfp_regs,
608 		    sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx));
609 		*flagsp |= _UC_FPU|_UC_ARM_VFP;
610 	}
611 }
612 
613 void
614 vfp_setcontext(struct lwp *l, const mcontext_t *mcp)
615 {
616 	pcu_discard(&arm_vfp_ops, true);
617 	struct pcb * const pcb = lwp_getpcb(l);
618 	pcb->pcb_vfp.vfp_fpscr = mcp->__fpu.__vfpregs.__vfp_fpscr;
619 	memcpy(pcb->pcb_vfp.vfp_regs, mcp->__fpu.__vfpregs.__vfp_fstmx,
620 	    sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx));
621 }
622 
623 #endif /* FPU_VFP */
624