1 /* $NetBSD: vfp_init.c,v 1.39 2014/05/16 00:48:41 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2008 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 25 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/cpu.h> 38 39 #include <arm/locore.h> 40 #include <arm/pcb.h> 41 #include <arm/undefined.h> 42 #include <arm/vfpreg.h> 43 #include <arm/mcontext.h> 44 45 #include <uvm/uvm_extern.h> /* for pmap.h */ 46 47 #ifdef FPU_VFP 48 49 #ifdef CPU_CORTEX 50 __asm(".fpu\tvfpv4"); 51 #else 52 __asm(".fpu\tvfp"); 53 #endif 54 55 /* FLDMD <X>, {d0-d15} */ 56 static inline void 57 load_vfpregs_lo(const uint64_t *p) 58 { 59 __asm __volatile("vldmia %0, {d0-d15}" :: "r" (p) : "memory"); 60 } 61 62 /* FSTMD <X>, {d0-d15} */ 63 static inline void 64 save_vfpregs_lo(uint64_t *p) 65 { 66 __asm __volatile("vstmia %0, {d0-d15}" :: "r" (p) : "memory"); 67 } 68 69 #ifdef CPU_CORTEX 70 /* FLDMD <X>, {d16-d31} */ 71 static inline void 72 load_vfpregs_hi(const uint64_t *p) 73 { 74 __asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory"); 75 } 76 77 /* FLDMD <X>, {d16-d31} */ 78 static inline void 79 save_vfpregs_hi(uint64_t *p) 80 { 81 __asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory"); 82 } 83 #endif 84 85 static inline void 86 load_vfpregs(const struct vfpreg *fregs) 87 { 88 load_vfpregs_lo(fregs->vfp_regs); 89 #ifdef CPU_CORTEX 90 #ifdef CPU_ARM11 91 switch (curcpu()->ci_vfp_id) { 92 case FPU_VFP_CORTEXA5: 93 case FPU_VFP_CORTEXA7: 94 case FPU_VFP_CORTEXA8: 95 case FPU_VFP_CORTEXA9: 96 case FPU_VFP_CORTEXA15: 97 #endif 98 load_vfpregs_hi(fregs->vfp_regs); 99 #ifdef CPU_ARM11 100 break; 101 } 102 #endif 103 #endif 104 } 105 106 static inline void 107 save_vfpregs(struct vfpreg *fregs) 108 { 109 save_vfpregs_lo(fregs->vfp_regs); 110 #ifdef CPU_CORTEX 111 #ifdef CPU_ARM11 112 switch (curcpu()->ci_vfp_id) { 113 case FPU_VFP_CORTEXA5: 114 case FPU_VFP_CORTEXA7: 115 case FPU_VFP_CORTEXA8: 116 case FPU_VFP_CORTEXA9: 117 case FPU_VFP_CORTEXA15: 118 #endif 119 save_vfpregs_hi(fregs->vfp_regs); 120 #ifdef CPU_ARM11 121 break; 122 } 123 #endif 124 #endif 125 } 126 127 /* The real handler for VFP bounces. */ 128 static int vfp_handler(u_int, u_int, trapframe_t *, int); 129 #ifdef CPU_CORTEX 130 static int neon_handler(u_int, u_int, trapframe_t *, int); 131 #endif 132 133 static void vfp_state_load(lwp_t *, u_int); 134 static void vfp_state_save(lwp_t *); 135 static void vfp_state_release(lwp_t *); 136 137 const pcu_ops_t arm_vfp_ops = { 138 .pcu_id = PCU_FPU, 139 .pcu_state_save = vfp_state_save, 140 .pcu_state_load = vfp_state_load, 141 .pcu_state_release = vfp_state_release, 142 }; 143 144 /* determine what bits can be changed */ 145 uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM; 146 /* default to run fast */ 147 uint32_t vfp_fpscr_default = (VFP_FPSCR_DN | VFP_FPSCR_FZ | VFP_FPSCR_RN); 148 149 /* 150 * Used to test for a VFP. The following function is installed as a coproc10 151 * handler on the undefined instruction vector and then we issue a VFP 152 * instruction. If undefined_test is non zero then the VFP did not handle 153 * the instruction so must be absent, or disabled. 154 */ 155 156 static int undefined_test; 157 158 static int 159 vfp_test(u_int address, u_int insn, trapframe_t *frame, int fault_code) 160 { 161 162 frame->tf_pc += INSN_SIZE; 163 ++undefined_test; 164 return 0; 165 } 166 167 #else 168 /* determine what bits can be changed */ 169 uint32_t vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM|VFP_FPSCR_RMODE; 170 #endif /* FPU_VFP */ 171 172 static int 173 vfp_fpscr_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 174 { 175 struct lwp * const l = curlwp; 176 const u_int regno = (insn >> 12) & 0xf; 177 /* 178 * Only match move to/from the FPSCR register and we 179 * can't be using the SP,LR,PC as a source. 180 */ 181 if ((insn & 0xffef0fff) != 0xeee10a10 || regno > 12) 182 return 1; 183 184 struct pcb * const pcb = lwp_getpcb(l); 185 186 #ifdef FPU_VFP 187 /* 188 * If FPU is valid somewhere, let's just reenable VFP and 189 * retry the instruction (only safe thing to do since the 190 * pcb has a stale copy). 191 */ 192 if (pcb->pcb_vfp.vfp_fpexc & VFP_FPEXC_EN) 193 return 1; 194 195 if (__predict_false(!vfp_used_p())) { 196 pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default; 197 } 198 #endif 199 200 /* 201 * We now know the pcb has the saved copy. 202 */ 203 register_t * const regp = &frame->tf_r0 + regno; 204 if (insn & 0x00100000) { 205 *regp = pcb->pcb_vfp.vfp_fpscr; 206 } else { 207 pcb->pcb_vfp.vfp_fpscr &= ~vfp_fpscr_changable; 208 pcb->pcb_vfp.vfp_fpscr |= *regp & vfp_fpscr_changable; 209 } 210 211 curcpu()->ci_vfp_evs[0].ev_count++; 212 213 frame->tf_pc += INSN_SIZE; 214 return 0; 215 } 216 217 #ifndef FPU_VFP 218 /* 219 * If we don't want VFP support, we still need to handle emulating VFP FPSCR 220 * instructions. 221 */ 222 void 223 vfp_attach(struct cpu_info *ci) 224 { 225 if (CPU_IS_PRIMARY(ci)) { 226 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 227 } 228 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_TRAP, NULL, 229 ci->ci_cpuname, "vfp fpscr traps"); 230 } 231 232 #else 233 void 234 vfp_attach(struct cpu_info *ci) 235 { 236 const char *model = NULL; 237 238 if (CPU_ID_ARM11_P(ci->ci_arm_cpuid) 239 || CPU_ID_MV88SV58XX_P(ci->ci_arm_cpuid) 240 || CPU_ID_CORTEX_P(ci->ci_arm_cpuid)) { 241 #if 0 242 const uint32_t nsacr = armreg_nsacr_read(); 243 const uint32_t nsacr_vfp = __BITS(VFP_COPROC,VFP_COPROC2); 244 if ((nsacr & nsacr_vfp) != nsacr_vfp) { 245 aprint_normal_dev(ci->ci_dev, "VFP access denied\n"); 246 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 247 ci->ci_vfp_id = 0; 248 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], 249 EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname, 250 "vfp fpscr traps"); 251 return; 252 } 253 #endif 254 const uint32_t cpacr_vfp = CPACR_CPn(VFP_COPROC); 255 const uint32_t cpacr_vfp2 = CPACR_CPn(VFP_COPROC2); 256 257 /* 258 * We first need to enable access to the coprocessors. 259 */ 260 uint32_t cpacr = armreg_cpacr_read(); 261 cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp); 262 cpacr |= __SHIFTIN(CPACR_ALL, cpacr_vfp2); 263 armreg_cpacr_write(cpacr); 264 265 /* 266 * If we could enable them, then they exist. 267 */ 268 cpacr = armreg_cpacr_read(); 269 bool vfp_p = __SHIFTOUT(cpacr, cpacr_vfp2) != CPACR_NOACCESS 270 || __SHIFTOUT(cpacr, cpacr_vfp) != CPACR_NOACCESS; 271 if (!vfp_p) { 272 aprint_normal_dev(ci->ci_dev, "No VFP detected\n"); 273 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 274 ci->ci_vfp_id = 0; 275 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], 276 EVCNT_TYPE_TRAP, NULL, ci->ci_cpuname, 277 "vfp fpscr traps"); 278 return; 279 } 280 } 281 282 void *uh = install_coproc_handler(VFP_COPROC, vfp_test); 283 284 undefined_test = 0; 285 286 const uint32_t fpsid = armreg_fpsid_read(); 287 288 remove_coproc_handler(uh); 289 290 if (undefined_test != 0) { 291 aprint_normal_dev(ci->ci_dev, "No VFP detected\n"); 292 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 293 ci->ci_vfp_id = 0; 294 return; 295 } 296 297 ci->ci_vfp_id = fpsid; 298 switch (fpsid & ~ VFP_FPSID_REV_MSK) { 299 case FPU_VFP10_ARM10E: 300 model = "VFP10 R1"; 301 break; 302 case FPU_VFP11_ARM11: 303 model = "VFP11"; 304 break; 305 case FPU_VFP_MV88SV58XX: 306 model = "VFP3"; 307 break; 308 case FPU_VFP_CORTEXA5: 309 case FPU_VFP_CORTEXA7: 310 case FPU_VFP_CORTEXA8: 311 case FPU_VFP_CORTEXA9: 312 case FPU_VFP_CORTEXA15: 313 if (armreg_cpacr_read() & CPACR_V7_ASEDIS) { 314 model = "VFP 4.0+"; 315 } else { 316 model = "NEON MPE (VFP 3.0+)"; 317 cpu_neon_present = 1; 318 } 319 break; 320 default: 321 aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %#x\n", 322 fpsid); 323 install_coproc_handler(VFP_COPROC, vfp_fpscr_handler); 324 vfp_fpscr_changable = VFP_FPSCR_CSUM|VFP_FPSCR_ESUM 325 |VFP_FPSCR_RMODE; 326 vfp_fpscr_default = 0; 327 return; 328 } 329 330 cpu_fpu_present = 1; 331 cpu_media_and_vfp_features[0] = armreg_mvfr0_read(); 332 cpu_media_and_vfp_features[1] = armreg_mvfr1_read(); 333 if (fpsid != 0) { 334 uint32_t f0 = armreg_mvfr0_read(); 335 uint32_t f1 = armreg_mvfr0_read(); 336 aprint_normal("vfp%d at %s: %s%s%s%s%s\n", 337 device_unit(ci->ci_dev), 338 device_xname(ci->ci_dev), 339 model, 340 ((f0 & ARM_MVFR0_ROUNDING_MASK) ? ", rounding" : ""), 341 ((f0 & ARM_MVFR0_EXCEPT_MASK) ? ", exceptions" : ""), 342 ((f1 & ARM_MVFR1_D_NAN_MASK) ? ", NaN propagation" : ""), 343 ((f1 & ARM_MVFR1_FTZ_MASK) ? ", denormals" : "")); 344 aprint_verbose("vfp%d: mvfr: [0]=%#x [1]=%#x\n", 345 device_unit(ci->ci_dev), f0, f1); 346 if (CPU_IS_PRIMARY(ci)) { 347 if (f0 & ARM_MVFR0_ROUNDING_MASK) { 348 vfp_fpscr_changable |= VFP_FPSCR_RMODE; 349 } 350 if (f1 & ARM_MVFR0_EXCEPT_MASK) { 351 vfp_fpscr_changable |= VFP_FPSCR_ESUM; 352 } 353 // If hardware supports propagation of NaNs, select it. 354 if (f1 & ARM_MVFR1_D_NAN_MASK) { 355 vfp_fpscr_default &= ~VFP_FPSCR_DN; 356 vfp_fpscr_changable |= VFP_FPSCR_DN; 357 } 358 // If hardware supports denormalized numbers, use it. 359 if (cpu_media_and_vfp_features[1] & ARM_MVFR1_FTZ_MASK) { 360 vfp_fpscr_default &= ~VFP_FPSCR_FZ; 361 vfp_fpscr_changable |= VFP_FPSCR_FZ; 362 } 363 } 364 } 365 evcnt_attach_dynamic(&ci->ci_vfp_evs[0], EVCNT_TYPE_MISC, NULL, 366 ci->ci_cpuname, "vfp coproc use"); 367 evcnt_attach_dynamic(&ci->ci_vfp_evs[1], EVCNT_TYPE_MISC, NULL, 368 ci->ci_cpuname, "vfp coproc re-use"); 369 evcnt_attach_dynamic(&ci->ci_vfp_evs[2], EVCNT_TYPE_TRAP, NULL, 370 ci->ci_cpuname, "vfp coproc fault"); 371 install_coproc_handler(VFP_COPROC, vfp_handler); 372 install_coproc_handler(VFP_COPROC2, vfp_handler); 373 #ifdef CPU_CORTEX 374 install_coproc_handler(CORE_UNKNOWN_HANDLER, neon_handler); 375 #endif 376 } 377 378 /* The real handler for VFP bounces. */ 379 static int 380 vfp_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 381 { 382 struct cpu_info * const ci = curcpu(); 383 384 /* This shouldn't ever happen. */ 385 if (fault_code != FAULT_USER) 386 panic("VFP fault at %#x in non-user mode", frame->tf_pc); 387 388 if (ci->ci_vfp_id == 0) { 389 /* No VFP detected, just fault. */ 390 return 1; 391 } 392 393 /* 394 * If we are just changing/fetching FPSCR, don't bother loading it. 395 */ 396 if (!vfp_fpscr_handler(address, insn, frame, fault_code)) 397 return 0; 398 399 /* 400 * Make sure we own the FP. 401 */ 402 pcu_load(&arm_vfp_ops); 403 404 uint32_t fpexc = armreg_fpexc_read(); 405 if (fpexc & VFP_FPEXC_EX) { 406 ksiginfo_t ksi; 407 KASSERT(fpexc & VFP_FPEXC_EN); 408 409 curcpu()->ci_vfp_evs[2].ev_count++; 410 411 /* 412 * Need the clear the exception condition so any signal 413 * and future use can proceed. 414 */ 415 armreg_fpexc_write(fpexc & ~(VFP_FPEXC_EX|VFP_FPEXC_FSUM)); 416 417 pcu_save(&arm_vfp_ops); 418 419 /* 420 * XXX Need to emulate bounce instructions here to get correct 421 * XXX exception codes, etc. 422 */ 423 KSI_INIT_TRAP(&ksi); 424 ksi.ksi_signo = SIGFPE; 425 if (fpexc & VFP_FPEXC_IXF) 426 ksi.ksi_code = FPE_FLTRES; 427 else if (fpexc & VFP_FPEXC_UFF) 428 ksi.ksi_code = FPE_FLTUND; 429 else if (fpexc & VFP_FPEXC_OFF) 430 ksi.ksi_code = FPE_FLTOVF; 431 else if (fpexc & VFP_FPEXC_DZF) 432 ksi.ksi_code = FPE_FLTDIV; 433 else if (fpexc & VFP_FPEXC_IOF) 434 ksi.ksi_code = FPE_FLTINV; 435 ksi.ksi_addr = (uint32_t *)address; 436 ksi.ksi_trap = 0; 437 trapsignal(curlwp, &ksi); 438 return 0; 439 } 440 441 /* Need to restart the faulted instruction. */ 442 // frame->tf_pc -= INSN_SIZE; 443 return 0; 444 } 445 446 #ifdef CPU_CORTEX 447 /* The real handler for NEON bounces. */ 448 static int 449 neon_handler(u_int address, u_int insn, trapframe_t *frame, int fault_code) 450 { 451 struct cpu_info * const ci = curcpu(); 452 453 if (ci->ci_vfp_id == 0) 454 /* No VFP detected, just fault. */ 455 return 1; 456 457 if ((insn & 0xfe000000) != 0xf2000000 458 && (insn & 0xfe000000) != 0xf4000000) 459 /* Not NEON instruction, just fault. */ 460 return 1; 461 462 /* This shouldn't ever happen. */ 463 if (fault_code != FAULT_USER) 464 panic("NEON fault in non-user mode"); 465 466 pcu_load(&arm_vfp_ops); 467 468 /* Need to restart the faulted instruction. */ 469 // frame->tf_pc -= INSN_SIZE; 470 return 0; 471 } 472 #endif 473 474 static void 475 vfp_state_load(lwp_t *l, u_int flags) 476 { 477 struct pcb * const pcb = lwp_getpcb(l); 478 struct vfpreg * const fregs = &pcb->pcb_vfp; 479 480 /* 481 * Instrument VFP usage -- if a process has not previously 482 * used the VFP, mark it as having used VFP for the first time, 483 * and count this event. 484 * 485 * If a process has used the VFP, count a "used VFP, and took 486 * a trap to use it again" event. 487 */ 488 if (__predict_false((flags & PCU_VALID) == 0)) { 489 curcpu()->ci_vfp_evs[0].ev_count++; 490 pcb->pcb_vfp.vfp_fpscr = vfp_fpscr_default; 491 } else { 492 curcpu()->ci_vfp_evs[1].ev_count++; 493 } 494 495 /* 496 * If the VFP is already enabled we must be bouncing an instruction. 497 */ 498 if (flags & PCU_REENABLE) { 499 uint32_t fpexc = armreg_fpexc_read(); 500 armreg_fpexc_write(fpexc | VFP_FPEXC_EN); 501 return; 502 } 503 504 /* 505 * Load and Enable the VFP (so that we can write the registers). 506 */ 507 bool enabled = fregs->vfp_fpexc & VFP_FPEXC_EN; 508 fregs->vfp_fpexc |= VFP_FPEXC_EN; 509 armreg_fpexc_write(fregs->vfp_fpexc); 510 if (enabled) { 511 /* 512 * If we think the VFP is enabled, it must have be 513 * disabled by vfp_state_release for another LWP so 514 * we can now just return. 515 */ 516 return; 517 } 518 519 load_vfpregs(fregs); 520 armreg_fpscr_write(fregs->vfp_fpscr); 521 522 if (fregs->vfp_fpexc & VFP_FPEXC_EX) { 523 /* Need to restore the exception handling state. */ 524 armreg_fpinst2_write(fregs->vfp_fpinst2); 525 if (fregs->vfp_fpexc & VFP_FPEXC_FP2V) 526 armreg_fpinst_write(fregs->vfp_fpinst); 527 } 528 } 529 530 void 531 vfp_state_save(lwp_t *l) 532 { 533 struct pcb * const pcb = lwp_getpcb(l); 534 struct vfpreg * const fregs = &pcb->pcb_vfp; 535 uint32_t fpexc = armreg_fpexc_read(); 536 537 /* 538 * Enable the VFP (so we can read the registers). 539 * Make sure the exception bit is cleared so that we can 540 * safely dump the registers. 541 */ 542 armreg_fpexc_write((fpexc | VFP_FPEXC_EN) & ~VFP_FPEXC_EX); 543 544 fregs->vfp_fpexc = fpexc; 545 if (fpexc & VFP_FPEXC_EX) { 546 /* Need to save the exception handling state */ 547 fregs->vfp_fpinst = armreg_fpinst_read(); 548 if (fpexc & VFP_FPEXC_FP2V) 549 fregs->vfp_fpinst2 = armreg_fpinst2_read(); 550 } 551 fregs->vfp_fpscr = armreg_fpscr_read(); 552 save_vfpregs(fregs); 553 554 /* Disable the VFP. */ 555 armreg_fpexc_write(fpexc & ~VFP_FPEXC_EN); 556 } 557 558 void 559 vfp_state_release(lwp_t *l) 560 { 561 struct pcb * const pcb = lwp_getpcb(l); 562 563 /* 564 * Now mark the VFP as disabled (and our state 565 * has been already saved or is being discarded). 566 */ 567 pcb->pcb_vfp.vfp_fpexc &= ~VFP_FPEXC_EN; 568 569 /* 570 * Turn off the FPU so the next time a VFP instruction is issued 571 * an exception happens. We don't know if this LWP's state was 572 * loaded but if we turned off the FPU for some other LWP, when 573 * pcu_load invokes vfp_state_load it will see that VFP_FPEXC_EN 574 * is still set so it just restore fpexc and return since its 575 * contents are still sitting in the VFP. 576 */ 577 armreg_fpexc_write(armreg_fpexc_read() & ~VFP_FPEXC_EN); 578 } 579 580 void 581 vfp_savecontext(void) 582 { 583 pcu_save(&arm_vfp_ops); 584 } 585 586 void 587 vfp_discardcontext(bool used_p) 588 { 589 pcu_discard(&arm_vfp_ops, used_p); 590 } 591 592 bool 593 vfp_used_p(void) 594 { 595 return pcu_valid_p(&arm_vfp_ops); 596 } 597 598 void 599 vfp_getcontext(struct lwp *l, mcontext_t *mcp, int *flagsp) 600 { 601 if (vfp_used_p()) { 602 const struct pcb * const pcb = lwp_getpcb(l); 603 pcu_save(&arm_vfp_ops); 604 mcp->__fpu.__vfpregs.__vfp_fpscr = pcb->pcb_vfp.vfp_fpscr; 605 memcpy(mcp->__fpu.__vfpregs.__vfp_fstmx, pcb->pcb_vfp.vfp_regs, 606 sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx)); 607 *flagsp |= _UC_FPU|_UC_ARM_VFP; 608 } 609 } 610 611 void 612 vfp_setcontext(struct lwp *l, const mcontext_t *mcp) 613 { 614 pcu_discard(&arm_vfp_ops, true); 615 struct pcb * const pcb = lwp_getpcb(l); 616 pcb->pcb_vfp.vfp_fpscr = mcp->__fpu.__vfpregs.__vfp_fpscr; 617 memcpy(pcb->pcb_vfp.vfp_regs, mcp->__fpu.__vfpregs.__vfp_fstmx, 618 sizeof(mcp->__fpu.__vfpregs.__vfp_fstmx)); 619 } 620 621 #endif /* FPU_VFP */ 622