1*08e7d9faSjmcneill /* $NetBSD: vexpress_platform.h,v 1.1 2017/06/02 20:16:05 jmcneill Exp $ */ 2*08e7d9faSjmcneill 3*08e7d9faSjmcneill /*- 4*08e7d9faSjmcneill * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5*08e7d9faSjmcneill * All rights reserved. 6*08e7d9faSjmcneill * 7*08e7d9faSjmcneill * Redistribution and use in source and binary forms, with or without 8*08e7d9faSjmcneill * modification, are permitted provided that the following conditions 9*08e7d9faSjmcneill * are met: 10*08e7d9faSjmcneill * 1. Redistributions of source code must retain the above copyright 11*08e7d9faSjmcneill * notice, this list of conditions and the following disclaimer. 12*08e7d9faSjmcneill * 2. Redistributions in binary form must reproduce the above copyright 13*08e7d9faSjmcneill * notice, this list of conditions and the following disclaimer in the 14*08e7d9faSjmcneill * documentation and/or other materials provided with the distribution. 15*08e7d9faSjmcneill * 16*08e7d9faSjmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17*08e7d9faSjmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18*08e7d9faSjmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19*08e7d9faSjmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20*08e7d9faSjmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21*08e7d9faSjmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22*08e7d9faSjmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23*08e7d9faSjmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24*08e7d9faSjmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*08e7d9faSjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*08e7d9faSjmcneill * SUCH DAMAGE. 27*08e7d9faSjmcneill */ 28*08e7d9faSjmcneill 29*08e7d9faSjmcneill #ifndef _ARM_VEXPRESS_PLATFORM_H 30*08e7d9faSjmcneill #define _ARM_VEXPRESS_PLATFORM_H 31*08e7d9faSjmcneill 32*08e7d9faSjmcneill #define VEXPRESS_CORE_VBASE 0xf0000000 33*08e7d9faSjmcneill #define VEXPRESS_CORE_PBASE 0x10000000 34*08e7d9faSjmcneill #define VEXPRESS_CORE_SIZE 0x0ff00000 35*08e7d9faSjmcneill 36*08e7d9faSjmcneill #define VEXPRESS_GIC_VBASE (VEXPRESS_CORE_VBASE + VEXPRESS_CORE_SIZE) 37*08e7d9faSjmcneill #define VEXPRESS_GIC_PBASE 0x2c000000 38*08e7d9faSjmcneill #define VEXPRESS_GIC_SIZE 0x00100000 39*08e7d9faSjmcneill 40*08e7d9faSjmcneill #endif /* _ARM_VEXPRESS_PLATFORM_H */ 41