1 /* $NetBSD: vexpress_platform.c,v 1.8 2018/06/11 19:49:18 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_multiprocessor.h" 30 #include "opt_fdt_arm.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.8 2018/06/11 19:49:18 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 #include <sys/termios.h> 40 41 #include <dev/fdt/fdtvar.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <machine/bootconfig.h> 46 #include <arm/cpufunc.h> 47 48 #include <arm/fdt/arm_fdtvar.h> 49 50 #include <arm/cortex/gtmr_var.h> 51 52 #include <arm/cortex/gic_reg.h> 53 54 #include <evbarm/dev/plcomreg.h> 55 56 #include <arm/vexpress/vexpress_platform.h> 57 58 #include <libfdt.h> 59 60 #define VEXPRESS_CLCD_NODE_PATH \ 61 "/smb@8000000/motherboard/iofpga@3,00000000/clcd@1f0000" 62 #define VEXPRESS_REF_FREQ 24000000 63 64 extern struct bus_space armv7_generic_bs_tag; 65 extern struct bus_space armv7_generic_a4x_bs_tag; 66 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 67 68 #define SYSREG_BASE 0x1c010000 69 #define SYSREG_SIZE 0x1000 70 71 #define SYS_FLAGS 0x0030 72 #define SYS_FLAGSCLR 0x0034 73 #define SYS_CFGDATA 0x00a0 74 #define SYS_CFGCTRL 0x00a4 75 #define SYS_CFGCTRL_START __BIT(31) 76 #define SYS_CFGCTRL_WRITE __BIT(30) 77 #define SYS_CFGCTRL_DCC __BITS(29,26) 78 #define SYS_CFGCTRL_FUNCTION __BITS(25,20) 79 #define SYS_CFGCTRL_FUNCTION_SHUTDOWN 8 80 #define SYS_CFGCTRL_FUNCTION_REBOOT 9 81 #define SYS_CFGCTRL_SITE __BITS(17,16) 82 #define SYS_CFGCTRL_POSITION __BITS(15,12) 83 #define SYS_CFGCTRL_DEVICE __BITS(11,0) 84 #define SYS_CFGSTAT 0x00a8 85 #define SYS_CFGSTAT_ERROR __BIT(1) 86 #define SYS_CFGSTAT_COMPLETE __BIT(0) 87 88 static bus_space_tag_t sysreg_bst = &armv7_generic_bs_tag; 89 static bus_space_handle_t sysreg_bsh; 90 91 #define SYSREG_WRITE(o, v) \ 92 bus_space_write_4(sysreg_bst, sysreg_bsh, (o), (v)) 93 94 95 static void 96 vexpress_a15_smp_init(void) 97 { 98 extern void cortex_mpstart(void); 99 bus_space_tag_t gicd_bst = &armv7_generic_bs_tag; 100 bus_space_handle_t gicd_bsh; 101 int started = 0; 102 103 /* Bitmask of CPUs (non-BSP) to start */ 104 for (int i = 1; i < arm_cpu_max; i++) 105 started |= __BIT(i); 106 107 /* Write init vec to SYS_FLAGS register */ 108 SYSREG_WRITE(SYS_FLAGSCLR, 0xffffffff); 109 SYSREG_WRITE(SYS_FLAGS, (uint32_t)cortex_mpstart); 110 111 /* Map GIC distributor */ 112 bus_space_map(gicd_bst, VEXPRESS_GIC_PBASE + GICD_BASE, 113 0x1000, 0, &gicd_bsh); 114 115 /* Enable GIC distributor */ 116 bus_space_write_4(gicd_bst, gicd_bsh, 117 GICD_CTRL, GICD_CTRL_Enable); 118 119 /* Send sw interrupt to APs */ 120 const uint32_t sgir = GICD_SGIR_TargetListFilter_NotMe; 121 bus_space_write_4(gicd_bst, gicd_bsh, GICD_SGIR, sgir); 122 123 /* Wait for APs to start */ 124 for (u_int i = 0x10000000; i > 0; i--) { 125 arm_dmb(); 126 if (arm_cpu_hatched == started) 127 break; 128 } 129 130 /* Disable GIC distributor */ 131 bus_space_write_4(gicd_bst, gicd_bsh, GICD_CTRL, 0); 132 } 133 134 135 static const struct pmap_devmap * 136 vexpress_platform_devmap(void) 137 { 138 static const struct pmap_devmap devmap[] = { 139 DEVMAP_ENTRY(VEXPRESS_CORE_VBASE, 140 VEXPRESS_CORE_PBASE, 141 VEXPRESS_CORE_SIZE), 142 DEVMAP_ENTRY(VEXPRESS_GIC_VBASE, 143 VEXPRESS_GIC_PBASE, 144 VEXPRESS_GIC_SIZE), 145 DEVMAP_ENTRY_END 146 }; 147 148 return devmap; 149 } 150 151 static void 152 vexpress_platform_bootstrap(void) 153 { 154 bus_space_map(sysreg_bst, SYSREG_BASE, SYSREG_SIZE, 0, 155 &sysreg_bsh); 156 157 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU); 158 159 vexpress_a15_smp_init(); 160 161 if (match_bootconf_option(boot_args, "console", "fb")) { 162 void *fdt_data = __UNCONST(fdtbus_get_data()); 163 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 164 if (chosen_off >= 0) 165 fdt_setprop_string(fdt_data, chosen_off, "stdout-path", 166 VEXPRESS_CLCD_NODE_PATH); 167 } 168 } 169 170 static void 171 vexpress_platform_init_attach_args(struct fdt_attach_args *faa) 172 { 173 faa->faa_bst = &armv7_generic_bs_tag; 174 faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag; 175 faa->faa_dmat = &arm_generic_dma_tag; 176 } 177 178 static void 179 vexpress_platform_early_putchar(char c) 180 { 181 #ifdef CONSADDR 182 #define CONSADDR_VA ((CONSADDR - VEXPRESS_CORE_PBASE) + VEXPRESS_CORE_VBASE) 183 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 184 (volatile uint32_t *)CONSADDR_VA : 185 (volatile uint32_t *)CONSADDR; 186 187 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 188 continue; 189 190 uartaddr[PL01XCOM_DR / 4] = htole32(c); 191 arm_dsb(); 192 193 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0) 194 continue; 195 #endif 196 } 197 198 static void 199 vexpress_platform_device_register(device_t self, void *aux) 200 { 201 } 202 203 static void 204 vexpress_platform_reset(void) 205 { 206 SYSREG_WRITE(SYS_CFGSTAT, 0); 207 SYSREG_WRITE(SYS_CFGDATA, 0); 208 SYSREG_WRITE(SYS_CFGCTRL, 209 SYS_CFGCTRL_START | 210 SYS_CFGCTRL_WRITE | 211 __SHIFTIN(SYS_CFGCTRL_FUNCTION_REBOOT, 212 SYS_CFGCTRL_FUNCTION)); 213 } 214 215 static u_int 216 vexpress_platform_uart_freq(void) 217 { 218 return VEXPRESS_REF_FREQ; 219 } 220 221 static const struct arm_platform vexpress_platform = { 222 .devmap = vexpress_platform_devmap, 223 .bootstrap = vexpress_platform_bootstrap, 224 .init_attach_args = vexpress_platform_init_attach_args, 225 .early_putchar = vexpress_platform_early_putchar, 226 .device_register = vexpress_platform_device_register, 227 .reset = vexpress_platform_reset, 228 .delay = gtmr_delay, 229 .uart_freq = vexpress_platform_uart_freq, 230 }; 231 232 ARM_PLATFORM(vexpress, "arm,vexpress", &vexpress_platform); 233