1 /* $NetBSD: ti_omapintc.c,v 1.1 2017/10/26 01:16:32 jakllsch Exp $ */ 2 /* 3 * Define the SDP2430 specific information and then include the generic OMAP 4 * interrupt header. 5 */ 6 7 /* 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain this list of conditions 12 * and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce this list of conditions 14 * and the following disclaimer in the documentation and/or other materials 15 * provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 19 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #define _INTR_PRIVATE 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: ti_omapintc.c,v 1.1 2017/10/26 01:16:32 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/evcnt.h> 36 #include <sys/device.h> 37 38 #include <uvm/uvm_extern.h> 39 40 #include <machine/intr.h> 41 #include <sys/bus.h> 42 43 #include <arm/cpu.h> 44 #include <arm/armreg.h> 45 #include <arm/cpufunc.h> 46 #include <arm/atomic.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #define INTC_CONTROL 0x048 51 #define INTC_CONTROL_NEWIRQAGR __BIT(0) 52 #define INTC_ITR 0x080 53 #define INTC_MIR 0x084 54 #define INTC_MIR_CLEAR 0x088 55 #define INTC_MIR_SET 0x08c 56 #define INTC_PENDING_IRQ 0x098 57 58 #define INTC_MAX_SOURCES 128 59 60 61 #define INTC_READ(sc, g, o) \ 62 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o)) 63 #define INTC_WRITE(sc, g, o, v) \ 64 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (g) * 0x20 + (o), v) 65 66 static int omap2icu_match(device_t, cfdata_t, void *); 67 static void omap2icu_attach(device_t, device_t, void *); 68 69 static void omap2icu_unblock_irqs(struct pic_softc *, size_t, uint32_t); 70 static void omap2icu_block_irqs(struct pic_softc *, size_t, uint32_t); 71 static void omap2icu_establish_irq(struct pic_softc *, struct intrsource *); 72 static void omap2icu_set_priority(struct pic_softc *, int); 73 #if 0 74 static void omap2icu_source_name(struct pic_softc *, int, char *, size_t); 75 #endif 76 77 static const struct pic_ops omap2icu_picops = { 78 .pic_unblock_irqs = omap2icu_unblock_irqs, 79 .pic_block_irqs = omap2icu_block_irqs, 80 .pic_establish_irq = omap2icu_establish_irq, 81 .pic_set_priority = omap2icu_set_priority, 82 #if 0 83 .pic_source_name = omap2icu_source_name, 84 #endif 85 }; 86 87 #define PICTOSOFTC(pic) \ 88 ((struct omap2icu_softc *)((uintptr_t)(pic) - offsetof(struct omap2icu_softc, sc_pic))) 89 90 struct omap2icu_softc { 91 device_t sc_dev; 92 bus_space_tag_t sc_memt; 93 bus_space_handle_t sc_memh; 94 struct pic_softc sc_pic; 95 uint32_t sc_enabled_irqs[howmany(INTC_MAX_SOURCES, 32)]; 96 }; 97 98 static struct omap2icu_softc *intc_softc; 99 100 static void 101 omap2icu_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 102 { 103 struct omap2icu_softc * const sc = PICTOSOFTC(pic); 104 const size_t group = irqbase / 32; 105 KASSERT((irq_mask & sc->sc_enabled_irqs[group]) == 0); 106 sc->sc_enabled_irqs[group] |= irq_mask; 107 INTC_WRITE(sc, group, INTC_MIR_CLEAR, irq_mask); 108 109 /* Force INTC to recompute IRQ availability */ 110 INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR); 111 } 112 113 static void 114 omap2icu_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask) 115 { 116 struct omap2icu_softc * const sc = PICTOSOFTC(pic); 117 const size_t group = irqbase / 32; 118 119 INTC_WRITE(sc, group, INTC_MIR_SET, irq_mask); 120 sc->sc_enabled_irqs[group] &= ~irq_mask; 121 } 122 123 /* 124 * Called with interrupts disabled 125 */ 126 static int 127 find_pending_irqs(struct omap2icu_softc *sc, size_t group) 128 { 129 uint32_t pending = INTC_READ(sc, group, INTC_PENDING_IRQ); 130 131 KASSERT((sc->sc_enabled_irqs[group] & pending) == pending); 132 133 if (pending == 0) 134 return 0; 135 136 return pic_mark_pending_sources(&sc->sc_pic, group * 32, pending); 137 } 138 139 static void 140 omap_irq_handler(void *frame) 141 { 142 struct cpu_info * const ci = curcpu(); 143 struct omap2icu_softc * const sc = intc_softc; 144 const int oldipl = ci->ci_cpl; 145 const uint32_t oldipl_mask = __BIT(oldipl); 146 int ipl_mask = 0; 147 148 ci->ci_data.cpu_nintr++; 149 150 if (sc->sc_enabled_irqs[0]) 151 ipl_mask |= find_pending_irqs(sc, 0); 152 if (sc->sc_enabled_irqs[1]) 153 ipl_mask |= find_pending_irqs(sc, 1); 154 if (sc->sc_enabled_irqs[2]) 155 ipl_mask |= find_pending_irqs(sc, 2); 156 if (sc->sc_enabled_irqs[3]) 157 ipl_mask |= find_pending_irqs(sc, 3); 158 159 /* force INTC to recomputq IRQ */ 160 INTC_WRITE(sc, 0, INTC_CONTROL, INTC_CONTROL_NEWIRQAGR); 161 162 /* 163 * Record the pending_ipls and deliver them if we can. 164 */ 165 if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 166 pic_do_pending_ints(I32_bit, oldipl, frame); 167 } 168 169 void 170 omap2icu_establish_irq(struct pic_softc *pic, struct intrsource *is) 171 { 172 KASSERT(is->is_irq < PICTOSOFTC(pic)->sc_pic.pic_maxsources); 173 KASSERT(is->is_type == IST_LEVEL); 174 } 175 176 static void 177 omap2icu_set_priority(struct pic_softc *pic, int ipl) 178 { 179 curcpu()->ci_cpl = ipl; 180 } 181 182 static void * 183 omapintc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 184 int (*func)(void *), void *arg) 185 { 186 const u_int irq = be32toh(specifier[0]); 187 if (irq >= INTC_MAX_SOURCES) { 188 device_printf(dev, "IRQ %u is invalid\n", irq); 189 return NULL; 190 } 191 192 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 193 return intr_establish(irq, ipl, IST_LEVEL | mpsafe, func, arg); 194 } 195 196 static void 197 omapintc_fdt_disestablish(device_t dev, void *ih) 198 { 199 intr_disestablish(ih); 200 } 201 202 static bool 203 omapintc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 204 { 205 if (!specifier) 206 return false; 207 208 const u_int irq = be32toh(specifier[0]); 209 snprintf(buf, buflen, "INTC irq %d", irq); 210 return true; 211 } 212 213 static const struct fdtbus_interrupt_controller_func omapintc_fdt_funcs = { 214 .establish = omapintc_fdt_establish, 215 .disestablish = omapintc_fdt_disestablish, 216 .intrstr = omapintc_fdt_intrstr, 217 }; 218 219 int 220 omap2icu_match(device_t parent, cfdata_t cf, void *aux) 221 { 222 struct fdt_attach_args * const faa = aux; 223 224 static const char * const compatible[] = { 225 "ti,am33xx-intc", 226 NULL 227 }; 228 229 return of_match_compatible(faa->faa_phandle, compatible); 230 } 231 232 void 233 omap2icu_attach(device_t parent, device_t self, void *aux) 234 { 235 struct omap2icu_softc * const sc = device_private(self); 236 struct fdt_attach_args * const faa = aux; 237 const int phandle = faa->faa_phandle; 238 bus_addr_t addr; 239 bus_size_t size; 240 int error; 241 242 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 243 aprint_error(": couldn't get registers\n"); 244 return; 245 } 246 247 sc->sc_dev = self; 248 sc->sc_memt = faa->faa_bst; 249 if (bus_space_map(sc->sc_memt, addr, size, 0, &sc->sc_memh) != 0) { 250 aprint_error(": couldn't map registers\n"); 251 return; 252 } 253 254 aprint_naive("\n"); 255 aprint_normal("\n"); 256 257 INTC_WRITE(sc, 0, INTC_MIR_SET, 0xffffffff); 258 INTC_WRITE(sc, 1, INTC_MIR_SET, 0xffffffff); 259 INTC_WRITE(sc, 2, INTC_MIR_SET, 0xffffffff); 260 261 sc->sc_dev = self; 262 self->dv_private = sc; 263 264 sc->sc_pic.pic_ops = &omap2icu_picops; 265 sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES; 266 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc"); 267 pic_add(&sc->sc_pic, 0); 268 error = fdtbus_register_interrupt_controller(self, phandle, 269 &omapintc_fdt_funcs); 270 if (error) { 271 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 272 error); 273 return; 274 } 275 276 KASSERT(intc_softc == NULL); 277 intc_softc = sc; 278 arm_fdt_irq_set_handler(omap_irq_handler); 279 } 280 281 CFATTACH_DECL_NEW(omapintc, 282 sizeof(struct omap2icu_softc), 283 omap2icu_match, omap2icu_attach, 284 NULL, NULL); 285