xref: /netbsd-src/sys/arch/arm/ti/ti_gpio.c (revision 15a984a0d95c8f96abe9717ee6241762c55dc106) 
1 /* $NetBSD: ti_gpio.c,v 1.14 2021/08/07 16:18:46 thorpej Exp $ */
2 
3 /*-
4  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: ti_gpio.c,v 1.14 2021/08/07 16:18:46 thorpej Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/bitops.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/gpio.h>
37 #include <sys/intr.h>
38 #include <sys/kmem.h>
39 #include <sys/lwp.h>
40 #include <sys/mutex.h>
41 #include <sys/systm.h>
42 
43 #include <dev/fdt/fdtvar.h>
44 #include <dev/gpio/gpiovar.h>
45 
46 #include <arm/ti/ti_prcm.h>
47 
48 #define	TI_GPIO_NPINS			32
49 
50 enum ti_gpio_type {
51 	TI_GPIO_OMAP3,
52 	TI_GPIO_OMAP4,
53 	TI_NGPIO
54 };
55 
56 enum {
57 	GPIO_IRQSTATUS1,
58 	GPIO_IRQENABLE1,	/* OMAP3 */
59 	GPIO_IRQENABLE1_SET,	/* OMAP4 */
60 	GPIO_IRQENABLE1_CLR,	/* OMAP4 */
61 	GPIO_OE,
62 	GPIO_DATAIN,
63 	GPIO_DATAOUT,
64 	GPIO_LEVELDETECT0,
65 	GPIO_LEVELDETECT1,
66 	GPIO_RISINGDETECT,
67 	GPIO_FALLINGDETECT,
68 	GPIO_CLEARDATAOUT,
69 	GPIO_SETDATAOUT,
70 	GPIO_NREG
71 };
72 
73 static const u_int ti_gpio_regmap[TI_NGPIO][GPIO_NREG] = {
74 	[TI_GPIO_OMAP3] = {
75 		[GPIO_IRQSTATUS1]	= 0x18,
76 		[GPIO_IRQENABLE1]	= 0x1c,
77 		[GPIO_OE]		= 0x34,
78 		[GPIO_DATAIN]		= 0x38,
79 		[GPIO_DATAOUT]		= 0x3c,
80 		[GPIO_LEVELDETECT0]	= 0x40,
81 		[GPIO_LEVELDETECT1]	= 0x44,
82 		[GPIO_RISINGDETECT]	= 0x48,
83 		[GPIO_FALLINGDETECT]	= 0x4c,
84 		[GPIO_CLEARDATAOUT]	= 0x90,
85 		[GPIO_SETDATAOUT]	= 0x94,
86 	},
87 	[TI_GPIO_OMAP4] = {
88 		[GPIO_IRQSTATUS1]	= 0x2c,
89 		[GPIO_IRQENABLE1_SET]	= 0x34,
90 		[GPIO_IRQENABLE1_CLR]	= 0x38,
91 		[GPIO_OE]		= 0x134,
92 		[GPIO_DATAIN]		= 0x138,
93 		[GPIO_DATAOUT]		= 0x13c,
94 		[GPIO_LEVELDETECT0]	= 0x140,
95 		[GPIO_LEVELDETECT1]	= 0x144,
96 		[GPIO_RISINGDETECT]	= 0x148,
97 		[GPIO_FALLINGDETECT]	= 0x14c,
98 		[GPIO_CLEARDATAOUT]	= 0x190,
99 		[GPIO_SETDATAOUT]	= 0x194,
100 	},
101 };
102 
103 static const struct device_compatible_entry compat_data[] = {
104 	{ .compat = "ti,omap3-gpio",	.value = TI_GPIO_OMAP3 },
105 	{ .compat = "ti,omap4-gpio",	.value = TI_GPIO_OMAP4 },
106 	DEVICE_COMPAT_EOL
107 };
108 
109 struct ti_gpio_intr {
110 	u_int intr_pin;
111 	int (*intr_func)(void *);
112 	void *intr_arg;
113 	bool intr_mpsafe;
114 };
115 
116 struct ti_gpio_softc {
117 	device_t sc_dev;
118 	bus_space_tag_t sc_bst;
119 	bus_space_handle_t sc_bsh;
120 	kmutex_t sc_lock;
121 	enum ti_gpio_type sc_type;
122 	const char *sc_modname;
123 	void *sc_ih;
124 
125 	struct gpio_chipset_tag sc_gp;
126 	gpio_pin_t sc_pins[TI_GPIO_NPINS];
127 	bool sc_pinout[TI_GPIO_NPINS];
128 	struct ti_gpio_intr sc_intr[TI_GPIO_NPINS];
129 	device_t sc_gpiodev;
130 };
131 
132 struct ti_gpio_pin {
133 	struct ti_gpio_softc *pin_sc;
134 	u_int pin_nr;
135 	int pin_flags;
136 	bool pin_actlo;
137 };
138 
139 #define RD4(sc, reg) 		\
140     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)])
141 #define WR4(sc, reg, val) 	\
142     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, ti_gpio_regmap[(sc)->sc_type][(reg)], (val))
143 
144 static int	ti_gpio_match(device_t, cfdata_t, void *);
145 static void	ti_gpio_attach(device_t, device_t, void *);
146 
147 CFATTACH_DECL_NEW(ti_gpio, sizeof(struct ti_gpio_softc),
148 	ti_gpio_match, ti_gpio_attach, NULL, NULL);
149 
150 static int
151 ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags)
152 {
153 	uint32_t oe;
154 
155 	KASSERT(mutex_owned(&sc->sc_lock));
156 
157 	oe = RD4(sc, GPIO_OE);
158 	if (flags & GPIO_PIN_INPUT)
159 		oe |= __BIT(pin);
160 	else if (flags & GPIO_PIN_OUTPUT)
161 		oe &= ~__BIT(pin);
162 	WR4(sc, GPIO_OE, oe);
163 
164 	sc->sc_pinout[pin] = (flags & GPIO_PIN_OUTPUT) != 0;
165 
166 	return 0;
167 }
168 
169 static void *
170 ti_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
171 {
172 	struct ti_gpio_softc * const sc = device_private(dev);
173 	struct ti_gpio_pin *gpin;
174 	const u_int *gpio = data;
175 	int error;
176 
177 	if (len != 12)
178 		return NULL;
179 
180 	const uint8_t pin = be32toh(gpio[1]) & 0xff;
181 	const bool actlo = be32toh(gpio[2]) & 1;
182 
183 	if (pin >= __arraycount(sc->sc_pins))
184 		return NULL;
185 
186 	mutex_enter(&sc->sc_lock);
187 	error = ti_gpio_ctl(sc, pin, flags);
188 	mutex_exit(&sc->sc_lock);
189 
190 	if (error != 0)
191 		return NULL;
192 
193 	gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
194 	gpin->pin_sc = sc;
195 	gpin->pin_nr = pin;
196 	gpin->pin_flags = flags;
197 	gpin->pin_actlo = actlo;
198 
199 	return gpin;
200 }
201 
202 static void
203 ti_gpio_release(device_t dev, void *priv)
204 {
205 	struct ti_gpio_softc * const sc = device_private(dev);
206 	struct ti_gpio_pin *pin = priv;
207 
208 	mutex_enter(&sc->sc_lock);
209 	ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
210 	mutex_exit(&sc->sc_lock);
211 
212 	kmem_free(pin, sizeof(*pin));
213 }
214 
215 static int
216 ti_gpio_read(device_t dev, void *priv, bool raw)
217 {
218 	struct ti_gpio_softc * const sc = device_private(dev);
219 	struct ti_gpio_pin *pin = priv;
220 	uint32_t data;
221 	int val;
222 
223 	KASSERT(sc == pin->pin_sc);
224 
225 	const uint32_t data_mask = __BIT(pin->pin_nr);
226 
227 	/* No lock required for reads */
228 	if (sc->sc_pinout[pin->pin_nr])
229 		data = RD4(sc, GPIO_DATAOUT);
230 	else
231 		data = RD4(sc, GPIO_DATAIN);
232 	val = __SHIFTOUT(data, data_mask);
233 	if (!raw && pin->pin_actlo)
234 		val = !val;
235 
236 	return val;
237 }
238 
239 static void
240 ti_gpio_write(device_t dev, void *priv, int val, bool raw)
241 {
242 	struct ti_gpio_softc * const sc = device_private(dev);
243 	struct ti_gpio_pin *pin = priv;
244 
245 	KASSERT(sc == pin->pin_sc);
246 
247 	const uint32_t data_mask = __BIT(pin->pin_nr);
248 
249 	if (!raw && pin->pin_actlo)
250 		val = !val;
251 
252 	const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
253 
254 	WR4(sc, data_reg, data_mask);
255 }
256 
257 static struct fdtbus_gpio_controller_func ti_gpio_funcs = {
258 	.acquire = ti_gpio_acquire,
259 	.release = ti_gpio_release,
260 	.read = ti_gpio_read,
261 	.write = ti_gpio_write,
262 };
263 
264 static void
265 ti_gpio_intr_disestablish(device_t dev, void *ih)
266 {
267 	struct ti_gpio_softc * const sc = device_private(dev);
268 	struct ti_gpio_intr *intr = ih;
269 	const u_int pin = intr->intr_pin;
270 	const uint32_t pin_mask = __BIT(pin);
271 	uint32_t val;
272 
273 	/* Disable interrupts */
274 	if (sc->sc_type == TI_GPIO_OMAP3) {
275 		val = RD4(sc, GPIO_IRQENABLE1);
276 		WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask);
277 	} else {
278 		WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask);
279 	}
280 
281 	intr->intr_func = NULL;
282 	intr->intr_arg = NULL;
283 }
284 
285 static void *
286 ti_gpio_intr_establish(device_t dev, u_int *specifier, int ipl, int flags,
287     int (*func)(void *), void *arg, const char *xname)
288 {
289 	struct ti_gpio_softc * const sc = device_private(dev);
290 	uint32_t val;
291 
292 	/* 1st cell is the pin */
293 	/* 2nd cell is flags */
294 	const u_int pin = be32toh(specifier[0]);
295 	const u_int type = be32toh(specifier[2]) & 0xf;
296 
297 	if (ipl != IPL_VM || pin >= __arraycount(sc->sc_pins))
298 		return NULL;
299 
300 	/*
301 	 * Enabling both high and low level triggers will cause the GPIO
302 	 * controller to always assert the interrupt.
303 	 */
304 	if ((type & (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL)) ==
305 	    (FDT_INTR_TYPE_LOW_LEVEL|FDT_INTR_TYPE_HIGH_LEVEL))
306 		return NULL;
307 
308 	if (sc->sc_intr[pin].intr_func != NULL)
309 		return NULL;
310 
311 	/* Set pin as input */
312 	if (ti_gpio_ctl(sc, pin, GPIO_PIN_INPUT) != 0)
313 		return NULL;
314 
315 	sc->sc_intr[pin].intr_pin = pin;
316 	sc->sc_intr[pin].intr_func = func;
317 	sc->sc_intr[pin].intr_arg = arg;
318 	sc->sc_intr[pin].intr_mpsafe = (flags & FDT_INTR_MPSAFE) != 0;
319 
320 	const uint32_t pin_mask = __BIT(pin);
321 
322 	/* Configure triggers */
323 	val = RD4(sc, GPIO_LEVELDETECT0);
324 	if ((type & FDT_INTR_TYPE_LOW_LEVEL) != 0)
325 		val |= pin_mask;
326 	else
327 		val &= ~pin_mask;
328 	WR4(sc, GPIO_LEVELDETECT0, val);
329 
330 	val = RD4(sc, GPIO_LEVELDETECT1);
331 	if ((type & FDT_INTR_TYPE_HIGH_LEVEL) != 0)
332 		val |= pin_mask;
333 	else
334 		val &= ~pin_mask;
335 	WR4(sc, GPIO_LEVELDETECT1, val);
336 
337 	val = RD4(sc, GPIO_RISINGDETECT);
338 	if ((type & FDT_INTR_TYPE_POS_EDGE) != 0)
339 		val |= pin_mask;
340 	else
341 		val &= ~pin_mask;
342 	WR4(sc, GPIO_RISINGDETECT, val);
343 
344 	val = RD4(sc, GPIO_FALLINGDETECT);
345 	if ((type & FDT_INTR_TYPE_NEG_EDGE) != 0)
346 		val |= pin_mask;
347 	else
348 		val &= ~pin_mask;
349 	WR4(sc, GPIO_FALLINGDETECT, val);
350 
351 	/* Enable interrupts */
352 	if (sc->sc_type == TI_GPIO_OMAP3) {
353 		val = RD4(sc, GPIO_IRQENABLE1);
354 		WR4(sc, GPIO_IRQENABLE1, val | pin_mask);
355 	} else {
356 		WR4(sc, GPIO_IRQENABLE1_SET, pin_mask);
357 	}
358 
359 	return &sc->sc_intr[pin];
360 }
361 
362 static bool
363 ti_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen)
364 {
365 	struct ti_gpio_softc * const sc = device_private(dev);
366 
367 	/* 1st cell is the pin */
368 	/* 2nd cell is flags */
369 	const u_int pin = be32toh(specifier[0]);
370 
371 	if (pin >= __arraycount(sc->sc_pins))
372 		return false;
373 
374 	snprintf(buf, buflen, "%s pin %d", sc->sc_modname, pin);
375 	return true;
376 }
377 
378 static struct fdtbus_interrupt_controller_func ti_gpio_intrfuncs = {
379 	.establish = ti_gpio_intr_establish,
380 	.disestablish = ti_gpio_intr_disestablish,
381 	.intrstr = ti_gpio_intrstr,
382 };
383 
384 static int
385 ti_gpio_pin_read(void *priv, int pin)
386 {
387 	struct ti_gpio_softc * const sc = priv;
388 	uint32_t data;
389 	int val;
390 
391 	KASSERT(pin < __arraycount(sc->sc_pins));
392 
393 	const uint32_t data_mask = __BIT(pin);
394 
395 	data = RD4(sc, GPIO_DATAIN);
396 	val = __SHIFTOUT(data, data_mask);
397 
398 	return val;
399 }
400 
401 static void
402 ti_gpio_pin_write(void *priv, int pin, int val)
403 {
404 	struct ti_gpio_softc * const sc = priv;
405 
406 	KASSERT(pin < __arraycount(sc->sc_pins));
407 
408 	const u_int data_reg = val ? GPIO_SETDATAOUT : GPIO_CLEARDATAOUT;
409 	const uint32_t data_mask = __BIT(pin);
410 
411 	WR4(sc, data_reg, data_mask);
412 }
413 
414 static void
415 ti_gpio_pin_ctl(void *priv, int pin, int flags)
416 {
417 	struct ti_gpio_softc * const sc = priv;
418 
419 	KASSERT(pin < __arraycount(sc->sc_pins));
420 
421 	mutex_enter(&sc->sc_lock);
422 	ti_gpio_ctl(sc, pin, flags);
423 	mutex_exit(&sc->sc_lock);
424 }
425 
426 static void
427 ti_gpio_attach_ports(struct ti_gpio_softc *sc)
428 {
429 	struct gpio_chipset_tag *gp = &sc->sc_gp;
430 	struct gpiobus_attach_args gba;
431 	u_int pin;
432 
433 	gp->gp_cookie = sc;
434 	gp->gp_pin_read = ti_gpio_pin_read;
435 	gp->gp_pin_write = ti_gpio_pin_write;
436 	gp->gp_pin_ctl = ti_gpio_pin_ctl;
437 
438 	for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
439 		sc->sc_pins[pin].pin_num = pin;
440 		sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
441 		sc->sc_pins[pin].pin_state = ti_gpio_pin_read(sc, pin);
442 	}
443 
444 	memset(&gba, 0, sizeof(gba));
445 	gba.gba_gc = gp;
446 	gba.gba_pins = sc->sc_pins;
447 	gba.gba_npins = __arraycount(sc->sc_pins);
448 	sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE);
449 }
450 
451 static int
452 ti_gpio_intr(void *priv)
453 {
454 	struct ti_gpio_softc * const sc = priv;
455 	uint32_t status;
456 	u_int bit;
457 	int rv = 0;
458 
459 	status = RD4(sc, GPIO_IRQSTATUS1);
460 	WR4(sc, GPIO_IRQSTATUS1, status);
461 
462 	while ((bit = ffs32(status)) != 0) {
463 		const u_int pin = bit - 1;
464 		const uint32_t pin_mask = __BIT(pin);
465 		struct ti_gpio_intr *intr = &sc->sc_intr[pin];
466 		status &= ~pin_mask;
467 		if (intr->intr_func == NULL)
468 			continue;
469 		if (!intr->intr_mpsafe)
470 			KERNEL_LOCK(1, curlwp);
471 		rv |= intr->intr_func(intr->intr_arg);
472 		if (!intr->intr_mpsafe)
473 			KERNEL_UNLOCK_ONE(curlwp);
474 	}
475 
476 	return rv;
477 }
478 
479 static int
480 ti_gpio_match(device_t parent, cfdata_t cf, void *aux)
481 {
482 	struct fdt_attach_args * const faa = aux;
483 
484 	return of_compatible_match(faa->faa_phandle, compat_data);
485 }
486 
487 static void
488 ti_gpio_attach(device_t parent, device_t self, void *aux)
489 {
490 	struct ti_gpio_softc * const sc = device_private(self);
491 	struct fdt_attach_args * const faa = aux;
492 	const int phandle = faa->faa_phandle;
493 	char intrstr[128];
494 	bus_addr_t addr;
495 	bus_size_t size;
496 
497 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
498 		aprint_error(": couldn't get registers\n");
499 		return;
500 	}
501 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
502 		aprint_error(": couldn't decode interrupt\n");
503 		return;
504 	}
505 	if (ti_prcm_enable_hwmod(phandle, 0) != 0) {
506 		aprint_error(": couldn't enable module\n");
507 		return;
508 	}
509 
510 	sc->sc_dev = self;
511 	sc->sc_bst = faa->faa_bst;
512 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
513 		aprint_error(": couldn't map registers\n");
514 		return;
515 	}
516 	sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
517 	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
518 
519 	sc->sc_modname = fdtbus_get_string(phandle, "ti,hwmods");
520 	if (sc->sc_modname == NULL)
521 		sc->sc_modname = fdtbus_get_string(OF_parent(phandle), "ti,hwmods");
522 	if (sc->sc_modname == NULL)
523 		sc->sc_modname = kmem_asprintf("gpio@%" PRIxBUSADDR, addr);
524 
525 	aprint_naive("\n");
526 	aprint_normal(": GPIO (%s)\n", sc->sc_modname);
527 
528 	fdtbus_register_gpio_controller(self, phandle, &ti_gpio_funcs);
529 
530 	ti_gpio_attach_ports(sc);
531 
532 	sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
533 	    FDT_INTR_MPSAFE, ti_gpio_intr, sc, device_xname(self));
534 	if (sc->sc_ih == NULL) {
535 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
536 		    intrstr);
537 		return;
538 	}
539 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
540 	fdtbus_register_interrupt_controller(self, phandle, &ti_gpio_intrfuncs);
541 }
542