1 /* $NetBSD: sunxi_usbphy.c,v 1.17 2022/06/28 05:19:03 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_usbphy.c,v 1.17 2022/06/28 05:19:03 skrll Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 /* PHY control registers */ 43 #define PHYCTL_ICR 0x00 44 #define PHYCTL_ICR_ID_PULLUP __BIT(17) 45 #define PHYCTL_ICR_DPDM_PULLUP __BIT(16) 46 #define PHYCTL_ICR_FORCE_ID __BITS(15,14) 47 #define PHYCTL_ICR_FORCE_ID_LOW 2 48 #define PHYCTL_ICR_FORCE_ID_HIGH 3 49 #define PHYCTL_ICR_FORCE_VBUS __BITS(13,12) 50 #define PHYCTL_ICR_FORCE_VBUS_LOW 2 51 #define PHYCTL_ICR_FORCE_VBUS_HIGH 3 52 #define PHYCTL_A10 0x04 53 #define PHYCTL_A33 0x10 54 #define PHYCTL_ADDR __BITS(15,8) 55 #define PHYCTL_DATA __BIT(7) 56 #define PHYCTL_OTG_CFG 0x20 57 #define PHYCTL_OTG_ROUTE_OTG __BIT(0) 58 59 /* PHY registers */ 60 #define PHY_RES45_CAL_EN 0x0c 61 #define PHY_TX_AMPLITUDE_TUNE 0x20 62 #define PHY_DISCON_TH_SEL 0x2a 63 64 /* PMU registers */ 65 #define PMU_CFG 0x00 66 #define AHB_INCR8 __BIT(10) 67 #define AHB_INCR4 __BIT(9) 68 #define AHB_INCRX_ALIGN __BIT(8) 69 #define ULPI_BYPASS __BIT(0) 70 #define PMU_UNK_H3 0x10 71 #define PMU_UNK_H3_CLR __BIT(1) 72 73 static int sunxi_usbphy_match(device_t, cfdata_t, void *); 74 static void sunxi_usbphy_attach(device_t, device_t, void *); 75 76 enum sunxi_usbphy_type { 77 USBPHY_A10 = 1, 78 USBPHY_A13, 79 USBPHY_A20, 80 USBPHY_A31, 81 USBPHY_A64, 82 USBPHY_A83T, 83 USBPHY_H3, 84 USBPHY_H6, 85 }; 86 87 static const struct device_compatible_entry compat_data[] = { 88 { .compat = "allwinner,sun4i-a10-usb-phy", .value = USBPHY_A10 }, 89 { .compat = "allwinner,sun5i-a13-usb-phy", .value = USBPHY_A13 }, 90 { .compat = "allwinner,sun6i-a31-usb-phy", .value = USBPHY_A31 }, 91 { .compat = "allwinner,sun7i-a20-usb-phy", .value = USBPHY_A20 }, 92 { .compat = "allwinner,sun8i-a83t-usb-phy", .value = USBPHY_A83T }, 93 { .compat = "allwinner,sun8i-h3-usb-phy", .value = USBPHY_H3 }, 94 { .compat = "allwinner,sun8i-v3s-usb-phy", .value = USBPHY_H3 }, 95 { .compat = "allwinner,sun50i-a64-usb-phy", .value = USBPHY_A64 }, 96 { .compat = "allwinner,sun50i-h6-usb-phy", .value = USBPHY_H6 }, 97 DEVICE_COMPAT_EOL 98 }; 99 100 #define SUNXI_MAXUSBPHY 4 101 102 struct sunxi_usbphy { 103 u_int phy_index; 104 bus_space_handle_t phy_bsh; 105 struct fdtbus_regulator *phy_reg; 106 }; 107 108 struct sunxi_usbphy_softc { 109 device_t sc_dev; 110 bus_space_tag_t sc_bst; 111 bus_space_handle_t sc_bsh_phy_ctrl; 112 enum sunxi_usbphy_type sc_type; 113 114 struct sunxi_usbphy sc_phys[SUNXI_MAXUSBPHY]; 115 u_int sc_nphys; 116 117 struct fdtbus_gpio_pin *sc_gpio_id_det; 118 struct fdtbus_gpio_pin *sc_gpio_vbus_det; 119 }; 120 121 #define PHYCTL_READ(sc, reg) \ 122 bus_space_read_4((sc)->sc_bst, \ 123 (sc)->sc_bsh_phy_ctrl, (reg)) 124 #define PHYCTL_WRITE(sc, reg, val) \ 125 bus_space_write_4((sc)->sc_bst, \ 126 (sc)->sc_bsh_phy_ctrl, (reg), (val)) 127 #define PMU_READ(sc, id, reg) \ 128 bus_space_read_4((sc)->sc_bst, \ 129 (sc)->sc_phys[(id)].phy_bsh, (reg)) 130 #define PMU_WRITE(sc, id, reg, val) \ 131 bus_space_write_4((sc)->sc_bst, \ 132 (sc)->sc_phys[(id)].phy_bsh, (reg), (val)) 133 134 CFATTACH_DECL_NEW(sunxi_usbphy, sizeof(struct sunxi_usbphy_softc), 135 sunxi_usbphy_match, sunxi_usbphy_attach, NULL, NULL); 136 137 static void 138 sunxi_usbphy_write(struct sunxi_usbphy_softc *sc, 139 struct sunxi_usbphy *phy, u_int bit_addr, u_int bits, 140 u_int len) 141 { 142 const uint32_t usbc_mask = __BIT(phy->phy_index * 2); 143 bus_size_t reg; 144 uint32_t val; 145 146 switch (sc->sc_type) { 147 case USBPHY_A10: 148 case USBPHY_A13: 149 case USBPHY_A20: 150 case USBPHY_A31: 151 reg = PHYCTL_A10; 152 break; 153 case USBPHY_H3: 154 case USBPHY_H6: 155 case USBPHY_A64: 156 case USBPHY_A83T: 157 reg = PHYCTL_A33; 158 break; 159 default: 160 panic("unsupported phy type"); 161 } 162 163 if (reg == PHYCTL_A33) 164 PHYCTL_WRITE(sc, reg, 0); 165 166 for (; len > 0; bit_addr++, bits >>= 1, len--) { 167 val = PHYCTL_READ(sc, reg); 168 val &= ~PHYCTL_ADDR; 169 val |= __SHIFTIN(bit_addr, PHYCTL_ADDR); 170 PHYCTL_WRITE(sc, reg, val); 171 172 val = PHYCTL_READ(sc, reg); 173 val &= ~PHYCTL_DATA; 174 val |= __SHIFTIN(bits & 1, PHYCTL_DATA); 175 PHYCTL_WRITE(sc, reg, val); 176 177 PHYCTL_READ(sc, reg); 178 val |= usbc_mask; 179 PHYCTL_WRITE(sc, reg, val); 180 181 PHYCTL_READ(sc, reg); 182 val &= ~usbc_mask; 183 PHYCTL_WRITE(sc, reg, val); 184 } 185 } 186 187 static bool 188 sunxi_usbphy_vbus_detect(struct sunxi_usbphy_softc *sc) 189 { 190 if (sc->sc_gpio_vbus_det) 191 return fdtbus_gpio_read(sc->sc_gpio_vbus_det); 192 return 1; 193 } 194 195 static void * 196 sunxi_usbphy_acquire(device_t dev, const void *data, size_t len) 197 { 198 struct sunxi_usbphy_softc * const sc = device_private(dev); 199 200 if (len != 4) 201 return NULL; 202 203 const int phy_id = be32dec(data); 204 if (phy_id >= sc->sc_nphys || !sc->sc_phys[phy_id].phy_bsh) 205 return NULL; 206 207 return &sc->sc_phys[phy_id]; 208 } 209 210 static void 211 sunxi_usbphy_release(device_t dev, void *priv) 212 { 213 } 214 215 static int 216 sunxi_usbphy_enable(device_t dev, void *priv, bool enable) 217 { 218 struct sunxi_usbphy_softc * const sc = device_private(dev); 219 struct sunxi_usbphy * const phy = priv; 220 u_int disc_thresh; 221 bool phy0_reroute; 222 uint32_t val; 223 224 switch (sc->sc_type) { 225 case USBPHY_A13: 226 disc_thresh = 0x2; 227 phy0_reroute = false; 228 break; 229 case USBPHY_A10: 230 case USBPHY_A20: 231 case USBPHY_A31: 232 disc_thresh = 0x3; 233 phy0_reroute = false; 234 break; 235 case USBPHY_A64: 236 case USBPHY_H3: 237 case USBPHY_H6: 238 disc_thresh = 0x3; 239 phy0_reroute = true; 240 break; 241 case USBPHY_A83T: 242 disc_thresh = 0x0; 243 phy0_reroute = false; 244 break; 245 default: 246 aprint_error_dev(dev, "unsupported board\n"); 247 return ENXIO; 248 } 249 250 if (phy->phy_bsh) { 251 /* Enable/disable passby */ 252 const uint32_t mask = 253 ULPI_BYPASS|AHB_INCR8|AHB_INCR4|AHB_INCRX_ALIGN; 254 val = PMU_READ(sc, phy->phy_index, PMU_CFG); 255 if (enable) 256 val |= mask; 257 else 258 val &= ~mask; 259 PMU_WRITE(sc, phy->phy_index, PMU_CFG, val); 260 } 261 262 switch (sc->sc_type) { 263 case USBPHY_H3: 264 case USBPHY_A64: 265 if (enable && phy->phy_bsh) { 266 val = PMU_READ(sc, phy->phy_index, PMU_UNK_H3); 267 val &= ~PMU_UNK_H3_CLR; 268 PMU_WRITE(sc, phy->phy_index, PMU_UNK_H3, val); 269 } 270 break; 271 default: 272 break; 273 } 274 275 if (enable) { 276 switch (sc->sc_type) { 277 case USBPHY_A83T: 278 case USBPHY_H6: 279 break; 280 default: 281 if (phy->phy_index == 0) 282 sunxi_usbphy_write(sc, phy, PHY_RES45_CAL_EN, 0x1, 1); 283 sunxi_usbphy_write(sc, phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); 284 sunxi_usbphy_write(sc, phy, PHY_DISCON_TH_SEL, disc_thresh, 2); 285 break; 286 } 287 } 288 289 if (phy->phy_index == 0) { 290 const uint32_t mask = 291 PHYCTL_ICR_ID_PULLUP|PHYCTL_ICR_DPDM_PULLUP; 292 val = PHYCTL_READ(sc, PHYCTL_ICR); 293 294 if (enable) 295 val |= mask; 296 else 297 val &= ~mask; 298 299 /* XXX only host mode is supported */ 300 val &= ~PHYCTL_ICR_FORCE_ID; 301 val |= __SHIFTIN(PHYCTL_ICR_FORCE_ID_LOW, PHYCTL_ICR_FORCE_ID); 302 val &= ~PHYCTL_ICR_FORCE_VBUS; 303 val |= __SHIFTIN(PHYCTL_ICR_FORCE_VBUS_HIGH, PHYCTL_ICR_FORCE_VBUS); 304 305 PHYCTL_WRITE(sc, PHYCTL_ICR, val); 306 307 if (phy0_reroute) { 308 val = PHYCTL_READ(sc, PHYCTL_OTG_CFG); 309 val &= ~PHYCTL_OTG_ROUTE_OTG; 310 PHYCTL_WRITE(sc, PHYCTL_OTG_CFG, val); 311 } 312 } 313 314 if (phy->phy_reg == NULL) 315 return 0; 316 317 if (enable) { 318 /* If an external vbus is detected, do not enable phy 0 */ 319 if (phy->phy_index == 0 && sunxi_usbphy_vbus_detect(sc)) 320 return 0; 321 return fdtbus_regulator_enable(phy->phy_reg); 322 } else { 323 return fdtbus_regulator_disable(phy->phy_reg); 324 } 325 } 326 327 const struct fdtbus_phy_controller_func sunxi_usbphy_funcs = { 328 .acquire = sunxi_usbphy_acquire, 329 .release = sunxi_usbphy_release, 330 .enable = sunxi_usbphy_enable, 331 }; 332 333 static int 334 sunxi_usbphy_match(device_t parent, cfdata_t cf, void *aux) 335 { 336 struct fdt_attach_args * const faa = aux; 337 338 return of_compatible_match(faa->faa_phandle, compat_data); 339 } 340 341 static void 342 sunxi_usbphy_attach(device_t parent, device_t self, void *aux) 343 { 344 struct sunxi_usbphy_softc * const sc = device_private(self); 345 struct fdt_attach_args * const faa = aux; 346 const int phandle = faa->faa_phandle; 347 struct fdtbus_reset *rst; 348 struct sunxi_usbphy *phy; 349 struct clk *clk; 350 bus_addr_t addr; 351 bus_size_t size; 352 char pname[20]; 353 u_int n; 354 355 sc->sc_dev = self; 356 sc->sc_bst = faa->faa_bst; 357 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 358 359 if (fdtbus_get_reg_byname(phandle, "phy_ctrl", &addr, &size) != 0) { 360 aprint_error(": couldn't get phy ctrl registers\n"); 361 return; 362 } 363 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_phy_ctrl) != 0) { 364 aprint_error(": couldn't map phy ctrl registers\n"); 365 return; 366 } 367 368 for (sc->sc_nphys = 0; sc->sc_nphys < SUNXI_MAXUSBPHY; sc->sc_nphys++) { 369 phy = &sc->sc_phys[sc->sc_nphys]; 370 phy->phy_index = sc->sc_nphys; 371 snprintf(pname, sizeof(pname), "pmu%d", sc->sc_nphys); 372 if (fdtbus_get_reg_byname(phandle, pname, &addr, &size) != 0) { 373 continue; 374 } else if (bus_space_map(sc->sc_bst, addr, size, 0, &phy->phy_bsh) != 0) { 375 aprint_error(": failed to map reg #%d\n", sc->sc_nphys); 376 return; 377 } 378 /* Get optional regulator */ 379 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", sc->sc_nphys); 380 phy->phy_reg = fdtbus_regulator_acquire(phandle, pname); 381 } 382 383 /* Enable clocks */ 384 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 385 if (clk_enable(clk) != 0) { 386 aprint_error(": couldn't enable clock #%d\n", n); 387 return; 388 } 389 /* De-assert resets */ 390 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 391 if (fdtbus_reset_deassert(rst) != 0) { 392 aprint_error(": couldn't de-assert reset #%d\n", n); 393 return; 394 } 395 396 aprint_naive("\n"); 397 aprint_normal(": USB PHY\n"); 398 399 fdtbus_register_phy_controller(self, phandle, &sunxi_usbphy_funcs); 400 } 401