1 /* $NetBSD: sunxi_usb3phy.c,v 1.1 2018/05/01 23:59:42 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_usb3phy.c,v 1.1 2018/05/01 23:59:42 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define SUNXI_APP 0x00 43 #define APP_FORCE_VBUS __BITS(13,12) 44 45 #define SUNXI_PIPE_CLOCK_CONTROL 0x14 46 #define PCC_PIPE_CLK_OPEN __BIT(6) 47 48 #define SUNXI_PHY_TUNE_LOW 0x18 49 #define PTL_MAGIC 0x0047fc87 50 51 #define SUNXI_PHY_TUNE_HIGH 0x1c 52 #define PTH_TX_DEEMPH_3P5DB __BITS(24,19) 53 #define PTH_TX_DEEMPH_6DB __BITS(18,13) 54 #define PTH_TX_SWING_FULL __BITS(12,6) 55 #define PTH_LOS_BIAS __BITS(5,3) 56 #define PTH_TX_BOOST_LVL __BITS(2,0) 57 58 #define SUNXI_PHY_EXTERNAL_CONTROL 0x20 59 #define PEC_REF_SSP_EN __BIT(26) 60 #define PEC_SSC_EN __BIT(24) 61 #define PEC_EXTERN_VBUS __BITS(2,1) 62 63 static int sunxi_usb3phy_match(device_t, cfdata_t, void *); 64 static void sunxi_usb3phy_attach(device_t, device_t, void *); 65 66 enum sunxi_usb3phy_type { 67 USB3PHY_H6 = 1, 68 }; 69 70 static const struct of_compat_data compat_data[] = { 71 { "allwinner,sun50i-h6-usb3-phy", USB3PHY_H6 }, 72 { NULL } 73 }; 74 75 struct sunxi_usb3phy { 76 bus_space_tag_t phy_bst; 77 bus_space_handle_t phy_bsh; 78 struct fdtbus_regulator *phy_reg; 79 }; 80 81 struct sunxi_usb3phy_softc { 82 device_t sc_dev; 83 enum sunxi_usb3phy_type sc_type; 84 85 struct sunxi_usb3phy sc_phy; 86 87 struct fdtbus_gpio_pin *sc_gpio_id_det; 88 struct fdtbus_gpio_pin *sc_gpio_vbus_det; 89 }; 90 91 #define PHY_READ(phy, reg) \ 92 bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg)) 93 #define PHY_WRITE(phy, reg, val) \ 94 bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val)) 95 96 CFATTACH_DECL_NEW(sunxi_usb3phy, sizeof(struct sunxi_usb3phy_softc), 97 sunxi_usb3phy_match, sunxi_usb3phy_attach, NULL, NULL); 98 99 static void * 100 sunxi_usb3phy_acquire(device_t dev, const void *data, size_t len) 101 { 102 struct sunxi_usb3phy_softc * const sc = device_private(dev); 103 104 return &sc->sc_phy; 105 } 106 107 static void 108 sunxi_usb3phy_release(device_t dev, void *priv) 109 { 110 } 111 112 static int 113 sunxi_usb3phy_enable(device_t dev, void *priv, bool enable) 114 { 115 struct sunxi_usb3phy * const phy = priv; 116 uint32_t val; 117 118 if (enable) { 119 val = PHY_READ(phy, SUNXI_PHY_EXTERNAL_CONTROL); 120 val |= PEC_EXTERN_VBUS; 121 val |= PEC_SSC_EN; 122 val |= PEC_REF_SSP_EN; 123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val); 124 125 val = PHY_READ(phy, SUNXI_PIPE_CLOCK_CONTROL); 126 val |= PCC_PIPE_CLK_OPEN; 127 PHY_WRITE(phy, SUNXI_PIPE_CLOCK_CONTROL, val); 128 129 val = PHY_READ(phy, SUNXI_APP); 130 val |= APP_FORCE_VBUS; 131 PHY_WRITE(phy, SUNXI_APP, val); 132 133 PHY_WRITE(phy, SUNXI_PHY_TUNE_LOW, PTL_MAGIC); 134 135 val = PHY_READ(phy, SUNXI_PHY_TUNE_HIGH); 136 val |= PTH_TX_BOOST_LVL; 137 val |= PTH_LOS_BIAS; 138 val &= ~PTH_TX_SWING_FULL; 139 val |= __SHIFTIN(0x55, PTH_TX_SWING_FULL); 140 val &= ~PTH_TX_DEEMPH_6DB; 141 val |= __SHIFTIN(0x20, PTH_TX_DEEMPH_6DB); 142 val &= ~PTH_TX_DEEMPH_3P5DB; 143 val |= __SHIFTIN(0x15, PTH_TX_DEEMPH_3P5DB); 144 PHY_WRITE(phy, SUNXI_PHY_TUNE_HIGH, val); 145 146 return phy->phy_reg ? fdtbus_regulator_enable(phy->phy_reg) : 0; 147 } else { 148 return phy->phy_reg ? fdtbus_regulator_disable(phy->phy_reg) : 0; 149 } 150 } 151 152 const struct fdtbus_phy_controller_func sunxi_usb3phy_funcs = { 153 .acquire = sunxi_usb3phy_acquire, 154 .release = sunxi_usb3phy_release, 155 .enable = sunxi_usb3phy_enable, 156 }; 157 158 static int 159 sunxi_usb3phy_match(device_t parent, cfdata_t cf, void *aux) 160 { 161 struct fdt_attach_args * const faa = aux; 162 163 return of_match_compat_data(faa->faa_phandle, compat_data); 164 } 165 166 static void 167 sunxi_usb3phy_attach(device_t parent, device_t self, void *aux) 168 { 169 struct sunxi_usb3phy_softc * const sc = device_private(self); 170 struct sunxi_usb3phy *phy = &sc->sc_phy; 171 struct fdt_attach_args * const faa = aux; 172 const int phandle = faa->faa_phandle; 173 struct fdtbus_reset *rst; 174 struct clk *clk; 175 bus_addr_t addr; 176 bus_size_t size; 177 u_int n; 178 179 sc->sc_dev = self; 180 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 181 182 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 183 aprint_error(": couldn't get phy registers\n"); 184 return; 185 } 186 187 phy->phy_bst = faa->faa_bst; 188 if (bus_space_map(phy->phy_bst, addr, size, 0, &phy->phy_bsh) != 0) { 189 aprint_error(": couldn't map phy registers\n"); 190 return; 191 } 192 193 /* Get optional regulator */ 194 phy->phy_reg = fdtbus_regulator_acquire(phandle, "phy-supply"); 195 196 /* Enable clocks */ 197 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 198 if (clk_enable(clk) != 0) { 199 aprint_error(": couldn't enable clock #%d\n", n); 200 return; 201 } 202 /* De-assert resets */ 203 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 204 if (fdtbus_reset_deassert(rst) != 0) { 205 aprint_error(": couldn't de-assert reset #%d\n", n); 206 return; 207 } 208 209 aprint_naive("\n"); 210 aprint_normal(": USB3 PHY\n"); 211 212 fdtbus_register_phy_controller(self, phandle, &sunxi_usb3phy_funcs); 213 } 214