1 /* $NetBSD: sunxi_sramc.c,v 1.11 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_sramc.c,v 1.11 2021/01/27 03:10:20 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 40 #include <dev/fdt/fdtvar.h> 41 #include <dev/fdt/syscon.h> 42 43 #include <arm/sunxi/sunxi_sramc.h> 44 45 static const struct device_compatible_entry compat_data[] = { 46 /* old compat string */ 47 { .compat = "allwinner,sun4i-a10-sram-controller" }, 48 { .compat = "allwinner,sun4i-a10-system-control" }, 49 { .compat = "allwinner,sun8i-h3-system-control" }, 50 { .compat = "allwinner,sun50i-a64-system-control" }, 51 { .compat = "allwinner,sun50i-h5-system-control" }, 52 { .compat = "allwinner,sun50i-h6-system-control" }, 53 DEVICE_COMPAT_EOL 54 }; 55 56 struct sunxi_sramc_area { 57 const char *desc; 58 bus_size_t reg; 59 uint32_t mask; 60 u_int flags; 61 #define SUNXI_SRAMC_F_SWAP __BIT(0) 62 }; 63 64 static const struct sunxi_sramc_area sunxi_sramc_area_a3_a4 = { 65 .desc = "SRAM A3/A4", 66 .reg = 0x04, 67 .mask = __BITS(5,4), 68 .flags = 0, 69 }; 70 71 static const struct sunxi_sramc_area sunxi_sramc_area_d = { 72 .desc = "SRAM D", 73 .reg = 0x04, 74 .mask = __BIT(0), 75 .flags = 0, 76 }; 77 78 static const struct sunxi_sramc_area sunxi_sramc_area_c = { 79 .desc = "SRAM C", 80 .reg = 0x04, 81 .mask = __BIT(24), 82 .flags = SUNXI_SRAMC_F_SWAP, 83 }; 84 85 static const struct device_compatible_entry sunxi_sramc_areas[] = { 86 { .compat = "allwinner,sun4i-a10-sram-a3-a4", 87 .data = &sunxi_sramc_area_a3_a4 }, 88 89 { .compat = "allwinner,sun4i-a10-sram-d", 90 .data = &sunxi_sramc_area_d }, 91 92 { .compat = "allwinner,sun50i-a64-sram-c", 93 .data = &sunxi_sramc_area_c }, 94 95 DEVICE_COMPAT_EOL 96 }; 97 98 struct sunxi_sramc_node { 99 int phandle; 100 const struct sunxi_sramc_area *area; 101 TAILQ_ENTRY(sunxi_sramc_node) nodes; 102 }; 103 104 struct sunxi_sramc_softc { 105 device_t sc_dev; 106 int sc_phandle; 107 bus_space_tag_t sc_bst; 108 bus_space_handle_t sc_bsh; 109 kmutex_t sc_lock; 110 struct syscon sc_syscon; 111 TAILQ_HEAD(, sunxi_sramc_node) sc_nodes; 112 }; 113 114 static struct sunxi_sramc_softc *sramc_softc = NULL; 115 116 #define SRAMC_READ(sc, reg) \ 117 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 118 #define SRAMC_WRITE(sc, reg, val) \ 119 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 120 121 static void 122 sunxi_sramc_init_mmio(struct sunxi_sramc_softc *sc, int phandle) 123 { 124 const struct device_compatible_entry *dce; 125 struct sunxi_sramc_node *node; 126 int child; 127 128 for (child = OF_child(phandle); child; child = OF_peer(child)) { 129 dce = of_compatible_lookup(child, sunxi_sramc_areas); 130 if (dce != NULL) { 131 node = kmem_alloc(sizeof(*node), KM_SLEEP); 132 node->phandle = child; 133 node->area = dce->data; 134 TAILQ_INSERT_TAIL(&sc->sc_nodes, node, nodes); 135 aprint_verbose_dev(sc->sc_dev, "area: %s\n", 136 node->area->desc); 137 } 138 } 139 } 140 141 static void 142 sunxi_sramc_init(struct sunxi_sramc_softc *sc) 143 { 144 const struct device_compatible_entry mmio_compat_data[] = { 145 { .compat = "mmio-sram" }, 146 DEVICE_COMPAT_EOL 147 }; 148 int child; 149 150 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 151 if (!of_compatible_match(child, mmio_compat_data)) 152 continue; 153 sunxi_sramc_init_mmio(sc, child); 154 } 155 } 156 157 static void 158 sunxi_sramc_lock(void *priv) 159 { 160 struct sunxi_sramc_softc * const sc = priv; 161 162 mutex_enter(&sc->sc_lock); 163 } 164 165 static void 166 sunxi_sramc_unlock(void *priv) 167 { 168 struct sunxi_sramc_softc * const sc = priv; 169 170 mutex_exit(&sc->sc_lock); 171 } 172 173 static uint32_t 174 sunxi_sramc_read_4(void *priv, bus_size_t reg) 175 { 176 struct sunxi_sramc_softc * const sc = priv; 177 178 KASSERT(mutex_owned(&sc->sc_lock)); 179 180 return SRAMC_READ(sc, reg); 181 } 182 183 static void 184 sunxi_sramc_write_4(void *priv, bus_size_t reg, uint32_t val) 185 { 186 struct sunxi_sramc_softc * const sc = priv; 187 188 KASSERT(mutex_owned(&sc->sc_lock)); 189 190 SRAMC_WRITE(sc, reg, val); 191 } 192 193 static int 194 sunxi_sramc_match(device_t parent, cfdata_t cf, void *aux) 195 { 196 struct fdt_attach_args * const faa = aux; 197 198 return of_compatible_match(faa->faa_phandle, compat_data); 199 } 200 201 static void 202 sunxi_sramc_attach(device_t parent, device_t self, void *aux) 203 { 204 struct sunxi_sramc_softc * const sc = device_private(self); 205 struct fdt_attach_args * const faa = aux; 206 const int phandle = faa->faa_phandle; 207 bus_addr_t addr; 208 bus_size_t size; 209 210 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 211 aprint_error(": couldn't get registers\n"); 212 return; 213 } 214 215 sc->sc_dev = self; 216 sc->sc_phandle = phandle; 217 sc->sc_bst = faa->faa_bst; 218 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 219 aprint_error(": couldn't map registers\n"); 220 return; 221 } 222 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 223 TAILQ_INIT(&sc->sc_nodes); 224 225 aprint_naive("\n"); 226 aprint_normal(": SRAM Controller\n"); 227 228 sunxi_sramc_init(sc); 229 230 KASSERT(sramc_softc == NULL); 231 sramc_softc = sc; 232 233 sc->sc_syscon.priv = sc; 234 sc->sc_syscon.lock = sunxi_sramc_lock; 235 sc->sc_syscon.unlock = sunxi_sramc_unlock; 236 sc->sc_syscon.read_4 = sunxi_sramc_read_4; 237 sc->sc_syscon.write_4 = sunxi_sramc_write_4; 238 fdtbus_register_syscon(self, phandle, &sc->sc_syscon); 239 } 240 241 CFATTACH_DECL_NEW(sunxi_sramc, sizeof(struct sunxi_sramc_softc), 242 sunxi_sramc_match, sunxi_sramc_attach, NULL, NULL); 243 244 static int 245 sunxi_sramc_map(const int node_phandle, u_int config) 246 { 247 struct sunxi_sramc_softc * const sc = sramc_softc; 248 struct sunxi_sramc_node *node; 249 uint32_t val; 250 251 if (sc == NULL) 252 return ENXIO; 253 254 TAILQ_FOREACH(node, &sc->sc_nodes, nodes) 255 if (node->phandle == node_phandle) { 256 if (config > __SHIFTOUT_MASK(node->area->mask)) 257 return ERANGE; 258 if ((node->area->flags & SUNXI_SRAMC_F_SWAP) != 0) 259 config = !config; 260 val = SRAMC_READ(sc, node->area->reg); 261 val &= ~node->area->mask; 262 val |= __SHIFTIN(config, node->area->mask); 263 SRAMC_WRITE(sc, node->area->reg, val); 264 return 0; 265 } 266 267 return EINVAL; 268 } 269 270 int 271 sunxi_sramc_claim(const int phandle) 272 { 273 const u_int *data; 274 int len; 275 276 data = fdtbus_get_prop(phandle, "allwinner,sram", &len); 277 if (data == NULL) 278 return ENOENT; 279 if (len != 8) 280 return EIO; 281 282 const int node_phandle = fdtbus_get_phandle_from_native(be32toh(data[0])); 283 const u_int config = be32toh(data[1]); 284 285 return sunxi_sramc_map(node_phandle, config); 286 } 287