1 /* $NetBSD: sunxi_rsb.c,v 1.8 2019/12/22 23:23:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rsb.c,v 1.8 2019/12/22 23:23:30 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <arm/sunxi/sunxi_rsb.h> 46 47 enum sunxi_rsb_type { 48 SUNXI_P2WI, 49 SUNXI_RSB, 50 }; 51 52 static const struct of_compat_data compat_data[] = { 53 { "allwinner,sun6i-a31-p2wi", SUNXI_P2WI }, 54 { "allwinner,sun8i-a23-rsb", SUNXI_RSB }, 55 { NULL } 56 }; 57 58 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 59 #define RSB_ADDR_PMIC_SECONDARY 0x745 60 #define RSB_ADDR_PERIPH_IC 0xe89 61 62 /* 63 * Device address to Run-time address mappings. 64 * 65 * Run-time address (RTA) is an 8-bit value used to address the device during 66 * a read or write transaction. The following are valid RTAs: 67 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 68 * 69 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 70 * and 0x4e for the peripheral IC (where applicable). 71 */ 72 static const struct { 73 uint16_t addr; 74 uint8_t rta; 75 } rsb_rtamap[] = { 76 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 77 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 78 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 79 { .addr = 0, .rta = 0 } 80 }; 81 82 struct sunxi_rsb_softc { 83 device_t sc_dev; 84 bus_space_tag_t sc_bst; 85 bus_space_handle_t sc_bsh; 86 enum sunxi_rsb_type sc_type; 87 struct i2c_controller sc_ic; 88 kmutex_t sc_intr_lock; 89 kcondvar_t sc_intr_wait; 90 device_t sc_i2cdev; 91 void *sc_ih; 92 uint32_t sc_stat; 93 bool sc_busy; 94 95 uint16_t sc_rsb_last_da; 96 }; 97 98 #define RSB_READ(sc, reg) \ 99 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 100 #define RSB_WRITE(sc, reg, val) \ 101 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 102 103 static int sunxi_rsb_exec(void *, i2c_op_t, i2c_addr_t, const void *, 104 size_t, void *, size_t, int); 105 106 static int sunxi_rsb_intr(void *); 107 static int sunxi_rsb_wait(struct sunxi_rsb_softc *, int); 108 static int sunxi_rsb_rsb_config(struct sunxi_rsb_softc *, 109 uint8_t, i2c_addr_t, int); 110 111 static int sunxi_rsb_match(device_t, cfdata_t, void *); 112 static void sunxi_rsb_attach(device_t, device_t, void *); 113 114 static i2c_tag_t 115 sunxi_rsb_get_tag(device_t dev) 116 { 117 struct sunxi_rsb_softc * const sc = device_private(dev); 118 119 return &sc->sc_ic; 120 } 121 122 static const struct fdtbus_i2c_controller_func sunxi_rsb_funcs = { 123 .get_tag = sunxi_rsb_get_tag, 124 }; 125 126 CFATTACH_DECL_NEW(sunxi_rsb, sizeof(struct sunxi_rsb_softc), 127 sunxi_rsb_match, sunxi_rsb_attach, NULL, NULL); 128 129 static int 130 sunxi_rsb_match(device_t parent, cfdata_t cf, void *aux) 131 { 132 struct fdt_attach_args * const faa = aux; 133 134 return of_match_compat_data(faa->faa_phandle, compat_data); 135 } 136 137 static void 138 sunxi_rsb_attach(device_t parent, device_t self, void *aux) 139 { 140 struct sunxi_rsb_softc * const sc = device_private(self); 141 struct fdt_attach_args * const faa = aux; 142 const int phandle = faa->faa_phandle; 143 struct fdtbus_reset *rst; 144 struct clk *clk; 145 char intrstr[128]; 146 bus_addr_t addr; 147 bus_size_t size; 148 149 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 150 aprint_error(": couldn't get registers\n"); 151 return; 152 } 153 154 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 155 aprint_error(": couldn't decode interrupt\n"); 156 return; 157 } 158 159 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 160 if (clk_enable(clk) != 0) { 161 aprint_error(": couldn't enable clock\n"); 162 return; 163 } 164 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 165 if (fdtbus_reset_deassert(rst) != 0) { 166 aprint_error(": couldn't de-assert reset\n"); 167 return; 168 } 169 170 sc->sc_dev = self; 171 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 172 sc->sc_bst = faa->faa_bst; 173 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 174 aprint_error(": couldn't map registers\n"); 175 return; 176 } 177 178 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 179 cv_init(&sc->sc_intr_wait, "sunxirsb"); 180 181 aprint_naive("\n"); 182 aprint_normal(": %s\n", sc->sc_type == SUNXI_P2WI ? "P2WI" : "RSB"); 183 184 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, 185 sunxi_rsb_intr, sc); 186 if (sc->sc_ih == NULL) { 187 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 188 intrstr); 189 return; 190 } 191 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 192 193 iic_tag_init(&sc->sc_ic); 194 sc->sc_ic.ic_cookie = sc; 195 sc->sc_ic.ic_exec = sunxi_rsb_exec; 196 197 fdtbus_register_i2c_controller(self, phandle, &sunxi_rsb_funcs); 198 199 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 200 } 201 202 static int 203 sunxi_rsb_intr(void *priv) 204 { 205 struct sunxi_rsb_softc *sc = priv; 206 uint32_t stat; 207 208 stat = RSB_READ(sc, RSB_STAT_REG); 209 if ((stat & RSB_STAT_MASK) == 0) 210 return 0; 211 212 RSB_WRITE(sc, RSB_STAT_REG, stat & RSB_STAT_MASK); 213 214 mutex_enter(&sc->sc_intr_lock); 215 sc->sc_stat |= stat; 216 cv_broadcast(&sc->sc_intr_wait); 217 mutex_exit(&sc->sc_intr_lock); 218 219 return 1; 220 } 221 222 static int 223 sunxi_rsb_soft_reset(struct sunxi_rsb_softc *sc) 224 { 225 int retry = 1000; 226 227 RSB_WRITE(sc, RSB_CTRL_REG, RSB_CTRL_SOFT_RESET); 228 while (--retry > 0) { 229 if ((RSB_READ(sc, RSB_CTRL_REG) & RSB_CTRL_SOFT_RESET) == 0) 230 break; 231 delay(10); 232 } 233 if (retry == 0) 234 return EIO; 235 236 return 0; 237 } 238 239 static int 240 sunxi_rsb_wait(struct sunxi_rsb_softc *sc, int flags) 241 { 242 int error = 0, retry; 243 244 /* Wait up to 5 seconds for a transfer to complete */ 245 sc->sc_stat = 0; 246 for (retry = (flags & I2C_F_POLL) ? 100 : 5; retry > 0; retry--) { 247 if (flags & I2C_F_POLL) { 248 sc->sc_stat |= RSB_READ(sc, RSB_STAT_REG); 249 } else { 250 error = cv_timedwait(&sc->sc_intr_wait, 251 &sc->sc_intr_lock, hz); 252 if (error && error != EWOULDBLOCK) { 253 break; 254 } 255 } 256 if (sc->sc_stat & RSB_STAT_MASK) { 257 break; 258 } 259 if (flags & I2C_F_POLL) { 260 delay(10000); 261 } 262 } 263 if (retry == 0) 264 error = EAGAIN; 265 266 if (flags & I2C_F_POLL) { 267 RSB_WRITE(sc, RSB_STAT_REG, 268 sc->sc_stat & RSB_STAT_MASK); 269 } 270 271 if (error) { 272 /* Abort transaction */ 273 device_printf(sc->sc_dev, "transfer timeout, error = %d\n", 274 error); 275 RSB_WRITE(sc, RSB_CTRL_REG, 276 RSB_CTRL_ABORT_TRANS); 277 return error; 278 } 279 280 if (sc->sc_stat & RSB_STAT_LOAD_BSY) { 281 device_printf(sc->sc_dev, "transfer busy\n"); 282 return EBUSY; 283 } 284 if (sc->sc_stat & RSB_STAT_TRANS_ERR) { 285 device_printf(sc->sc_dev, "transfer error, id 0x%02" PRIx64 286 "\n", __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID)); 287 return EIO; 288 } 289 290 return 0; 291 } 292 293 static int 294 sunxi_rsb_rsb_config(struct sunxi_rsb_softc *sc, uint8_t rta, i2c_addr_t da, 295 int flags) 296 { 297 uint32_t dar, ctrl; 298 299 KASSERT(mutex_owned(&sc->sc_intr_lock)); 300 301 RSB_WRITE(sc, RSB_STAT_REG, 302 RSB_READ(sc, RSB_STAT_REG) & RSB_STAT_MASK); 303 304 dar = __SHIFTIN(rta, RSB_DAR_RTA); 305 dar |= __SHIFTIN(da, RSB_DAR_DA); 306 RSB_WRITE(sc, RSB_DAR_REG, dar); 307 RSB_WRITE(sc, RSB_CMD_REG, RSB_CMD_IDX_SRTA); 308 309 /* Make sure the controller is idle */ 310 ctrl = RSB_READ(sc, RSB_CTRL_REG); 311 if (ctrl & RSB_CTRL_START_TRANS) { 312 device_printf(sc->sc_dev, "device is busy\n"); 313 return EBUSY; 314 } 315 316 /* Start the transfer */ 317 RSB_WRITE(sc, RSB_CTRL_REG, 318 ctrl | RSB_CTRL_START_TRANS); 319 320 return sunxi_rsb_wait(sc, flags); 321 } 322 323 static int 324 sunxi_rsb_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 325 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 326 { 327 struct sunxi_rsb_softc *sc = priv; 328 uint32_t dlen, ctrl; 329 uint8_t rta; 330 int error, i; 331 332 if (cmdlen != 1 || (len != 1 && len != 2 && len != 4)) 333 return EINVAL; 334 335 mutex_enter(&sc->sc_intr_lock); 336 337 error = sunxi_rsb_soft_reset(sc); 338 if (error != 0) { 339 mutex_exit(&sc->sc_intr_lock); 340 device_printf(sc->sc_dev, "soft reset timed out\n"); 341 return error; 342 } 343 344 if ((flags & I2C_F_POLL) == 0) { 345 /* Enable interrupts */ 346 RSB_WRITE(sc, RSB_INTE_REG, 347 RSB_INTE_LOAD_BSY_ENB | 348 RSB_INTE_TRANS_ERR_ENB | 349 RSB_INTE_TRANS_OVER_ENB); 350 RSB_WRITE(sc, RSB_CTRL_REG, 351 RSB_CTRL_GLOBAL_INT_ENB); 352 } 353 354 if (sc->sc_type == SUNXI_RSB && sc->sc_rsb_last_da != addr) { 355 /* Lookup run-time address for given device address */ 356 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 357 if (rsb_rtamap[i].addr == addr) { 358 rta = rsb_rtamap[i].rta; 359 break; 360 } 361 if (rta == 0) { 362 mutex_exit(&sc->sc_intr_lock); 363 device_printf(sc->sc_dev, 364 "RTA not known for address %#x\n", addr); 365 return ENXIO; 366 } 367 error = sunxi_rsb_rsb_config(sc, rta, addr, flags); 368 if (error) { 369 device_printf(sc->sc_dev, 370 "SRTA failed, flags = %x, error = %d\n", 371 flags, error); 372 sc->sc_rsb_last_da = 0; 373 goto done; 374 } 375 376 sc->sc_rsb_last_da = addr; 377 } 378 379 /* Data byte register */ 380 RSB_WRITE(sc, RSB_DADDR0_REG, *(const uint8_t *)cmdbuf); 381 382 if (I2C_OP_WRITE_P(op)) { 383 uint8_t *pbuf = buf; 384 uint32_t data; 385 /* Write data */ 386 switch (len) { 387 case 1: 388 data = pbuf[0]; 389 break; 390 case 2: 391 data = pbuf[0] | (pbuf[1] << 8); 392 break; 393 case 4: 394 data = pbuf[0] | (pbuf[1] << 8) | 395 (pbuf[2] << 16) | (pbuf[3] << 24); 396 break; 397 default: 398 error = EINVAL; 399 goto done; 400 } 401 RSB_WRITE(sc, RSB_DATA0_REG, data); 402 } 403 404 if (sc->sc_type == SUNXI_RSB) { 405 uint8_t cmd; 406 if (I2C_OP_WRITE_P(op)) { 407 switch (len) { 408 case 1: cmd = RSB_CMD_IDX_WR8; break; 409 case 2: cmd = RSB_CMD_IDX_WR16; break; 410 case 4: cmd = RSB_CMD_IDX_WR32; break; 411 default: error = EINVAL; goto done; 412 } 413 } else { 414 switch (len) { 415 case 1: cmd = RSB_CMD_IDX_RD8; break; 416 case 2: cmd = RSB_CMD_IDX_RD16; break; 417 case 4: cmd = RSB_CMD_IDX_RD32; break; 418 default: error = EINVAL; goto done; 419 } 420 } 421 RSB_WRITE(sc, RSB_CMD_REG, cmd); 422 } 423 424 /* Program data length register; if reading, set read/write bit */ 425 dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH); 426 if (I2C_OP_READ_P(op)) { 427 dlen |= RSB_DLEN_READ_WRITE_FLAG; 428 } 429 RSB_WRITE(sc, RSB_DLEN_REG, dlen); 430 431 /* Make sure the controller is idle */ 432 ctrl = RSB_READ(sc, RSB_CTRL_REG); 433 if (ctrl & RSB_CTRL_START_TRANS) { 434 device_printf(sc->sc_dev, "device is busy\n"); 435 error = EBUSY; 436 goto done; 437 } 438 439 /* Start the transfer */ 440 RSB_WRITE(sc, RSB_CTRL_REG, 441 ctrl | RSB_CTRL_START_TRANS); 442 443 error = sunxi_rsb_wait(sc, flags); 444 if (error) 445 goto done; 446 447 if (I2C_OP_READ_P(op)) { 448 uint32_t data = RSB_READ(sc, RSB_DATA0_REG); 449 switch (len) { 450 case 4: 451 *(uint32_t *)buf = data; 452 break; 453 case 2: 454 *(uint16_t *)buf = data & 0xffff; 455 break; 456 case 1: 457 *(uint8_t *)buf = data & 0xff; 458 break; 459 default: 460 error = EINVAL; 461 goto done; 462 } 463 } 464 465 error = 0; 466 467 done: 468 RSB_WRITE(sc, RSB_CTRL_REG, 0); 469 mutex_exit(&sc->sc_intr_lock); 470 471 return error; 472 } 473