1 /* $NetBSD: sunxi_rsb.c,v 1.1 2017/07/02 18:06:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rsb.c,v 1.1 2017/07/02 18:06:45 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <arm/sunxi/sunxi_rsb.h> 46 47 enum sunxi_rsb_type { 48 SUNXI_P2WI, 49 SUNXI_RSB, 50 }; 51 52 static const struct of_compat_data compat_data[] = { 53 { "allwinner,sun6i-a31-p2wi", SUNXI_P2WI }, 54 { "allwinner,sun8i-a23-rsb", SUNXI_RSB }, 55 { NULL } 56 }; 57 58 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 59 #define RSB_ADDR_PMIC_SECONDARY 0x745 60 #define RSB_ADDR_PERIPH_IC 0xe89 61 62 /* 63 * Device address to Run-time address mappings. 64 * 65 * Run-time address (RTA) is an 8-bit value used to address the device during 66 * a read or write transaction. The following are valid RTAs: 67 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 68 * 69 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 70 * and 0x4e for the peripheral IC (where applicable). 71 */ 72 static const struct { 73 uint16_t addr; 74 uint8_t rta; 75 } rsb_rtamap[] = { 76 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 77 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 78 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 79 { .addr = 0, .rta = 0 } 80 }; 81 82 struct sunxi_rsb_softc { 83 device_t sc_dev; 84 bus_space_tag_t sc_bst; 85 bus_space_handle_t sc_bsh; 86 enum sunxi_rsb_type sc_type; 87 struct i2c_controller sc_ic; 88 kmutex_t sc_lock; 89 kcondvar_t sc_cv; 90 device_t sc_i2cdev; 91 void *sc_ih; 92 uint32_t sc_stat; 93 94 uint16_t sc_rsb_last_da; 95 }; 96 97 #define RSB_READ(sc, reg) \ 98 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 99 #define RSB_WRITE(sc, reg, val) \ 100 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 101 102 static int sunxi_rsb_acquire_bus(void *, int); 103 static void sunxi_rsb_release_bus(void *, int); 104 static int sunxi_rsb_exec(void *, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 static int sunxi_rsb_intr(void *); 108 static int sunxi_rsb_wait(struct sunxi_rsb_softc *, int); 109 static int sunxi_rsb_rsb_config(struct sunxi_rsb_softc *, 110 uint8_t, i2c_addr_t, int); 111 112 static int sunxi_rsb_match(device_t, cfdata_t, void *); 113 static void sunxi_rsb_attach(device_t, device_t, void *); 114 115 static i2c_tag_t 116 sunxi_rsb_get_tag(device_t dev) 117 { 118 struct sunxi_rsb_softc * const sc = device_private(dev); 119 120 return &sc->sc_ic; 121 } 122 123 static const struct fdtbus_i2c_controller_func sunxi_rsb_funcs = { 124 .get_tag = sunxi_rsb_get_tag, 125 }; 126 127 CFATTACH_DECL_NEW(sunxi_rsb, sizeof(struct sunxi_rsb_softc), 128 sunxi_rsb_match, sunxi_rsb_attach, NULL, NULL); 129 130 static int 131 sunxi_rsb_match(device_t parent, cfdata_t cf, void *aux) 132 { 133 struct fdt_attach_args * const faa = aux; 134 135 return of_match_compat_data(faa->faa_phandle, compat_data); 136 } 137 138 static void 139 sunxi_rsb_attach(device_t parent, device_t self, void *aux) 140 { 141 struct sunxi_rsb_softc * const sc = device_private(self); 142 struct fdt_attach_args * const faa = aux; 143 const int phandle = faa->faa_phandle; 144 struct i2cbus_attach_args iba; 145 prop_dictionary_t devs; 146 uint32_t address_cells; 147 struct fdtbus_reset *rst; 148 struct clk *clk; 149 char intrstr[128]; 150 bus_addr_t addr; 151 bus_size_t size; 152 153 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 154 aprint_error(": couldn't get registers\n"); 155 return; 156 } 157 158 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 159 aprint_error(": couldn't decode interrupt\n"); 160 return; 161 } 162 163 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 164 if (clk_enable(clk) != 0) { 165 aprint_error(": couldn't enable clock\n"); 166 return; 167 } 168 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 169 if (fdtbus_reset_deassert(rst) != 0) { 170 aprint_error(": couldn't de-assert reset\n"); 171 return; 172 } 173 174 sc->sc_dev = self; 175 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 176 sc->sc_bst = faa->faa_bst; 177 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 178 aprint_error(": couldn't map registers\n"); 179 return; 180 } 181 182 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 183 cv_init(&sc->sc_cv, "awinp2wi"); 184 185 aprint_naive("\n"); 186 aprint_normal(": %s\n", sc->sc_type == SUNXI_P2WI ? "P2WI" : "RSB"); 187 188 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, 189 sunxi_rsb_intr, sc); 190 if (sc->sc_ih == NULL) { 191 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 192 intrstr); 193 return; 194 } 195 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 196 197 /* Enable interrupts */ 198 RSB_WRITE(sc, RSB_INTE_REG, 199 RSB_INTE_LOAD_BSY_ENB | 200 RSB_INTE_TRANS_ERR_ENB | 201 RSB_INTE_TRANS_OVER_ENB); 202 RSB_WRITE(sc, RSB_CTRL_REG, 203 RSB_CTRL_GLOBAL_INT_ENB); 204 205 sc->sc_ic.ic_cookie = sc; 206 sc->sc_ic.ic_acquire_bus = sunxi_rsb_acquire_bus; 207 sc->sc_ic.ic_release_bus = sunxi_rsb_release_bus; 208 sc->sc_ic.ic_exec = sunxi_rsb_exec; 209 210 fdtbus_register_i2c_controller(self, phandle, &sunxi_rsb_funcs); 211 212 devs = prop_dictionary_create(); 213 if (of_getprop_uint32(phandle, "#address-cells", &address_cells)) 214 address_cells = 1; 215 216 of_enter_i2c_devs(devs, phandle, address_cells * 4, 0); 217 218 memset(&iba, 0, sizeof(iba)); 219 iba.iba_tag = &sc->sc_ic; 220 iba.iba_child_devices = prop_dictionary_get(devs, "i2c-child-devices"); 221 if (iba.iba_child_devices) 222 prop_object_retain(iba.iba_child_devices); 223 else 224 iba.iba_child_devices = prop_array_create(); 225 prop_object_release(devs); 226 227 sc->sc_i2cdev = config_found_ia(self, "i2cbus", &iba, iicbus_print); 228 } 229 230 static int 231 sunxi_rsb_intr(void *priv) 232 { 233 struct sunxi_rsb_softc *sc = priv; 234 uint32_t stat; 235 236 stat = RSB_READ(sc, RSB_STAT_REG); 237 if ((stat & RSB_STAT_MASK) == 0) 238 return 0; 239 240 RSB_WRITE(sc, RSB_STAT_REG, stat & RSB_STAT_MASK); 241 242 mutex_enter(&sc->sc_lock); 243 sc->sc_stat |= stat; 244 cv_broadcast(&sc->sc_cv); 245 mutex_exit(&sc->sc_lock); 246 247 return 1; 248 } 249 250 static int 251 sunxi_rsb_wait(struct sunxi_rsb_softc *sc, int flags) 252 { 253 int error = 0, retry; 254 255 /* Wait up to 5 seconds for a transfer to complete */ 256 sc->sc_stat = 0; 257 for (retry = (flags & I2C_F_POLL) ? 100 : 5; retry > 0; retry--) { 258 if (flags & I2C_F_POLL) { 259 sc->sc_stat |= RSB_READ(sc, RSB_STAT_REG); 260 } else { 261 error = cv_timedwait(&sc->sc_cv, &sc->sc_lock, hz); 262 if (error && error != EWOULDBLOCK) { 263 break; 264 } 265 } 266 if (sc->sc_stat & RSB_STAT_MASK) { 267 break; 268 } 269 if (flags & I2C_F_POLL) { 270 delay(10000); 271 } 272 } 273 if (retry == 0) 274 error = EAGAIN; 275 276 if (flags & I2C_F_POLL) { 277 RSB_WRITE(sc, RSB_STAT_REG, 278 sc->sc_stat & RSB_STAT_MASK); 279 } 280 281 if (error) { 282 /* Abort transaction */ 283 device_printf(sc->sc_dev, "transfer timeout, error = %d\n", 284 error); 285 RSB_WRITE(sc, RSB_CTRL_REG, 286 RSB_CTRL_ABORT_TRANS); 287 return error; 288 } 289 290 if (sc->sc_stat & RSB_STAT_LOAD_BSY) { 291 device_printf(sc->sc_dev, "transfer busy\n"); 292 return EBUSY; 293 } 294 if (sc->sc_stat & RSB_STAT_TRANS_ERR) { 295 device_printf(sc->sc_dev, "transfer error, id 0x%02llx\n", 296 __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID)); 297 return EIO; 298 } 299 300 return 0; 301 } 302 303 static int 304 sunxi_rsb_rsb_config(struct sunxi_rsb_softc *sc, uint8_t rta, i2c_addr_t da, 305 int flags) 306 { 307 uint32_t dar, ctrl; 308 309 KASSERT(mutex_owned(&sc->sc_lock)); 310 311 RSB_WRITE(sc, RSB_STAT_REG, 312 RSB_READ(sc, RSB_STAT_REG) & RSB_STAT_MASK); 313 314 dar = __SHIFTIN(rta, RSB_DAR_RTA); 315 dar |= __SHIFTIN(da, RSB_DAR_DA); 316 RSB_WRITE(sc, RSB_DAR_REG, dar); 317 RSB_WRITE(sc, RSB_CMD_REG, RSB_CMD_IDX_SRTA); 318 319 /* Make sure the controller is idle */ 320 ctrl = RSB_READ(sc, RSB_CTRL_REG); 321 if (ctrl & RSB_CTRL_START_TRANS) { 322 device_printf(sc->sc_dev, "device is busy\n"); 323 return EBUSY; 324 } 325 326 /* Start the transfer */ 327 RSB_WRITE(sc, RSB_CTRL_REG, 328 ctrl | RSB_CTRL_START_TRANS); 329 330 return sunxi_rsb_wait(sc, flags); 331 } 332 333 static int 334 sunxi_rsb_acquire_bus(void *priv, int flags) 335 { 336 struct sunxi_rsb_softc *sc = priv; 337 338 if (flags & I2C_F_POLL) { 339 if (!mutex_tryenter(&sc->sc_lock)) 340 return EBUSY; 341 } else { 342 mutex_enter(&sc->sc_lock); 343 } 344 345 return 0; 346 } 347 348 static void 349 sunxi_rsb_release_bus(void *priv, int flags) 350 { 351 struct sunxi_rsb_softc *sc = priv; 352 353 mutex_exit(&sc->sc_lock); 354 } 355 356 static int 357 sunxi_rsb_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 358 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 359 { 360 struct sunxi_rsb_softc *sc = priv; 361 uint32_t dlen, ctrl; 362 uint8_t rta; 363 int error, i; 364 365 KASSERT(mutex_owned(&sc->sc_lock)); 366 367 if (cmdlen != 1 || (len != 1 && len != 2 && len != 4)) 368 return EINVAL; 369 370 if (sc->sc_type == SUNXI_RSB && sc->sc_rsb_last_da != addr) { 371 /* Lookup run-time address for given device address */ 372 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 373 if (rsb_rtamap[i].addr == addr) { 374 rta = rsb_rtamap[i].rta; 375 break; 376 } 377 if (rta == 0) { 378 device_printf(sc->sc_dev, 379 "RTA not known for address %#x\n", addr); 380 return ENXIO; 381 } 382 error = sunxi_rsb_rsb_config(sc, rta, addr, flags); 383 if (error) { 384 device_printf(sc->sc_dev, 385 "SRTA failed, flags = %x, error = %d\n", 386 flags, error); 387 sc->sc_rsb_last_da = 0; 388 return error; 389 } 390 391 sc->sc_rsb_last_da = addr; 392 } 393 394 /* Data byte register */ 395 RSB_WRITE(sc, RSB_DADDR0_REG, *(const uint8_t *)cmdbuf); 396 397 if (I2C_OP_WRITE_P(op)) { 398 uint8_t *pbuf = buf; 399 uint32_t data; 400 /* Write data */ 401 switch (len) { 402 case 1: 403 data = pbuf[0]; 404 break; 405 case 2: 406 data = pbuf[0] | (pbuf[1] << 8); 407 break; 408 case 4: 409 data = pbuf[0] | (pbuf[1] << 8) | 410 (pbuf[2] << 16) | (pbuf[3] << 24); 411 break; 412 default: 413 return EINVAL; 414 } 415 RSB_WRITE(sc, RSB_DATA0_REG, data); 416 } 417 418 if (sc->sc_type == SUNXI_RSB) { 419 uint8_t cmd; 420 if (I2C_OP_WRITE_P(op)) { 421 switch (len) { 422 case 1: cmd = RSB_CMD_IDX_WR8; break; 423 case 2: cmd = RSB_CMD_IDX_WR16; break; 424 case 4: cmd = RSB_CMD_IDX_WR32; break; 425 default: return EINVAL; 426 } 427 } else { 428 switch (len) { 429 case 1: cmd = RSB_CMD_IDX_RD8; break; 430 case 2: cmd = RSB_CMD_IDX_RD16; break; 431 case 4: cmd = RSB_CMD_IDX_RD32; break; 432 default: return EINVAL; 433 } 434 } 435 RSB_WRITE(sc, RSB_CMD_REG, cmd); 436 } 437 438 /* Program data length register; if reading, set read/write bit */ 439 dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH); 440 if (I2C_OP_READ_P(op)) { 441 dlen |= RSB_DLEN_READ_WRITE_FLAG; 442 } 443 RSB_WRITE(sc, RSB_DLEN_REG, dlen); 444 445 /* Make sure the controller is idle */ 446 ctrl = RSB_READ(sc, RSB_CTRL_REG); 447 if (ctrl & RSB_CTRL_START_TRANS) { 448 device_printf(sc->sc_dev, "device is busy\n"); 449 return EBUSY; 450 } 451 452 /* Start the transfer */ 453 RSB_WRITE(sc, RSB_CTRL_REG, 454 ctrl | RSB_CTRL_START_TRANS); 455 456 error = sunxi_rsb_wait(sc, flags); 457 if (error) { 458 return error; 459 } 460 461 if (I2C_OP_READ_P(op)) { 462 uint32_t data = RSB_READ(sc, RSB_DATA0_REG); 463 switch (len) { 464 case 4: 465 *(uint32_t *)buf = data; 466 break; 467 case 2: 468 *(uint16_t *)buf = data & 0xffff; 469 break; 470 case 1: 471 *(uint8_t *)buf = data & 0xff; 472 break; 473 default: 474 return EINVAL; 475 } 476 } 477 478 return 0; 479 } 480