1 /* $NetBSD: sunxi_rsb.c,v 1.5 2018/07/16 23:11:47 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rsb.c,v 1.5 2018/07/16 23:11:47 christos Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <arm/sunxi/sunxi_rsb.h> 46 47 enum sunxi_rsb_type { 48 SUNXI_P2WI, 49 SUNXI_RSB, 50 }; 51 52 static const struct of_compat_data compat_data[] = { 53 { "allwinner,sun6i-a31-p2wi", SUNXI_P2WI }, 54 { "allwinner,sun8i-a23-rsb", SUNXI_RSB }, 55 { NULL } 56 }; 57 58 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 59 #define RSB_ADDR_PMIC_SECONDARY 0x745 60 #define RSB_ADDR_PERIPH_IC 0xe89 61 62 /* 63 * Device address to Run-time address mappings. 64 * 65 * Run-time address (RTA) is an 8-bit value used to address the device during 66 * a read or write transaction. The following are valid RTAs: 67 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 68 * 69 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 70 * and 0x4e for the peripheral IC (where applicable). 71 */ 72 static const struct { 73 uint16_t addr; 74 uint8_t rta; 75 } rsb_rtamap[] = { 76 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 77 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 78 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 79 { .addr = 0, .rta = 0 } 80 }; 81 82 struct sunxi_rsb_softc { 83 device_t sc_dev; 84 bus_space_tag_t sc_bst; 85 bus_space_handle_t sc_bsh; 86 enum sunxi_rsb_type sc_type; 87 struct i2c_controller sc_ic; 88 kmutex_t sc_lock; 89 kcondvar_t sc_cv; 90 device_t sc_i2cdev; 91 void *sc_ih; 92 uint32_t sc_stat; 93 94 uint16_t sc_rsb_last_da; 95 }; 96 97 #define RSB_READ(sc, reg) \ 98 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 99 #define RSB_WRITE(sc, reg, val) \ 100 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 101 102 static int sunxi_rsb_acquire_bus(void *, int); 103 static void sunxi_rsb_release_bus(void *, int); 104 static int sunxi_rsb_exec(void *, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 static int sunxi_rsb_intr(void *); 108 static int sunxi_rsb_wait(struct sunxi_rsb_softc *, int); 109 static int sunxi_rsb_rsb_config(struct sunxi_rsb_softc *, 110 uint8_t, i2c_addr_t, int); 111 112 static int sunxi_rsb_match(device_t, cfdata_t, void *); 113 static void sunxi_rsb_attach(device_t, device_t, void *); 114 115 static i2c_tag_t 116 sunxi_rsb_get_tag(device_t dev) 117 { 118 struct sunxi_rsb_softc * const sc = device_private(dev); 119 120 return &sc->sc_ic; 121 } 122 123 static const struct fdtbus_i2c_controller_func sunxi_rsb_funcs = { 124 .get_tag = sunxi_rsb_get_tag, 125 }; 126 127 CFATTACH_DECL_NEW(sunxi_rsb, sizeof(struct sunxi_rsb_softc), 128 sunxi_rsb_match, sunxi_rsb_attach, NULL, NULL); 129 130 static int 131 sunxi_rsb_match(device_t parent, cfdata_t cf, void *aux) 132 { 133 struct fdt_attach_args * const faa = aux; 134 135 return of_match_compat_data(faa->faa_phandle, compat_data); 136 } 137 138 static void 139 sunxi_rsb_attach(device_t parent, device_t self, void *aux) 140 { 141 struct sunxi_rsb_softc * const sc = device_private(self); 142 struct fdt_attach_args * const faa = aux; 143 const int phandle = faa->faa_phandle; 144 struct fdtbus_reset *rst; 145 struct clk *clk; 146 char intrstr[128]; 147 bus_addr_t addr; 148 bus_size_t size; 149 150 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 151 aprint_error(": couldn't get registers\n"); 152 return; 153 } 154 155 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 156 aprint_error(": couldn't decode interrupt\n"); 157 return; 158 } 159 160 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 161 if (clk_enable(clk) != 0) { 162 aprint_error(": couldn't enable clock\n"); 163 return; 164 } 165 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 166 if (fdtbus_reset_deassert(rst) != 0) { 167 aprint_error(": couldn't de-assert reset\n"); 168 return; 169 } 170 171 sc->sc_dev = self; 172 sc->sc_type = of_search_compatible(phandle, compat_data)->data; 173 sc->sc_bst = faa->faa_bst; 174 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 175 aprint_error(": couldn't map registers\n"); 176 return; 177 } 178 179 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 180 cv_init(&sc->sc_cv, "awinp2wi"); 181 182 aprint_naive("\n"); 183 aprint_normal(": %s\n", sc->sc_type == SUNXI_P2WI ? "P2WI" : "RSB"); 184 185 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, 186 sunxi_rsb_intr, sc); 187 if (sc->sc_ih == NULL) { 188 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 189 intrstr); 190 return; 191 } 192 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 193 194 sc->sc_ic.ic_cookie = sc; 195 sc->sc_ic.ic_acquire_bus = sunxi_rsb_acquire_bus; 196 sc->sc_ic.ic_release_bus = sunxi_rsb_release_bus; 197 sc->sc_ic.ic_exec = sunxi_rsb_exec; 198 199 fdtbus_register_i2c_controller(self, phandle, &sunxi_rsb_funcs); 200 201 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 202 } 203 204 static int 205 sunxi_rsb_intr(void *priv) 206 { 207 struct sunxi_rsb_softc *sc = priv; 208 uint32_t stat; 209 210 stat = RSB_READ(sc, RSB_STAT_REG); 211 if ((stat & RSB_STAT_MASK) == 0) 212 return 0; 213 214 RSB_WRITE(sc, RSB_STAT_REG, stat & RSB_STAT_MASK); 215 216 mutex_enter(&sc->sc_lock); 217 sc->sc_stat |= stat; 218 cv_broadcast(&sc->sc_cv); 219 mutex_exit(&sc->sc_lock); 220 221 return 1; 222 } 223 224 static int 225 sunxi_rsb_soft_reset(struct sunxi_rsb_softc *sc) 226 { 227 int retry = 1000; 228 229 RSB_WRITE(sc, RSB_CTRL_REG, RSB_CTRL_SOFT_RESET); 230 while (--retry > 0) { 231 if ((RSB_READ(sc, RSB_CTRL_REG) & RSB_CTRL_SOFT_RESET) == 0) 232 break; 233 delay(10); 234 } 235 if (retry == 0) 236 return EIO; 237 238 return 0; 239 } 240 241 static int 242 sunxi_rsb_wait(struct sunxi_rsb_softc *sc, int flags) 243 { 244 int error = 0, retry; 245 246 /* Wait up to 5 seconds for a transfer to complete */ 247 sc->sc_stat = 0; 248 for (retry = (flags & I2C_F_POLL) ? 100 : 5; retry > 0; retry--) { 249 if (flags & I2C_F_POLL) { 250 sc->sc_stat |= RSB_READ(sc, RSB_STAT_REG); 251 } else { 252 error = cv_timedwait(&sc->sc_cv, &sc->sc_lock, hz); 253 if (error && error != EWOULDBLOCK) { 254 break; 255 } 256 } 257 if (sc->sc_stat & RSB_STAT_MASK) { 258 break; 259 } 260 if (flags & I2C_F_POLL) { 261 delay(10000); 262 } 263 } 264 if (retry == 0) 265 error = EAGAIN; 266 267 if (flags & I2C_F_POLL) { 268 RSB_WRITE(sc, RSB_STAT_REG, 269 sc->sc_stat & RSB_STAT_MASK); 270 } 271 272 if (error) { 273 /* Abort transaction */ 274 device_printf(sc->sc_dev, "transfer timeout, error = %d\n", 275 error); 276 RSB_WRITE(sc, RSB_CTRL_REG, 277 RSB_CTRL_ABORT_TRANS); 278 return error; 279 } 280 281 if (sc->sc_stat & RSB_STAT_LOAD_BSY) { 282 device_printf(sc->sc_dev, "transfer busy\n"); 283 return EBUSY; 284 } 285 if (sc->sc_stat & RSB_STAT_TRANS_ERR) { 286 device_printf(sc->sc_dev, "transfer error, id 0x%02" PRIx64 287 "\n", __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID)); 288 return EIO; 289 } 290 291 return 0; 292 } 293 294 static int 295 sunxi_rsb_rsb_config(struct sunxi_rsb_softc *sc, uint8_t rta, i2c_addr_t da, 296 int flags) 297 { 298 uint32_t dar, ctrl; 299 300 KASSERT(mutex_owned(&sc->sc_lock)); 301 302 RSB_WRITE(sc, RSB_STAT_REG, 303 RSB_READ(sc, RSB_STAT_REG) & RSB_STAT_MASK); 304 305 dar = __SHIFTIN(rta, RSB_DAR_RTA); 306 dar |= __SHIFTIN(da, RSB_DAR_DA); 307 RSB_WRITE(sc, RSB_DAR_REG, dar); 308 RSB_WRITE(sc, RSB_CMD_REG, RSB_CMD_IDX_SRTA); 309 310 /* Make sure the controller is idle */ 311 ctrl = RSB_READ(sc, RSB_CTRL_REG); 312 if (ctrl & RSB_CTRL_START_TRANS) { 313 device_printf(sc->sc_dev, "device is busy\n"); 314 return EBUSY; 315 } 316 317 /* Start the transfer */ 318 RSB_WRITE(sc, RSB_CTRL_REG, 319 ctrl | RSB_CTRL_START_TRANS); 320 321 return sunxi_rsb_wait(sc, flags); 322 } 323 324 static int 325 sunxi_rsb_acquire_bus(void *priv, int flags) 326 { 327 struct sunxi_rsb_softc *sc = priv; 328 329 mutex_enter(&sc->sc_lock); 330 331 return 0; 332 } 333 334 static void 335 sunxi_rsb_release_bus(void *priv, int flags) 336 { 337 struct sunxi_rsb_softc *sc = priv; 338 339 mutex_exit(&sc->sc_lock); 340 } 341 342 static int 343 sunxi_rsb_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 344 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 345 { 346 struct sunxi_rsb_softc *sc = priv; 347 uint32_t dlen, ctrl; 348 uint8_t rta; 349 int error, i; 350 351 KASSERT(mutex_owned(&sc->sc_lock)); 352 353 if (cmdlen != 1 || (len != 1 && len != 2 && len != 4)) 354 return EINVAL; 355 356 error = sunxi_rsb_soft_reset(sc); 357 if (error != 0) { 358 device_printf(sc->sc_dev, "soft reset timed out\n"); 359 return error; 360 } 361 362 if ((flags & I2C_F_POLL) == 0) { 363 /* Enable interrupts */ 364 RSB_WRITE(sc, RSB_INTE_REG, 365 RSB_INTE_LOAD_BSY_ENB | 366 RSB_INTE_TRANS_ERR_ENB | 367 RSB_INTE_TRANS_OVER_ENB); 368 RSB_WRITE(sc, RSB_CTRL_REG, 369 RSB_CTRL_GLOBAL_INT_ENB); 370 } 371 372 if (sc->sc_type == SUNXI_RSB && sc->sc_rsb_last_da != addr) { 373 /* Lookup run-time address for given device address */ 374 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 375 if (rsb_rtamap[i].addr == addr) { 376 rta = rsb_rtamap[i].rta; 377 break; 378 } 379 if (rta == 0) { 380 device_printf(sc->sc_dev, 381 "RTA not known for address %#x\n", addr); 382 return ENXIO; 383 } 384 error = sunxi_rsb_rsb_config(sc, rta, addr, flags); 385 if (error) { 386 device_printf(sc->sc_dev, 387 "SRTA failed, flags = %x, error = %d\n", 388 flags, error); 389 sc->sc_rsb_last_da = 0; 390 goto done; 391 } 392 393 sc->sc_rsb_last_da = addr; 394 } 395 396 /* Data byte register */ 397 RSB_WRITE(sc, RSB_DADDR0_REG, *(const uint8_t *)cmdbuf); 398 399 if (I2C_OP_WRITE_P(op)) { 400 uint8_t *pbuf = buf; 401 uint32_t data; 402 /* Write data */ 403 switch (len) { 404 case 1: 405 data = pbuf[0]; 406 break; 407 case 2: 408 data = pbuf[0] | (pbuf[1] << 8); 409 break; 410 case 4: 411 data = pbuf[0] | (pbuf[1] << 8) | 412 (pbuf[2] << 16) | (pbuf[3] << 24); 413 break; 414 default: 415 error = EINVAL; 416 goto done; 417 } 418 RSB_WRITE(sc, RSB_DATA0_REG, data); 419 } 420 421 if (sc->sc_type == SUNXI_RSB) { 422 uint8_t cmd; 423 if (I2C_OP_WRITE_P(op)) { 424 switch (len) { 425 case 1: cmd = RSB_CMD_IDX_WR8; break; 426 case 2: cmd = RSB_CMD_IDX_WR16; break; 427 case 4: cmd = RSB_CMD_IDX_WR32; break; 428 default: error = EINVAL; goto done; 429 } 430 } else { 431 switch (len) { 432 case 1: cmd = RSB_CMD_IDX_RD8; break; 433 case 2: cmd = RSB_CMD_IDX_RD16; break; 434 case 4: cmd = RSB_CMD_IDX_RD32; break; 435 default: error = EINVAL; goto done; 436 } 437 } 438 RSB_WRITE(sc, RSB_CMD_REG, cmd); 439 } 440 441 /* Program data length register; if reading, set read/write bit */ 442 dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH); 443 if (I2C_OP_READ_P(op)) { 444 dlen |= RSB_DLEN_READ_WRITE_FLAG; 445 } 446 RSB_WRITE(sc, RSB_DLEN_REG, dlen); 447 448 /* Make sure the controller is idle */ 449 ctrl = RSB_READ(sc, RSB_CTRL_REG); 450 if (ctrl & RSB_CTRL_START_TRANS) { 451 device_printf(sc->sc_dev, "device is busy\n"); 452 error = EBUSY; 453 goto done; 454 } 455 456 /* Start the transfer */ 457 RSB_WRITE(sc, RSB_CTRL_REG, 458 ctrl | RSB_CTRL_START_TRANS); 459 460 error = sunxi_rsb_wait(sc, flags); 461 if (error) 462 goto done; 463 464 if (I2C_OP_READ_P(op)) { 465 uint32_t data = RSB_READ(sc, RSB_DATA0_REG); 466 switch (len) { 467 case 4: 468 *(uint32_t *)buf = data; 469 break; 470 case 2: 471 *(uint16_t *)buf = data & 0xffff; 472 break; 473 case 1: 474 *(uint8_t *)buf = data & 0xff; 475 break; 476 default: 477 error = EINVAL; 478 goto done; 479 } 480 } 481 482 error = 0; 483 484 done: 485 RSB_WRITE(sc, RSB_CTRL_REG, 0); 486 487 return error; 488 } 489