1 /* $NetBSD: sunxi_rsb.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rsb.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <arm/sunxi/sunxi_rsb.h> 46 47 enum sunxi_rsb_type { 48 SUNXI_P2WI, 49 SUNXI_RSB, 50 }; 51 52 static const struct device_compatible_entry compat_data[] = { 53 { .compat = "allwinner,sun6i-a31-p2wi", .value = SUNXI_P2WI }, 54 { .compat = "allwinner,sun8i-a23-rsb", .value = SUNXI_RSB }, 55 DEVICE_COMPAT_EOL 56 }; 57 58 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 59 #define RSB_ADDR_PMIC_SECONDARY 0x745 60 #define RSB_ADDR_PERIPH_IC 0xe89 61 62 /* 63 * Device address to Run-time address mappings. 64 * 65 * Run-time address (RTA) is an 8-bit value used to address the device during 66 * a read or write transaction. The following are valid RTAs: 67 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 68 * 69 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 70 * and 0x4e for the peripheral IC (where applicable). 71 */ 72 static const struct { 73 uint16_t addr; 74 uint8_t rta; 75 } rsb_rtamap[] = { 76 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 77 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 78 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 79 { .addr = 0, .rta = 0 } 80 }; 81 82 struct sunxi_rsb_softc { 83 device_t sc_dev; 84 bus_space_tag_t sc_bst; 85 bus_space_handle_t sc_bsh; 86 enum sunxi_rsb_type sc_type; 87 struct i2c_controller sc_ic; 88 kmutex_t sc_intr_lock; 89 kcondvar_t sc_intr_wait; 90 device_t sc_i2cdev; 91 void *sc_ih; 92 uint32_t sc_stat; 93 bool sc_busy; 94 95 uint16_t sc_rsb_last_da; 96 }; 97 98 #define RSB_READ(sc, reg) \ 99 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 100 #define RSB_WRITE(sc, reg, val) \ 101 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 102 103 static int sunxi_rsb_exec(void *, i2c_op_t, i2c_addr_t, const void *, 104 size_t, void *, size_t, int); 105 106 static int sunxi_rsb_intr(void *); 107 static int sunxi_rsb_wait(struct sunxi_rsb_softc *, int); 108 static int sunxi_rsb_rsb_config(struct sunxi_rsb_softc *, 109 uint8_t, i2c_addr_t, int); 110 111 static int sunxi_rsb_match(device_t, cfdata_t, void *); 112 static void sunxi_rsb_attach(device_t, device_t, void *); 113 114 CFATTACH_DECL_NEW(sunxi_rsb, sizeof(struct sunxi_rsb_softc), 115 sunxi_rsb_match, sunxi_rsb_attach, NULL, NULL); 116 117 static int 118 sunxi_rsb_match(device_t parent, cfdata_t cf, void *aux) 119 { 120 struct fdt_attach_args * const faa = aux; 121 122 return of_compatible_match(faa->faa_phandle, compat_data); 123 } 124 125 static void 126 sunxi_rsb_attach(device_t parent, device_t self, void *aux) 127 { 128 struct sunxi_rsb_softc * const sc = device_private(self); 129 struct fdt_attach_args * const faa = aux; 130 const int phandle = faa->faa_phandle; 131 struct fdtbus_reset *rst; 132 struct clk *clk; 133 char intrstr[128]; 134 bus_addr_t addr; 135 bus_size_t size; 136 137 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 138 aprint_error(": couldn't get registers\n"); 139 return; 140 } 141 142 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 143 aprint_error(": couldn't decode interrupt\n"); 144 return; 145 } 146 147 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 148 if (clk_enable(clk) != 0) { 149 aprint_error(": couldn't enable clock\n"); 150 return; 151 } 152 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 153 if (fdtbus_reset_deassert(rst) != 0) { 154 aprint_error(": couldn't de-assert reset\n"); 155 return; 156 } 157 158 sc->sc_dev = self; 159 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 160 sc->sc_bst = faa->faa_bst; 161 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 162 aprint_error(": couldn't map registers\n"); 163 return; 164 } 165 166 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 167 cv_init(&sc->sc_intr_wait, "sunxirsb"); 168 169 aprint_naive("\n"); 170 aprint_normal(": %s\n", sc->sc_type == SUNXI_P2WI ? "P2WI" : "RSB"); 171 172 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0, 173 sunxi_rsb_intr, sc, device_xname(self)); 174 if (sc->sc_ih == NULL) { 175 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 176 intrstr); 177 return; 178 } 179 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 180 181 iic_tag_init(&sc->sc_ic); 182 sc->sc_ic.ic_cookie = sc; 183 sc->sc_ic.ic_exec = sunxi_rsb_exec; 184 185 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 186 187 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 188 } 189 190 static int 191 sunxi_rsb_intr(void *priv) 192 { 193 struct sunxi_rsb_softc *sc = priv; 194 uint32_t stat; 195 196 stat = RSB_READ(sc, RSB_STAT_REG); 197 if ((stat & RSB_STAT_MASK) == 0) 198 return 0; 199 200 RSB_WRITE(sc, RSB_STAT_REG, stat & RSB_STAT_MASK); 201 202 mutex_enter(&sc->sc_intr_lock); 203 sc->sc_stat |= stat; 204 cv_broadcast(&sc->sc_intr_wait); 205 mutex_exit(&sc->sc_intr_lock); 206 207 return 1; 208 } 209 210 static int 211 sunxi_rsb_soft_reset(struct sunxi_rsb_softc *sc) 212 { 213 int retry = 1000; 214 215 RSB_WRITE(sc, RSB_CTRL_REG, RSB_CTRL_SOFT_RESET); 216 while (--retry > 0) { 217 if ((RSB_READ(sc, RSB_CTRL_REG) & RSB_CTRL_SOFT_RESET) == 0) 218 break; 219 delay(10); 220 } 221 if (retry == 0) 222 return EIO; 223 224 return 0; 225 } 226 227 static int 228 sunxi_rsb_wait(struct sunxi_rsb_softc *sc, int flags) 229 { 230 int error = 0, retry; 231 232 /* Wait up to 5 seconds for a transfer to complete */ 233 sc->sc_stat = 0; 234 for (retry = (flags & I2C_F_POLL) ? 100 : 5; retry > 0; retry--) { 235 if (flags & I2C_F_POLL) { 236 sc->sc_stat |= RSB_READ(sc, RSB_STAT_REG); 237 } else { 238 error = cv_timedwait(&sc->sc_intr_wait, 239 &sc->sc_intr_lock, hz); 240 if (error && error != EWOULDBLOCK) { 241 break; 242 } 243 } 244 if (sc->sc_stat & RSB_STAT_MASK) { 245 break; 246 } 247 if (flags & I2C_F_POLL) { 248 delay(10000); 249 } 250 } 251 if (retry == 0) 252 error = EAGAIN; 253 254 if (flags & I2C_F_POLL) { 255 RSB_WRITE(sc, RSB_STAT_REG, 256 sc->sc_stat & RSB_STAT_MASK); 257 } 258 259 if (error) { 260 /* Abort transaction */ 261 device_printf(sc->sc_dev, "transfer timeout, error = %d\n", 262 error); 263 RSB_WRITE(sc, RSB_CTRL_REG, 264 RSB_CTRL_ABORT_TRANS); 265 return error; 266 } 267 268 if (sc->sc_stat & RSB_STAT_LOAD_BSY) { 269 device_printf(sc->sc_dev, "transfer busy\n"); 270 return EBUSY; 271 } 272 if (sc->sc_stat & RSB_STAT_TRANS_ERR) { 273 device_printf(sc->sc_dev, "transfer error, id 0x%02" PRIx64 274 "\n", __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID)); 275 return EIO; 276 } 277 278 return 0; 279 } 280 281 static int 282 sunxi_rsb_rsb_config(struct sunxi_rsb_softc *sc, uint8_t rta, i2c_addr_t da, 283 int flags) 284 { 285 uint32_t dar, ctrl; 286 287 KASSERT(mutex_owned(&sc->sc_intr_lock)); 288 289 RSB_WRITE(sc, RSB_STAT_REG, 290 RSB_READ(sc, RSB_STAT_REG) & RSB_STAT_MASK); 291 292 dar = __SHIFTIN(rta, RSB_DAR_RTA); 293 dar |= __SHIFTIN(da, RSB_DAR_DA); 294 RSB_WRITE(sc, RSB_DAR_REG, dar); 295 RSB_WRITE(sc, RSB_CMD_REG, RSB_CMD_IDX_SRTA); 296 297 /* Make sure the controller is idle */ 298 ctrl = RSB_READ(sc, RSB_CTRL_REG); 299 if (ctrl & RSB_CTRL_START_TRANS) { 300 device_printf(sc->sc_dev, "device is busy\n"); 301 return EBUSY; 302 } 303 304 /* Start the transfer */ 305 RSB_WRITE(sc, RSB_CTRL_REG, 306 ctrl | RSB_CTRL_START_TRANS); 307 308 return sunxi_rsb_wait(sc, flags); 309 } 310 311 static int 312 sunxi_rsb_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 313 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 314 { 315 struct sunxi_rsb_softc *sc = priv; 316 uint32_t dlen, ctrl; 317 uint8_t rta; 318 int error, i; 319 320 if (cmdlen != 1 || (len != 1 && len != 2 && len != 4)) 321 return EINVAL; 322 323 mutex_enter(&sc->sc_intr_lock); 324 325 error = sunxi_rsb_soft_reset(sc); 326 if (error != 0) { 327 mutex_exit(&sc->sc_intr_lock); 328 device_printf(sc->sc_dev, "soft reset timed out\n"); 329 return error; 330 } 331 332 if ((flags & I2C_F_POLL) == 0) { 333 /* Enable interrupts */ 334 RSB_WRITE(sc, RSB_INTE_REG, 335 RSB_INTE_LOAD_BSY_ENB | 336 RSB_INTE_TRANS_ERR_ENB | 337 RSB_INTE_TRANS_OVER_ENB); 338 RSB_WRITE(sc, RSB_CTRL_REG, 339 RSB_CTRL_GLOBAL_INT_ENB); 340 } 341 342 if (sc->sc_type == SUNXI_RSB && sc->sc_rsb_last_da != addr) { 343 /* Lookup run-time address for given device address */ 344 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 345 if (rsb_rtamap[i].addr == addr) { 346 rta = rsb_rtamap[i].rta; 347 break; 348 } 349 if (rta == 0) { 350 mutex_exit(&sc->sc_intr_lock); 351 device_printf(sc->sc_dev, 352 "RTA not known for address %#x\n", addr); 353 return ENXIO; 354 } 355 error = sunxi_rsb_rsb_config(sc, rta, addr, flags); 356 if (error) { 357 device_printf(sc->sc_dev, 358 "SRTA failed, flags = %x, error = %d\n", 359 flags, error); 360 sc->sc_rsb_last_da = 0; 361 goto done; 362 } 363 364 sc->sc_rsb_last_da = addr; 365 } 366 367 /* Data byte register */ 368 RSB_WRITE(sc, RSB_DADDR0_REG, *(const uint8_t *)cmdbuf); 369 370 if (I2C_OP_WRITE_P(op)) { 371 uint8_t *pbuf = buf; 372 uint32_t data; 373 /* Write data */ 374 switch (len) { 375 case 1: 376 data = pbuf[0]; 377 break; 378 case 2: 379 data = pbuf[0] | (pbuf[1] << 8); 380 break; 381 case 4: 382 data = pbuf[0] | (pbuf[1] << 8) | 383 (pbuf[2] << 16) | (pbuf[3] << 24); 384 break; 385 default: 386 error = EINVAL; 387 goto done; 388 } 389 RSB_WRITE(sc, RSB_DATA0_REG, data); 390 } 391 392 if (sc->sc_type == SUNXI_RSB) { 393 uint8_t cmd; 394 if (I2C_OP_WRITE_P(op)) { 395 switch (len) { 396 case 1: cmd = RSB_CMD_IDX_WR8; break; 397 case 2: cmd = RSB_CMD_IDX_WR16; break; 398 case 4: cmd = RSB_CMD_IDX_WR32; break; 399 default: error = EINVAL; goto done; 400 } 401 } else { 402 switch (len) { 403 case 1: cmd = RSB_CMD_IDX_RD8; break; 404 case 2: cmd = RSB_CMD_IDX_RD16; break; 405 case 4: cmd = RSB_CMD_IDX_RD32; break; 406 default: error = EINVAL; goto done; 407 } 408 } 409 RSB_WRITE(sc, RSB_CMD_REG, cmd); 410 } 411 412 /* Program data length register; if reading, set read/write bit */ 413 dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH); 414 if (I2C_OP_READ_P(op)) { 415 dlen |= RSB_DLEN_READ_WRITE_FLAG; 416 } 417 RSB_WRITE(sc, RSB_DLEN_REG, dlen); 418 419 /* Make sure the controller is idle */ 420 ctrl = RSB_READ(sc, RSB_CTRL_REG); 421 if (ctrl & RSB_CTRL_START_TRANS) { 422 device_printf(sc->sc_dev, "device is busy\n"); 423 error = EBUSY; 424 goto done; 425 } 426 427 /* Start the transfer */ 428 RSB_WRITE(sc, RSB_CTRL_REG, 429 ctrl | RSB_CTRL_START_TRANS); 430 431 error = sunxi_rsb_wait(sc, flags); 432 if (error) 433 goto done; 434 435 if (I2C_OP_READ_P(op)) { 436 uint32_t data = RSB_READ(sc, RSB_DATA0_REG); 437 switch (len) { 438 case 4: 439 *(uint32_t *)buf = data; 440 break; 441 case 2: 442 *(uint16_t *)buf = data & 0xffff; 443 break; 444 case 1: 445 *(uint8_t *)buf = data & 0xff; 446 break; 447 default: 448 error = EINVAL; 449 goto done; 450 } 451 } 452 453 error = 0; 454 455 done: 456 RSB_WRITE(sc, RSB_CTRL_REG, 0); 457 mutex_exit(&sc->sc_intr_lock); 458 459 return error; 460 } 461