1 /* $NetBSD: sunxi_nmi.c,v 1.5 2020/02/16 20:29:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define _INTR_PRIVATE 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_nmi.c,v 1.5 2020/02/16 20:29:36 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/systm.h> 40 #include <sys/atomic.h> 41 #include <sys/mutex.h> 42 #include <sys/lwp.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/cpu.h> 47 #include <arm/pic/picvar.h> 48 #include <arm/fdt/arm_fdtvar.h> 49 50 /* ctrl_reg */ 51 #define NMI_CTRL_IRQ_LOW_LEVEL 0 52 #define NMI_CTRL_IRQ_LOW_EDGE 1 53 #define NMI_CTRL_IRQ_HIGH_LEVEL 2 54 #define NMI_CTRL_IRQ_HIGH_EDGE 3 55 #define NMI_CTRL_IRQ_TYPE __BITS(1,0) 56 57 /* pend_reg */ 58 #define NMI_PEND_IRQ_ACK __BIT(0) 59 60 /* enable_reg */ 61 #define NMI_ENABLE_IRQEN __BIT(0) 62 63 struct sunxi_nmi_config { 64 const char * name; 65 bus_size_t ctrl_reg; 66 bus_size_t pend_reg; 67 bus_size_t enable_reg; 68 }; 69 70 static const struct sunxi_nmi_config sun7i_a20_sc_nmi_config = { 71 .name = "NMI", 72 .ctrl_reg = 0x00, 73 .pend_reg = 0x04, 74 .enable_reg = 0x08, 75 }; 76 77 static const struct sunxi_nmi_config sun6i_a31_r_intc_config = { 78 .name = "R_INTC", 79 .ctrl_reg = 0x0c, 80 .pend_reg = 0x10, 81 .enable_reg = 0x40, 82 }; 83 84 static const struct sunxi_nmi_config sun9i_a80_nmi_config = { 85 .name = "NMI", 86 .ctrl_reg = 0x00, 87 .pend_reg = 0x04, 88 .enable_reg = 0x08, 89 }; 90 91 static const struct of_compat_data compat_data[] = { 92 { "allwinner,sun7i-a20-sc-nmi", (uintptr_t)&sun7i_a20_sc_nmi_config }, 93 { "allwinner,sun6i-a31-r-intc", (uintptr_t)&sun6i_a31_r_intc_config }, 94 { "allwinner,sun9i-a80-nmi", (uintptr_t)&sun9i_a80_nmi_config }, 95 { NULL } 96 }; 97 98 struct sunxi_nmi_softc { 99 device_t sc_dev; 100 bus_space_tag_t sc_bst; 101 bus_space_handle_t sc_bsh; 102 int sc_phandle; 103 104 kmutex_t sc_intr_lock; 105 106 const struct sunxi_nmi_config *sc_config; 107 108 struct intrsource sc_is; 109 void *sc_ih; 110 }; 111 112 #define NMI_READ(sc, reg) \ 113 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 114 #define NMI_WRITE(sc, reg, val) \ 115 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 116 117 static void 118 sunxi_nmi_irq_ack(struct sunxi_nmi_softc *sc) 119 { 120 uint32_t val; 121 122 val = NMI_READ(sc, sc->sc_config->pend_reg); 123 val |= NMI_PEND_IRQ_ACK; 124 NMI_WRITE(sc, sc->sc_config->pend_reg, val); 125 } 126 127 static void 128 sunxi_nmi_irq_enable(struct sunxi_nmi_softc *sc, bool on) 129 { 130 uint32_t val; 131 132 val = NMI_READ(sc, sc->sc_config->enable_reg); 133 if (on) 134 val |= NMI_ENABLE_IRQEN; 135 else 136 val &= ~NMI_ENABLE_IRQEN; 137 NMI_WRITE(sc, sc->sc_config->enable_reg, val); 138 } 139 140 static void 141 sunxi_nmi_irq_set_type(struct sunxi_nmi_softc *sc, u_int irq_type) 142 { 143 uint32_t val; 144 145 val = NMI_READ(sc, sc->sc_config->ctrl_reg); 146 val &= ~NMI_CTRL_IRQ_TYPE; 147 val |= __SHIFTIN(irq_type, NMI_CTRL_IRQ_TYPE); 148 NMI_WRITE(sc, sc->sc_config->ctrl_reg, val); 149 } 150 151 static int 152 sunxi_nmi_intr(void *priv) 153 { 154 struct sunxi_nmi_softc * const sc = priv; 155 int (*func)(void *); 156 int rv = 0; 157 158 func = atomic_load_acquire(&sc->sc_is.is_func); 159 if (func) 160 rv = func(sc->sc_is.is_arg); 161 162 /* 163 * We don't serialize access to this register because we're the 164 * only thing fiddling wth it. 165 */ 166 sunxi_nmi_irq_ack(sc); 167 168 return rv; 169 } 170 171 static void * 172 sunxi_nmi_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 173 int (*func)(void *), void *arg) 174 { 175 struct sunxi_nmi_softc * const sc = device_private(dev); 176 u_int irq_type; 177 int ist; 178 179 /* 1st cell is the interrupt number */ 180 const u_int irq = be32toh(specifier[0]); 181 /* 2nd cell is polarity */ 182 const u_int pol = be32toh(specifier[1]); 183 184 if (irq != 0) { 185 #ifdef DIAGNOSTIC 186 device_printf(dev, "IRQ %u is invalid\n", irq); 187 #endif 188 return NULL; 189 } 190 191 switch (pol & 0x7) { 192 case 1: /* IRQ_TYPE_EDGE_RISING */ 193 irq_type = NMI_CTRL_IRQ_HIGH_EDGE; 194 ist = IST_EDGE; 195 break; 196 case 2: /* IRQ_TYPE_EDGE_FALLING */ 197 irq_type = NMI_CTRL_IRQ_LOW_EDGE; 198 ist = IST_EDGE; 199 break; 200 case 3: /* IRQ_TYPE_LEVEL_HIGH */ 201 irq_type = NMI_CTRL_IRQ_HIGH_LEVEL; 202 ist = IST_LEVEL; 203 break; 204 case 4: /* IRQ_TYPE_LEVEL_LOW */ 205 irq_type = NMI_CTRL_IRQ_LOW_LEVEL; 206 ist = IST_LEVEL; 207 break; 208 default: 209 irq_type = NMI_CTRL_IRQ_LOW_LEVEL; 210 ist = IST_LEVEL; 211 break; 212 } 213 214 mutex_enter(&sc->sc_intr_lock); 215 216 if (atomic_load_relaxed(&sc->sc_is.is_func) != NULL) { 217 mutex_exit(&sc->sc_intr_lock); 218 #ifdef DIAGNOSTIC 219 device_printf(dev, "%s in use\n", sc->sc_config->name); 220 #endif 221 return NULL; 222 } 223 224 sc->sc_is.is_arg = arg; 225 atomic_store_release(&sc->sc_is.is_func, func); 226 227 sc->sc_is.is_type = ist; 228 sc->sc_is.is_ipl = ipl; 229 sc->sc_is.is_mpsafe = (flags & FDT_INTR_MPSAFE) ? true : false; 230 231 mutex_exit(&sc->sc_intr_lock); 232 233 sc->sc_ih = fdtbus_intr_establish(sc->sc_phandle, 0, ipl, flags, 234 sunxi_nmi_intr, sc); 235 236 mutex_enter(&sc->sc_intr_lock); 237 sunxi_nmi_irq_set_type(sc, irq_type); 238 sunxi_nmi_irq_enable(sc, true); 239 mutex_exit(&sc->sc_intr_lock); 240 241 return &sc->sc_is; 242 } 243 244 static void 245 sunxi_nmi_fdt_mask(device_t dev, void *ih __unused) 246 { 247 struct sunxi_nmi_softc * const sc = device_private(dev); 248 249 mutex_enter(&sc->sc_intr_lock); 250 if (sc->sc_is.is_mask_count++ == 0) { 251 sunxi_nmi_irq_enable(sc, false); 252 } 253 mutex_exit(&sc->sc_intr_lock); 254 } 255 256 static void 257 sunxi_nmi_fdt_unmask(device_t dev, void *ih __unused) 258 { 259 struct sunxi_nmi_softc * const sc = device_private(dev); 260 261 mutex_enter(&sc->sc_intr_lock); 262 if (sc->sc_is.is_mask_count-- == 1) { 263 sunxi_nmi_irq_enable(sc, true); 264 } 265 mutex_exit(&sc->sc_intr_lock); 266 } 267 268 static void 269 sunxi_nmi_fdt_disestablish(device_t dev, void *ih) 270 { 271 struct sunxi_nmi_softc * const sc = device_private(dev); 272 struct intrsource * const is = ih; 273 274 KASSERT(is == &sc->sc_is); 275 276 mutex_enter(&sc->sc_intr_lock); 277 sunxi_nmi_irq_enable(sc, false); 278 is->is_mask_count = 0; 279 mutex_exit(&sc->sc_intr_lock); 280 281 fdtbus_intr_disestablish(sc->sc_phandle, sc->sc_ih); 282 sc->sc_ih = NULL; 283 284 mutex_enter(&sc->sc_intr_lock); 285 is->is_arg = NULL; 286 is->is_func = NULL; 287 mutex_exit(&sc->sc_intr_lock); 288 } 289 290 static bool 291 sunxi_nmi_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 292 { 293 struct sunxi_nmi_softc * const sc = device_private(dev); 294 295 snprintf(buf, buflen, "%s", sc->sc_config->name); 296 297 return true; 298 } 299 300 static const struct fdtbus_interrupt_controller_func sunxi_nmi_fdt_funcs = { 301 .establish = sunxi_nmi_fdt_establish, 302 .disestablish = sunxi_nmi_fdt_disestablish, 303 .intrstr = sunxi_nmi_fdt_intrstr, 304 .mask = sunxi_nmi_fdt_mask, 305 .unmask = sunxi_nmi_fdt_unmask, 306 }; 307 308 static int 309 sunxi_nmi_match(device_t parent, cfdata_t cf, void *aux) 310 { 311 struct fdt_attach_args * const faa = aux; 312 313 return of_match_compat_data(faa->faa_phandle, compat_data); 314 } 315 316 static void 317 sunxi_nmi_attach(device_t parent, device_t self, void *aux) 318 { 319 struct sunxi_nmi_softc * const sc = device_private(self); 320 struct fdt_attach_args * const faa = aux; 321 const int phandle = faa->faa_phandle; 322 bus_addr_t addr; 323 bus_size_t size; 324 int error; 325 326 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 327 aprint_error(": couldn't get registers\n"); 328 return; 329 } 330 331 sc->sc_dev = self; 332 sc->sc_phandle = phandle; 333 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 334 sc->sc_bst = faa->faa_bst; 335 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 336 aprint_error(": couldn't map registers\n"); 337 return; 338 } 339 340 aprint_naive("\n"); 341 aprint_normal(": %s\n", sc->sc_config->name); 342 343 mutex_init(&sc->sc_intr_lock, MUTEX_SPIN, IPL_HIGH); 344 345 /* 346 * Normally it's assumed that an intrsource can be passed to 347 * interrupt_distribute(). We're providing our own that's 348 * independent of our parent PIC, but because we will leave 349 * the intrsource::is_pic field NULL, the right thing 350 * (i.e. nothing) will happen in interrupt_distribute(). 351 */ 352 snprintf(sc->sc_is.is_source, sizeof(sc->sc_is.is_source), 353 "%s", sc->sc_config->name); 354 355 sunxi_nmi_irq_enable(sc, false); 356 sunxi_nmi_irq_ack(sc); 357 358 error = fdtbus_register_interrupt_controller(self, phandle, 359 &sunxi_nmi_fdt_funcs); 360 if (error) { 361 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 362 error); 363 return; 364 } 365 } 366 367 CFATTACH_DECL_NEW(sunxi_nmi, sizeof(struct sunxi_nmi_softc), 368 sunxi_nmi_match, sunxi_nmi_attach, NULL, NULL); 369