1 /* $NetBSD: sunxi_intc.c,v 1.3 2017/10/24 15:07:09 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define _INTR_PRIVATE 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c,v 1.3 2017/10/24 15:07:09 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 41 #include <dev/fdt/fdtvar.h> 42 43 #include <arm/cpu.h> 44 #include <arm/pic/picvar.h> 45 #include <arm/fdt/arm_fdtvar.h> 46 47 #define INTC_MAX_SOURCES 96 48 #define INTC_MAX_GROUPS 3 49 50 #define INTC_VECTOR_REG 0x00 51 #define INTC_BASE_ADDR_REG 0x04 52 #define INTC_PROTECT_REG 0x08 53 #define INTC_PROTECT_EN __BIT(0) 54 #define INTC_NMII_CTRL_REG 0x0c 55 #define INTC_IRQ_PEND_REG(n) (0x10 + ((n) * 4)) 56 #define INTC_FIQ_PEND_REG(n) (0x20 + ((n) * 4)) 57 #define INTC_SEL_REG(n) (0x30 + ((n) * 4)) 58 #define INTC_EN_REG(n) (0x40 + ((n) * 4)) 59 #define INTC_MASK_REG(n) (0x50 + ((n) * 4)) 60 #define INTC_RESP_REG(n) (0x60 + ((n) * 4)) 61 #define INTC_FORCE_REG(n) (0x70 + ((n) * 4)) 62 #define INTC_SRC_PRIO_REG(n) (0x80 + ((n) * 4)) 63 64 static const char * const compatible[] = { 65 "allwinner,sun4i-a10-ic", 66 NULL 67 }; 68 69 struct sunxi_intc_softc { 70 device_t sc_dev; 71 bus_space_tag_t sc_bst; 72 bus_space_handle_t sc_bsh; 73 int sc_phandle; 74 75 uint32_t sc_enabled_irqs[INTC_MAX_GROUPS]; 76 77 struct pic_softc sc_pic; 78 }; 79 80 static struct sunxi_intc_softc *intc_softc; 81 82 #define PICTOSOFTC(pic) \ 83 ((void *)((uintptr_t)(pic) - offsetof(struct sunxi_intc_softc, sc_pic))) 84 85 #define INTC_READ(sc, reg) \ 86 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 87 #define INTC_WRITE(sc, reg, val) \ 88 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89 90 static void 91 sunxi_intc_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 92 { 93 struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 94 const u_int group = irqbase / 32; 95 96 KASSERT((mask & sc->sc_enabled_irqs[group]) == 0); 97 sc->sc_enabled_irqs[group] |= mask; 98 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 99 INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]); 100 } 101 102 static void 103 sunxi_intc_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 104 { 105 struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 106 const u_int group = irqbase / 32; 107 108 sc->sc_enabled_irqs[group] &= ~mask; 109 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 110 INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]); 111 } 112 113 static void 114 sunxi_intc_establish_irq(struct pic_softc *pic, struct intrsource *is) 115 { 116 KASSERT(is->is_irq < INTC_MAX_SOURCES); 117 KASSERT(is->is_type == IST_LEVEL); 118 } 119 120 static void 121 sunxi_intc_set_priority(struct pic_softc *pic, int ipl) 122 { 123 } 124 125 static const struct pic_ops sunxi_intc_picops = { 126 .pic_unblock_irqs = sunxi_intc_unblock_irqs, 127 .pic_block_irqs = sunxi_intc_block_irqs, 128 .pic_establish_irq = sunxi_intc_establish_irq, 129 .pic_set_priority = sunxi_intc_set_priority, 130 }; 131 132 static void * 133 sunxi_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 134 int (*func)(void *), void *arg) 135 { 136 /* 1st cell is the interrupt number */ 137 const u_int irq = be32toh(specifier[0]); 138 139 if (irq >= INTC_MAX_SOURCES) { 140 #ifdef DIAGNOSTIC 141 device_printf(dev, "IRQ %u is invalid\n", irq); 142 #endif 143 return NULL; 144 } 145 146 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 147 148 return intr_establish(irq, ipl, IST_LEVEL | mpsafe, func, arg); 149 } 150 151 static void 152 sunxi_intc_fdt_disestablish(device_t dev, void *ih) 153 { 154 intr_disestablish(ih); 155 } 156 157 static bool 158 sunxi_intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 159 { 160 /* 1st cell is the interrupt number */ 161 if (!specifier) 162 return false; 163 const u_int irq = be32toh(specifier[0]); 164 165 snprintf(buf, buflen, "INTC irq %d", irq); 166 167 return true; 168 } 169 170 static const struct fdtbus_interrupt_controller_func sunxi_intc_fdt_funcs = { 171 .establish = sunxi_intc_fdt_establish, 172 .disestablish = sunxi_intc_fdt_disestablish, 173 .intrstr = sunxi_intc_fdt_intrstr, 174 }; 175 176 static int 177 sunxi_intc_find_pending_irqs(struct sunxi_intc_softc *sc, u_int group) 178 { 179 uint32_t pend; 180 181 pend = INTC_READ(sc, INTC_IRQ_PEND_REG(group)); 182 pend &= sc->sc_enabled_irqs[group]; 183 184 if (pend == 0) 185 return 0; 186 187 INTC_WRITE(sc, INTC_IRQ_PEND_REG(group), pend); 188 189 return pic_mark_pending_sources(&sc->sc_pic, group * 32, pend); 190 } 191 192 static void 193 sunxi_intc_irq_handler(void *frame) 194 { 195 struct cpu_info * const ci = curcpu(); 196 struct sunxi_intc_softc * const sc = intc_softc; 197 const int oldipl = ci->ci_cpl; 198 const uint32_t oldipl_mask = __BIT(oldipl); 199 int ipl_mask = 0; 200 201 ci->ci_data.cpu_nintr++; 202 203 if (sc->sc_enabled_irqs[0]) 204 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 0); 205 if (sc->sc_enabled_irqs[1]) 206 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 1); 207 if (sc->sc_enabled_irqs[2]) 208 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 2); 209 210 if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 211 pic_do_pending_ints(I32_bit, oldipl, frame); 212 } 213 214 static int 215 sunxi_intc_match(device_t parent, cfdata_t cf, void *aux) 216 { 217 struct fdt_attach_args * const faa = aux; 218 219 return of_match_compatible(faa->faa_phandle, compatible); 220 } 221 222 static void 223 sunxi_intc_attach(device_t parent, device_t self, void *aux) 224 { 225 struct sunxi_intc_softc * const sc = device_private(self); 226 struct fdt_attach_args * const faa = aux; 227 const int phandle = faa->faa_phandle; 228 bus_addr_t addr; 229 bus_size_t size; 230 int error, i; 231 232 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 233 aprint_error(": couldn't get registers\n"); 234 return; 235 } 236 237 sc->sc_dev = self; 238 sc->sc_phandle = phandle; 239 sc->sc_bst = faa->faa_bst; 240 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 241 aprint_error(": couldn't map registers\n"); 242 return; 243 } 244 245 aprint_naive("\n"); 246 aprint_normal(": Interrupt Controller\n"); 247 248 /* Disable IRQs */ 249 for (i = 0; i < INTC_MAX_GROUPS; i++) { 250 INTC_WRITE(sc, INTC_EN_REG(i), 0); 251 INTC_WRITE(sc, INTC_MASK_REG(i), ~0U); 252 INTC_WRITE(sc, INTC_IRQ_PEND_REG(i), 253 INTC_READ(sc, INTC_IRQ_PEND_REG(i))); 254 } 255 /* Disable user mode access to intc registers */ 256 INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN); 257 258 sc->sc_pic.pic_ops = &sunxi_intc_picops; 259 sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES; 260 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc"); 261 pic_add(&sc->sc_pic, 0); 262 263 error = fdtbus_register_interrupt_controller(self, phandle, 264 &sunxi_intc_fdt_funcs); 265 if (error) { 266 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 267 error); 268 return; 269 } 270 271 KASSERT(intc_softc == NULL); 272 intc_softc = sc; 273 arm_fdt_irq_set_handler(sunxi_intc_irq_handler); 274 } 275 276 CFATTACH_DECL_NEW(sunxi_intc, sizeof(struct sunxi_intc_softc), 277 sunxi_intc_match, sunxi_intc_attach, NULL, NULL); 278