1 /* $NetBSD: sunxi_hdmi.c,v 1.10 2019/12/23 18:20:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmi.c,v 1.10 2019/12/23 18:20:02 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/kmem.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/proc.h> 42 #include <sys/mutex.h> 43 #include <sys/kthread.h> 44 45 #include <dev/fdt/fdtvar.h> 46 #include <dev/fdt/fdt_port.h> 47 48 #include <dev/i2c/i2cvar.h> 49 #include <dev/i2c/ddcvar.h> 50 #include <dev/i2c/ddcreg.h> 51 #include <dev/videomode/videomode.h> 52 #include <dev/videomode/edidvar.h> 53 54 #include <arm/sunxi/sunxi_hdmireg.h> 55 #include <arm/sunxi/sunxi_display.h> 56 57 enum sunxi_hdmi_type { 58 HDMI_A10 = 1, 59 HDMI_A31, 60 }; 61 62 struct sunxi_hdmi_softc { 63 device_t sc_dev; 64 int sc_phandle; 65 enum sunxi_hdmi_type sc_type; 66 bus_space_tag_t sc_bst; 67 bus_space_handle_t sc_bsh; 68 struct clk *sc_clk_ahb; 69 struct clk *sc_clk_mod; 70 struct clk *sc_clk_pll0; 71 struct clk *sc_clk_pll1; 72 void *sc_ih; 73 lwp_t *sc_thread; 74 75 struct i2c_controller sc_ic; 76 kmutex_t sc_exec_lock; 77 78 bool sc_display_connected; 79 char sc_display_vendor[16]; 80 char sc_display_product[16]; 81 82 u_int sc_display_mode; 83 u_int sc_current_display_mode; 84 #define DISPLAY_MODE_AUTO 0 85 #define DISPLAY_MODE_HDMI 1 86 #define DISPLAY_MODE_DVI 2 87 88 kmutex_t sc_pwr_lock; 89 int sc_pwr_refcount; /* reference who needs HDMI */ 90 91 uint32_t sc_ver; 92 unsigned int sc_i2c_blklen; 93 94 struct fdt_device_ports sc_ports; 95 struct fdt_endpoint *sc_in_ep; 96 struct fdt_endpoint *sc_in_rep; 97 struct fdt_endpoint *sc_out_ep; 98 }; 99 100 #define HDMI_READ(sc, reg) \ 101 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 102 #define HDMI_WRITE(sc, reg, val) \ 103 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)); 104 105 #define HDMI_1_3_P(sc) ((sc)->sc_ver == 0x00010003) 106 #define HDMI_1_4_P(sc) ((sc)->sc_ver == 0x00010004) 107 108 static const struct of_compat_data compat_data[] = { 109 {"allwinner,sun4i-a10-hdmi", HDMI_A10}, 110 {"allwinner,sun7i-a20-hdmi", HDMI_A10}, 111 {NULL} 112 }; 113 114 static int sunxi_hdmi_match(device_t, cfdata_t, void *); 115 static void sunxi_hdmi_attach(device_t, device_t, void *); 116 static void sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *); 117 static int sunxi_hdmi_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 118 size_t, void *, size_t, int); 119 static int sunxi_hdmi_i2c_xfer(void *, i2c_addr_t, uint8_t, uint8_t, 120 size_t, int, int); 121 static int sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *, int); 122 123 static int sunxi_hdmi_ep_activate(device_t, struct fdt_endpoint *, bool); 124 static int sunxi_hdmi_ep_enable(device_t, struct fdt_endpoint *, bool); 125 static void sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *); 126 static void sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *); 127 static int sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *, uint8_t *, 128 uint8_t); 129 static u_int sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *, 130 const struct edid_info *); 131 static void sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *, bool); 132 static void sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *, 133 const struct videomode *, u_int); 134 static void sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *, 135 const struct videomode *, u_int); 136 static void sunxi_hdmi_hpd(struct sunxi_hdmi_softc *); 137 static void sunxi_hdmi_thread(void *); 138 static int sunxi_hdmi_poweron(struct sunxi_hdmi_softc *, bool); 139 #if 0 140 static int sunxi_hdmi_intr(void *); 141 #endif 142 143 #if defined(DDB) 144 void sunxi_hdmi_dump_regs(void); 145 #endif 146 147 CFATTACH_DECL_NEW(sunxi_hdmi, sizeof(struct sunxi_hdmi_softc), 148 sunxi_hdmi_match, sunxi_hdmi_attach, NULL, NULL); 149 150 static int 151 sunxi_hdmi_match(device_t parent, cfdata_t cf, void *aux) 152 { 153 struct fdt_attach_args * const faa = aux; 154 155 return of_match_compat_data(faa->faa_phandle, compat_data); 156 } 157 158 static void 159 sunxi_hdmi_attach(device_t parent, device_t self, void *aux) 160 { 161 struct sunxi_hdmi_softc *sc = device_private(self); 162 struct fdt_attach_args * const faa = aux; 163 const int phandle = faa->faa_phandle; 164 bus_addr_t addr; 165 bus_size_t size; 166 uint32_t ver; 167 168 sc->sc_dev = self; 169 sc->sc_phandle = phandle; 170 sc->sc_bst = faa->faa_bst; 171 172 sc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 173 174 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 175 aprint_error(": couldn't get registers\n"); 176 } 177 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 178 aprint_error(": couldn't map registers\n"); 179 return; 180 } 181 182 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 183 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod"); 184 sc->sc_clk_pll0 = fdtbus_clock_get(phandle, "pll-0"); 185 sc->sc_clk_pll1 = fdtbus_clock_get(phandle, "pll-1"); 186 187 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mod == NULL 188 || sc->sc_clk_pll0 == NULL || sc->sc_clk_pll1 == NULL) { 189 aprint_error(": couldn't get clocks\n"); 190 aprint_debug_dev(self, "clk ahb %s mod %s pll-0 %s pll-1 %s\n", 191 sc->sc_clk_ahb == NULL ? "missing" : "present", 192 sc->sc_clk_mod == NULL ? "missing" : "present", 193 sc->sc_clk_pll0 == NULL ? "missing" : "present", 194 sc->sc_clk_pll1 == NULL ? "missing" : "present"); 195 return; 196 } 197 198 if (clk_enable(sc->sc_clk_ahb) != 0) { 199 aprint_error(": couldn't enable ahb clock\n"); 200 return; 201 } 202 ver = HDMI_READ(sc, SUNXI_HDMI_VERSION_ID_REG); 203 204 const int vmaj = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_H); 205 const int vmin = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_L); 206 207 aprint_naive("\n"); 208 aprint_normal(": HDMI %d.%d\n", vmaj, vmin); 209 210 sc->sc_ver = ver; 211 sc->sc_i2c_blklen = 16; 212 213 sc->sc_ports.dp_ep_activate = sunxi_hdmi_ep_activate; 214 sc->sc_ports.dp_ep_enable = sunxi_hdmi_ep_enable; 215 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 216 217 mutex_init(&sc->sc_pwr_lock, MUTEX_DEFAULT, IPL_NONE); 218 sunxi_hdmi_i2c_init(sc); 219 } 220 221 void 222 sunxi_hdmi_doreset(void) 223 { 224 device_t dev; 225 struct sunxi_hdmi_softc *sc; 226 int error; 227 228 for (int i = 0;;i++) { 229 dev = device_find_by_driver_unit("sunxihdmi", i); 230 if (dev == NULL) 231 return; 232 sc = device_private(dev); 233 234 error = clk_disable(sc->sc_clk_mod); 235 if (error) { 236 aprint_error_dev(dev, ": couldn't disable mod clock\n"); 237 return; 238 } 239 240 #if defined(SUNXI_HDMI_DEBUG) 241 sunxi_hdmi_dump_regs(); 242 #endif 243 244 /* 245 * reset device, in case it has been setup by firmware in an 246 * incompatible way 247 */ 248 for (int j = 0; j <= 0x500; j += 4) { 249 HDMI_WRITE(sc, j, 0); 250 } 251 252 if (clk_disable(sc->sc_clk_ahb) != 0) { 253 aprint_error_dev(dev, ": couldn't disable ahb clock\n"); 254 return; 255 } 256 } 257 } 258 259 static void 260 sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *sc) 261 { 262 struct i2c_controller *ic = &sc->sc_ic; 263 264 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_NONE); 265 266 iic_tag_init(ic); 267 ic->ic_cookie = sc; 268 ic->ic_exec = sunxi_hdmi_i2c_exec; 269 } 270 271 static int 272 sunxi_hdmi_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 273 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 274 { 275 struct sunxi_hdmi_softc *sc = priv; 276 uint8_t *pbuf; 277 uint8_t block; 278 int resid; 279 off_t off; 280 int err; 281 282 mutex_enter(&sc->sc_exec_lock); 283 284 KASSERT(op == I2C_OP_READ_WITH_STOP); 285 KASSERT(addr == DDC_ADDR); 286 KASSERT(cmdlen > 0); 287 KASSERT(buf != NULL); 288 289 err = sunxi_hdmi_i2c_reset(sc, flags); 290 if (err) 291 goto done; 292 293 block = *(const uint8_t *)cmdbuf; 294 off = (block & 1) ? 128 : 0; 295 296 pbuf = buf; 297 resid = len; 298 while (resid > 0) { 299 size_t blklen = uimin(resid, sc->sc_i2c_blklen); 300 301 err = sunxi_hdmi_i2c_xfer(sc, addr, block >> 1, off, blklen, 302 SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD, flags); 303 if (err) 304 goto done; 305 306 if (HDMI_1_3_P(sc)) { 307 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh, 308 SUNXI_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen); 309 } else { 310 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh, 311 SUNXI_A31_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen); 312 } 313 314 #ifdef SUNXI_HDMI_DEBUG 315 printf("off=%d:", (int)off); 316 for (int i = 0; i < blklen; i++) 317 printf(" %02x", pbuf[i]); 318 printf("\n"); 319 #endif 320 321 pbuf += blklen; 322 off += blklen; 323 resid -= blklen; 324 } 325 326 done: 327 mutex_exit(&sc->sc_exec_lock); 328 return err; 329 } 330 331 static int 332 sunxi_hdmi_i2c_xfer_1_3(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 333 size_t len, int type, int flags) 334 { 335 struct sunxi_hdmi_softc *sc = priv; 336 uint32_t val; 337 int retry; 338 339 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 340 val &= ~SUNXI_HDMI_DDC_CTRL_FIFO_DIR; 341 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val); 342 343 val |= __SHIFTIN(block, SUNXI_HDMI_DDC_SLAVE_ADDR_0); 344 val |= __SHIFTIN(0x60, SUNXI_HDMI_DDC_SLAVE_ADDR_1); 345 val |= __SHIFTIN(reg, SUNXI_HDMI_DDC_SLAVE_ADDR_2); 346 val |= __SHIFTIN(addr, SUNXI_HDMI_DDC_SLAVE_ADDR_3); 347 HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val); 348 349 val = HDMI_READ(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG); 350 val |= SUNXI_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR; 351 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val); 352 353 HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len); 354 355 HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type); 356 357 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 358 val |= SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START; 359 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val); 360 361 retry = 1000; 362 while (--retry > 0) { 363 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 364 if ((val & SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0) 365 break; 366 delay(1000); 367 } 368 if (retry == 0) 369 return ETIMEDOUT; 370 371 val = HDMI_READ(sc, SUNXI_HDMI_DDC_INT_STATUS_REG); 372 if ((val & SUNXI_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE) == 0) { 373 device_printf(sc->sc_dev, "xfer failed, status=%08x\n", val); 374 return EIO; 375 } 376 377 return 0; 378 } 379 380 static int 381 sunxi_hdmi_i2c_xfer_1_4(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 382 size_t len, int type, int flags) 383 { 384 struct sunxi_hdmi_softc *sc = priv; 385 uint32_t val; 386 int retry; 387 388 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG); 389 val |= SUNXI_A31_HDMI_DDC_FIFO_CTRL_RST; 390 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val); 391 392 val = __SHIFTIN(block, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR); 393 val |= __SHIFTIN(0x60, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD); 394 val |= __SHIFTIN(reg, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR); 395 val |= __SHIFTIN(addr, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR); 396 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val); 397 398 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_COMMAND_REG, 399 __SHIFTIN(len, SUNXI_A31_HDMI_DDC_COMMAND_DTC) | 400 __SHIFTIN(type, SUNXI_A31_HDMI_DDC_COMMAND_CMD)); 401 402 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG); 403 val |= SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START; 404 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, val); 405 406 retry = 1000; 407 while (--retry > 0) { 408 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG); 409 if ((val & SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0) 410 break; 411 if (flags & I2C_F_POLL) 412 delay(1000); 413 else 414 kpause("hdmiddc", false, mstohz(10), &sc->sc_exec_lock); 415 } 416 if (retry == 0) 417 return ETIMEDOUT; 418 419 return 0; 420 } 421 422 static int 423 sunxi_hdmi_i2c_xfer(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 424 size_t len, int type, int flags) 425 { 426 struct sunxi_hdmi_softc *sc = priv; 427 int rv; 428 429 if (HDMI_1_3_P(sc)) { 430 rv = sunxi_hdmi_i2c_xfer_1_3(priv, addr, block, reg, len, 431 type, flags); 432 } else { 433 rv = sunxi_hdmi_i2c_xfer_1_4(priv, addr, block, reg, len, 434 type, flags); 435 } 436 437 return rv; 438 } 439 440 static int 441 sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *sc, int flags) 442 { 443 uint32_t hpd, ctrl; 444 445 hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG); 446 if ((hpd & SUNXI_HDMI_HPD_HOTPLUG_DET) == 0) { 447 device_printf(sc->sc_dev, "no device detected\n"); 448 return ENODEV; /* no device plugged in */ 449 } 450 451 if (HDMI_1_3_P(sc)) { 452 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, 0); 453 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, 454 SUNXI_HDMI_DDC_CTRL_EN | SUNXI_HDMI_DDC_CTRL_SW_RST); 455 456 delay(1000); 457 458 ctrl = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 459 if (ctrl & SUNXI_HDMI_DDC_CTRL_SW_RST) { 460 device_printf(sc->sc_dev, "reset failed (1.3)\n"); 461 return EBUSY; 462 } 463 464 /* N=5,M=1 */ 465 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CLOCK_REG, 466 __SHIFTIN(5, SUNXI_HDMI_DDC_CLOCK_N) | 467 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_M)); 468 469 HDMI_WRITE(sc, SUNXI_HDMI_DDC_DBG_REG, 0x300); 470 } else { 471 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, 472 SUNXI_A31_HDMI_DDC_CTRL_SW_RST); 473 474 /* N=1,M=12 */ 475 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CLOCK_REG, 476 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_N) | 477 __SHIFTIN(12, SUNXI_HDMI_DDC_CLOCK_M)); 478 479 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, 480 SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_EN | 481 SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_EN | 482 SUNXI_A31_HDMI_DDC_CTRL_EN); 483 } 484 485 return 0; 486 } 487 488 static int 489 sunxi_hdmi_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 490 { 491 struct sunxi_hdmi_softc *sc = device_private(dev); 492 struct fdt_endpoint *in_ep, *out_ep; 493 int error; 494 495 /* our input is activated by tcon, we activate our output */ 496 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 497 panic("sunxi_hdmi_ep_activate: port %d", 498 fdt_endpoint_port_index(ep)); 499 } 500 501 if (!activate) 502 return EOPNOTSUPP; 503 504 /* check that out other input is not active */ 505 switch (fdt_endpoint_index(ep)) { 506 case 0: 507 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 508 SUNXI_PORT_INPUT, 1); 509 break; 510 case 1: 511 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 512 SUNXI_PORT_INPUT, 0); 513 break; 514 default: 515 in_ep = NULL; 516 panic("sunxi_hdmi_ep_activate: input index %d", 517 fdt_endpoint_index(ep)); 518 } 519 if (in_ep != NULL) { 520 if (fdt_endpoint_is_active(in_ep)) 521 return EBUSY; 522 } 523 /* only one output */ 524 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 525 SUNXI_PORT_OUTPUT, 0); 526 if (out_ep == NULL) { 527 aprint_error_dev(dev, "no output endpoint\n"); 528 return ENODEV; 529 } 530 error = fdt_endpoint_activate(out_ep, activate); 531 if (error == 0) { 532 sc->sc_in_ep = ep; 533 sc->sc_in_rep = fdt_endpoint_remote(ep); 534 sc->sc_out_ep = out_ep; 535 sunxi_hdmi_do_enable(sc); 536 return 0; 537 } 538 return error; 539 } 540 541 static int 542 sunxi_hdmi_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 543 { 544 struct sunxi_hdmi_softc *sc = device_private(dev); 545 int error; 546 547 if (fdt_endpoint_port_index(ep) == SUNXI_PORT_INPUT) { 548 KASSERT(ep == sc->sc_in_ep); 549 if (sc->sc_thread == NULL) { 550 if (enable) { 551 delay(50000); 552 mutex_enter(&sc->sc_pwr_lock); 553 sunxi_hdmi_hpd(sc); 554 mutex_exit(&sc->sc_pwr_lock); 555 kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 556 sunxi_hdmi_thread, sc, &sc->sc_thread, "%s", 557 device_xname(dev)); 558 } 559 return 0; 560 } else { 561 mutex_enter(&sc->sc_pwr_lock); 562 error = sunxi_hdmi_poweron(sc, enable); 563 mutex_exit(&sc->sc_pwr_lock); 564 return error; 565 } 566 } 567 panic("sunxi_hdmi_ep_enable"); 568 } 569 570 static void 571 sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *sc) 572 { 573 /* complete attach */ 574 struct clk *clk; 575 int error; 576 uint32_t dbg0_reg; 577 578 if (clk_enable(sc->sc_clk_ahb) != 0) { 579 aprint_error_dev(sc->sc_dev, "couldn't enable ahb clock\n"); 580 return; 581 } 582 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 583 switch(fdt_endpoint_index(sc->sc_in_ep)) { 584 case 0: 585 clk = sc->sc_clk_pll0; 586 dbg0_reg = (0<<21); 587 break; 588 case 1: 589 clk = sc->sc_clk_pll1; 590 dbg0_reg = (1<<21); 591 break; 592 default: 593 panic("sunxi_hdmi pll"); 594 } 595 error = clk_set_rate(clk, 270000000); 596 if (error) { 597 clk = clk_get_parent(clk); 598 /* probably because this is pllx2 */ 599 error = clk_set_rate(clk, 270000000); 600 } 601 if (error) { 602 aprint_error_dev(sc->sc_dev, ": couldn't init pll clock\n"); 603 return; 604 } 605 error = clk_set_parent(sc->sc_clk_mod, clk); 606 if (error) { 607 aprint_error_dev(sc->sc_dev, ": couldn't set mod clock parent\n"); 608 return; 609 } 610 error = clk_enable(sc->sc_clk_mod); 611 if (error) { 612 aprint_error_dev(sc->sc_dev, ": couldn't enable mod clock\n"); 613 return; 614 } 615 delay(1000); 616 617 HDMI_WRITE(sc, SUNXI_HDMI_CTRL_REG, SUNXI_HDMI_CTRL_MODULE_EN); 618 delay(1000); 619 if (sc->sc_type == HDMI_A10) { 620 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0xfe800000); 621 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x00d8c830); 622 } else if (sc->sc_type == HDMI_A31) { 623 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0x7e80000f); 624 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x01ded030); 625 } 626 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, dbg0_reg); 627 delay(1000); 628 } 629 630 #define EDID_BLOCK_SIZE 128 631 632 static int 633 sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *sc, uint8_t *data, 634 uint8_t block) 635 { 636 i2c_tag_t tag = &sc->sc_ic; 637 uint8_t wbuf[2]; 638 int error; 639 640 if ((error = iic_acquire_bus(tag, 0)) != 0) 641 return error; 642 643 wbuf[0] = block; /* start address */ 644 645 error = iic_exec(tag, I2C_OP_READ_WITH_STOP, DDC_ADDR, wbuf, 1, 646 data, EDID_BLOCK_SIZE, 0); 647 iic_release_bus(tag, 0); 648 return error; 649 } 650 651 static void 652 sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *sc) 653 { 654 const struct videomode *mode; 655 char *edid; 656 struct edid_info *eip; 657 int retry = 4; 658 u_int display_mode; 659 660 edid = kmem_zalloc(EDID_BLOCK_SIZE, KM_SLEEP); 661 eip = kmem_zalloc(sizeof(struct edid_info), KM_SLEEP); 662 663 while (--retry > 0) { 664 if (!sunxi_hdmi_read_edid_block(sc, edid, 0)) 665 break; 666 } 667 if (retry == 0) { 668 device_printf(sc->sc_dev, "failed to read EDID\n"); 669 } else { 670 if (edid_parse(edid, eip) != 0) { 671 device_printf(sc->sc_dev, "failed to parse EDID\n"); 672 } 673 #ifdef SUNXI_HDMI_DEBUG 674 else { 675 edid_print(eip); 676 } 677 #endif 678 } 679 680 if (sc->sc_display_mode == DISPLAY_MODE_AUTO) 681 display_mode = sunxi_hdmi_get_display_mode(sc, eip); 682 else 683 display_mode = sc->sc_display_mode; 684 685 const char *forced = sc->sc_display_mode == DISPLAY_MODE_AUTO ? 686 "auto-detected" : "forced"; 687 device_printf(sc->sc_dev, "%s mode (%s)\n", 688 display_mode == DISPLAY_MODE_HDMI ? "HDMI" : "DVI", forced); 689 690 strlcpy(sc->sc_display_vendor, eip->edid_vendorname, 691 sizeof(sc->sc_display_vendor)); 692 strlcpy(sc->sc_display_product, eip->edid_productname, 693 sizeof(sc->sc_display_product)); 694 sc->sc_current_display_mode = display_mode; 695 696 mode = eip->edid_preferred_mode; 697 if (mode == NULL) 698 mode = pick_mode_by_ref(640, 480, 60); 699 700 if (mode != NULL) { 701 sunxi_hdmi_video_enable(sc, false); 702 fdt_endpoint_enable(sc->sc_in_ep, false); 703 delay(20000); 704 705 sunxi_tcon1_set_videomode( 706 fdt_endpoint_device(sc->sc_in_rep), mode); 707 sunxi_hdmi_set_videomode(sc, mode, display_mode); 708 sunxi_hdmi_set_audiomode(sc, mode, display_mode); 709 fdt_endpoint_enable(sc->sc_in_ep, true); 710 delay(20000); 711 sunxi_hdmi_video_enable(sc, true); 712 } 713 kmem_free(edid, EDID_BLOCK_SIZE); 714 kmem_free(eip, sizeof(struct edid_info)); 715 } 716 717 static u_int 718 sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *sc, 719 const struct edid_info *ei) 720 { 721 char *edid; 722 bool found_hdmi = false; 723 unsigned int n, p; 724 edid = kmem_zalloc(EDID_BLOCK_SIZE, KM_SLEEP); 725 726 /* 727 * Scan through extension blocks, looking for a CEA-861-D v3 728 * block. If an HDMI Vendor-Specific Data Block (HDMI VSDB) is 729 * found in that, assume HDMI mode. 730 */ 731 for (n = 1; n <= MIN(ei->edid_ext_block_count, 4); n++) { 732 if (sunxi_hdmi_read_edid_block(sc, edid, n)) { 733 #ifdef SUNXI_HDMI_DEBUG 734 device_printf(sc->sc_dev, 735 "Failed to read EDID block %d\n", n); 736 #endif 737 break; 738 } 739 740 #ifdef SUNXI_HDMI_DEBUG 741 device_printf(sc->sc_dev, "EDID block #%d:\n", n); 742 #endif 743 744 const uint8_t tag = edid[0]; 745 const uint8_t rev = edid[1]; 746 const uint8_t off = edid[2]; 747 748 #ifdef SUNXI_HDMI_DEBUG 749 device_printf(sc->sc_dev, " Tag %d, Revision %d, Offset %d\n", 750 tag, rev, off); 751 device_printf(sc->sc_dev, " Flags: 0x%02x\n", edid[3]); 752 #endif 753 754 /* We are looking for a CEA-861-D tag (02h) with revision 3 */ 755 if (tag != 0x02 || rev != 3) 756 continue; 757 /* 758 * CEA data block collection starts at byte 4, so the 759 * DTD blocks must start after it. 760 */ 761 if (off <= 4) 762 continue; 763 764 /* Parse the CEA data blocks */ 765 for (p = 4; p < off;) { 766 const uint8_t btag = (edid[p] >> 5) & 0x7; 767 const uint8_t blen = edid[p] & 0x1f; 768 769 #ifdef SUNXI_HDMI_DEBUG 770 device_printf(sc->sc_dev, " CEA data block @ %d\n", p); 771 device_printf(sc->sc_dev, " Tag %d, Length %d\n", 772 btag, blen); 773 #endif 774 775 /* Make sure the length is sane */ 776 if (p + blen + 1 > off) 777 break; 778 /* Looking for a VSDB tag */ 779 if (btag != 3) 780 goto next_block; 781 /* HDMI VSDB is at least 5 bytes long */ 782 if (blen < 5) 783 goto next_block; 784 785 #ifdef SUNXI_HDMI_DEBUG 786 device_printf(sc->sc_dev, " ID: %02x%02x%02x\n", 787 edid[p + 1], edid[p + 2], edid[p + 3]); 788 #endif 789 790 /* HDMI 24-bit IEEE registration ID is 0x000C03 */ 791 if (memcmp(&edid[p + 1], "\x03\x0c\x00", 3) == 0) 792 found_hdmi = true; 793 794 next_block: 795 p += (1 + blen); 796 } 797 } 798 799 kmem_free(edid, EDID_BLOCK_SIZE); 800 return found_hdmi ? DISPLAY_MODE_HDMI : DISPLAY_MODE_DVI; 801 } 802 803 static void 804 sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *sc, bool enable) 805 { 806 uint32_t val; 807 808 fdt_endpoint_enable(sc->sc_out_ep, enable); 809 810 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG); 811 val &= ~SUNXI_HDMI_VID_CTRL_SRC_SEL; 812 #ifdef SUNXI_HDMI_CBGEN 813 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_CBGEN, 814 SUNXI_HDMI_VID_CTRL_SRC_SEL); 815 #else 816 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_RGB, 817 SUNXI_HDMI_VID_CTRL_SRC_SEL); 818 #endif 819 if (enable) { 820 val |= SUNXI_HDMI_VID_CTRL_VIDEO_EN; 821 } else { 822 val &= ~SUNXI_HDMI_VID_CTRL_VIDEO_EN; 823 } 824 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val); 825 826 #if defined(SUNXI_HDMI_DEBUG) 827 sunxi_hdmi_dump_regs(); 828 #endif 829 } 830 831 static void 832 sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *sc, 833 const struct videomode *mode, u_int display_mode) 834 { 835 uint32_t val; 836 const u_int dblscan_p = !!(mode->flags & VID_DBLSCAN); 837 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 838 const u_int phsync_p = !!(mode->flags & VID_PHSYNC); 839 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC); 840 const u_int hfp = mode->hsync_start - mode->hdisplay; 841 const u_int hspw = mode->hsync_end - mode->hsync_start; 842 const u_int hbp = mode->htotal - mode->hsync_start; 843 const u_int vfp = mode->vsync_start - mode->vdisplay; 844 const u_int vspw = mode->vsync_end - mode->vsync_start; 845 const u_int vbp = mode->vtotal - mode->vsync_start; 846 struct clk *clk_pll; 847 int parent_rate; 848 int best_div, best_dbl, best_diff; 849 int target_rate = mode->dot_clock * 1000; 850 851 #ifdef SUNXI_HDMI_DEBUG 852 device_printf(sc->sc_dev, 853 "dblscan %d, interlace %d, phsync %d, pvsync %d\n", 854 dblscan_p, interlace_p, phsync_p, pvsync_p); 855 device_printf(sc->sc_dev, "h: %u %u %u %u\n", 856 mode->hdisplay, hbp, hfp, hspw); 857 device_printf(sc->sc_dev, "v: %u %u %u %u\n", 858 mode->vdisplay, vbp, vfp, vspw); 859 #endif 860 861 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, 0xffffffff); 862 863 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 864 switch(fdt_endpoint_index(sc->sc_in_ep)) { 865 case 0: 866 clk_pll = sc->sc_clk_pll0; 867 break; 868 case 1: 869 clk_pll = sc->sc_clk_pll1; 870 break; 871 default: 872 panic("sunxi_hdmi pll"); 873 } 874 parent_rate = clk_get_rate(clk_pll); 875 KASSERT(parent_rate > 0); 876 best_div = best_dbl = 0; 877 best_diff = INT_MAX; 878 for (int d = 2; d > 0 && best_diff != 0; d--) { 879 for (int m = 1; m <= 16 && best_diff != 0; m++) { 880 int cur_rate = parent_rate / m / d; 881 int diff = abs(target_rate - cur_rate); 882 if (diff >= 0 && diff < best_diff) { 883 best_diff = diff; 884 best_div = m; 885 best_dbl = d; 886 } 887 } 888 } 889 890 #ifdef SUNXI_HDMI_DEBUG 891 device_printf(sc->sc_dev, "parent rate: %d\n", parent_rate); 892 device_printf(sc->sc_dev, "dot_clock: %d\n", mode->dot_clock); 893 device_printf(sc->sc_dev, "clkdiv: %d\n", best_div); 894 device_printf(sc->sc_dev, "clkdbl: %c\n", (best_dbl == 1) ? 'Y' : 'N'); 895 #endif 896 897 if (best_div == 0) { 898 device_printf(sc->sc_dev, "ERROR: TCON clk not configured\n"); 899 return; 900 } 901 902 uint32_t pll_ctrl, pad_ctrl0, pad_ctrl1; 903 if (HDMI_1_4_P(sc)) { 904 pad_ctrl0 = 0x7e8000ff; 905 pad_ctrl1 = 0x01ded030; 906 pll_ctrl = 0xba48a308; 907 pll_ctrl |= __SHIFTIN(best_div - 1, SUNXI_HDMI_PLL_CTRL_PREDIV); 908 } else { 909 pad_ctrl0 = 0xfe800000; 910 pad_ctrl1 = 0x00d8c830; 911 pll_ctrl = 0xfa4ef708; 912 pll_ctrl |= __SHIFTIN(best_div, SUNXI_HDMI_PLL_CTRL_PREDIV); 913 } 914 if (best_dbl == 2) 915 pad_ctrl1 |= 0x40; 916 917 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, pad_ctrl0); 918 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, pad_ctrl1); 919 HDMI_WRITE(sc, SUNXI_HDMI_PLL_CTRL_REG, pll_ctrl); 920 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 921 switch(fdt_endpoint_index(sc->sc_in_ep)) { 922 case 0: 923 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (0<<21)); 924 break; 925 case 1: 926 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (1<<21)); 927 break; 928 default: 929 panic("sunxi_hdmi pll"); 930 } 931 932 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG); 933 val &= ~SUNXI_HDMI_VID_CTRL_HDMI_MODE; 934 if (display_mode == DISPLAY_MODE_DVI) { 935 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_DVI, 936 SUNXI_HDMI_VID_CTRL_HDMI_MODE); 937 } else { 938 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_HDMI, 939 SUNXI_HDMI_VID_CTRL_HDMI_MODE); 940 } 941 val &= ~SUNXI_HDMI_VID_CTRL_REPEATER_SEL; 942 if (dblscan_p) { 943 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_REPEATER_SEL_2X, 944 SUNXI_HDMI_VID_CTRL_REPEATER_SEL); 945 } 946 val &= ~SUNXI_HDMI_VID_CTRL_OUTPUT_FMT; 947 if (interlace_p) { 948 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE, 949 SUNXI_HDMI_VID_CTRL_OUTPUT_FMT); 950 } 951 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val); 952 953 val = __SHIFTIN((mode->hdisplay << dblscan_p) - 1, 954 SUNXI_HDMI_VID_TIMING_0_ACT_H); 955 val |= __SHIFTIN(mode->vdisplay - 1, 956 SUNXI_HDMI_VID_TIMING_0_ACT_V); 957 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_0_REG, val); 958 959 val = __SHIFTIN((hbp << dblscan_p) - 1, 960 SUNXI_HDMI_VID_TIMING_1_HBP); 961 val |= __SHIFTIN(vbp - 1, 962 SUNXI_HDMI_VID_TIMING_1_VBP); 963 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_1_REG, val); 964 965 val = __SHIFTIN((hfp << dblscan_p) - 1, 966 SUNXI_HDMI_VID_TIMING_2_HFP); 967 val |= __SHIFTIN(vfp - 1, 968 SUNXI_HDMI_VID_TIMING_2_VFP); 969 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_2_REG, val); 970 971 val = __SHIFTIN((hspw << dblscan_p) - 1, 972 SUNXI_HDMI_VID_TIMING_3_HSPW); 973 val |= __SHIFTIN(vspw - 1, 974 SUNXI_HDMI_VID_TIMING_3_VSPW); 975 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_3_REG, val); 976 977 val = 0; 978 if (phsync_p) { 979 val |= SUNXI_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL; 980 } 981 if (pvsync_p) { 982 val |= SUNXI_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL; 983 } 984 val |= __SHIFTIN(SUNXI_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL, 985 SUNXI_HDMI_VID_TIMING_4_TX_CLOCK); 986 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_4_REG, val); 987 988 /* Packet control */ 989 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT0_REG, 0); 990 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT1_REG, 0); 991 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL0_REG, 0x00005321); 992 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL1_REG, 0x0000000f); 993 } 994 995 static void 996 sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *sc, 997 const struct videomode *mode, u_int display_mode) 998 { 999 uint32_t cts, n, val; 1000 1001 /* 1002 * Before changing audio parameters, disable and reset the 1003 * audio module. Wait for the soft reset bit to clear before 1004 * configuring the audio parameters. 1005 */ 1006 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1007 val &= ~SUNXI_HDMI_AUD_CTRL_EN; 1008 val |= SUNXI_HDMI_AUD_CTRL_RST; 1009 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val); 1010 do { 1011 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1012 } while (val & SUNXI_HDMI_AUD_CTRL_RST); 1013 1014 /* No audio support in DVI mode */ 1015 if (display_mode != DISPLAY_MODE_HDMI) { 1016 return; 1017 } 1018 1019 /* DMA & FIFO control */ 1020 val = HDMI_READ(sc, SUNXI_HDMI_ADMA_CTRL_REG); 1021 if (sc->sc_type == HDMI_A31) { 1022 val |= SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* NDMA */ 1023 } else { 1024 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* DDMA */ 1025 } 1026 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_SAMPLE_RATE; 1027 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_SAMPLE_LAYOUT; 1028 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_WORD_LEN; 1029 val &= ~SUNXI_HDMI_ADMA_CTRL_DATA_SEL; 1030 HDMI_WRITE(sc, SUNXI_HDMI_ADMA_CTRL_REG, val); 1031 1032 /* Audio format control */ 1033 val = HDMI_READ(sc, SUNXI_HDMI_AUD_FMT_REG); 1034 val &= ~SUNXI_HDMI_AUD_FMT_SRC_SEL; 1035 val &= ~SUNXI_HDMI_AUD_FMT_SEL; 1036 val &= ~SUNXI_HDMI_AUD_FMT_DSD_FMT; 1037 val &= ~SUNXI_HDMI_AUD_FMT_LAYOUT; 1038 val &= ~SUNXI_HDMI_AUD_FMT_SRC_CH_CFG; 1039 val |= __SHIFTIN(1, SUNXI_HDMI_AUD_FMT_SRC_CH_CFG); 1040 HDMI_WRITE(sc, SUNXI_HDMI_AUD_FMT_REG, val); 1041 1042 /* PCM control (channel map) */ 1043 HDMI_WRITE(sc, SUNXI_HDMI_AUD_PCM_CTRL_REG, 0x76543210); 1044 1045 /* Clock setup */ 1046 n = 6144; /* 48 kHz */ 1047 cts = ((mode->dot_clock * 10) * (n / 128)) / 480; 1048 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts); 1049 HDMI_WRITE(sc, SUNXI_HDMI_AUD_N_REG, n); 1050 1051 /* Audio PCM channel status 0 */ 1052 val = __SHIFTIN(SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_48, 1053 SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ); 1054 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS0_REG, val); 1055 1056 /* Audio PCM channel status 1 */ 1057 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG); 1058 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_CGMS_A; 1059 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_ORIGINAL_FS; 1060 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN; 1061 val |= __SHIFTIN(5, SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN); 1062 val |= SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN_MAX; 1063 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG, val); 1064 1065 /* Re-enable */ 1066 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1067 val |= SUNXI_HDMI_AUD_CTRL_EN; 1068 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val); 1069 1070 #if defined(SUNXI_HDMI_DEBUG) 1071 sunxi_hdmi_dump_regs(); 1072 #endif 1073 } 1074 1075 static void 1076 sunxi_hdmi_hpd(struct sunxi_hdmi_softc *sc) 1077 { 1078 uint32_t hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG); 1079 bool con = !!(hpd & SUNXI_HDMI_HPD_HOTPLUG_DET); 1080 1081 KASSERT(mutex_owned(&sc->sc_pwr_lock)); 1082 if (sc->sc_display_connected == con) 1083 return; 1084 1085 if (con) { 1086 device_printf(sc->sc_dev, "display connected\n"); 1087 sc->sc_pwr_refcount = 1; 1088 sunxi_hdmi_read_edid(sc); 1089 } else { 1090 device_printf(sc->sc_dev, "display disconnected\n"); 1091 sc->sc_pwr_refcount = 0; 1092 sunxi_hdmi_video_enable(sc, false); 1093 fdt_endpoint_enable(sc->sc_in_ep, false); 1094 sunxi_tcon1_set_videomode( 1095 fdt_endpoint_device(sc->sc_in_rep), NULL); 1096 } 1097 1098 sc->sc_display_connected = con; 1099 } 1100 1101 static void 1102 sunxi_hdmi_thread(void *priv) 1103 { 1104 struct sunxi_hdmi_softc *sc = priv; 1105 1106 for (;;) { 1107 mutex_enter(&sc->sc_pwr_lock); 1108 sunxi_hdmi_hpd(sc); 1109 mutex_exit(&sc->sc_pwr_lock); 1110 kpause("hdmihotplug", false, mstohz(1000), NULL); 1111 } 1112 } 1113 1114 static int 1115 sunxi_hdmi_poweron(struct sunxi_hdmi_softc *sc, bool enable) 1116 { 1117 int error = 0; 1118 KASSERT(mutex_owned(&sc->sc_pwr_lock)); 1119 if (!sc->sc_display_connected) 1120 return EOPNOTSUPP; 1121 if (enable) { 1122 KASSERT(sc->sc_pwr_refcount >= 0); 1123 if (sc->sc_pwr_refcount == 0) { 1124 error = fdt_endpoint_enable(sc->sc_in_ep, true); 1125 if (error) 1126 return error; 1127 sunxi_hdmi_video_enable(sc, true); 1128 } 1129 sc->sc_pwr_refcount++; 1130 } else { 1131 sc->sc_pwr_refcount--; 1132 KASSERT(sc->sc_pwr_refcount >= 0); 1133 if (sc->sc_pwr_refcount == 0) { 1134 sunxi_hdmi_video_enable(sc, false); 1135 error = fdt_endpoint_enable(sc->sc_in_ep, false); 1136 } 1137 } 1138 return error; 1139 } 1140 #if 0 1141 static int 1142 sunxi_hdmi_intr(void *priv) 1143 { 1144 struct sunxi_hdmi_softc *sc = priv; 1145 uint32_t intsts; 1146 1147 intsts = HDMI_READ(sc, SUNXI_HDMI_INT_STATUS_REG); 1148 if (!(intsts & 0x73)) 1149 return 0; 1150 1151 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, intsts); 1152 1153 device_printf(sc->sc_dev, "INT_STATUS %08X\n", intsts); 1154 1155 return 1; 1156 } 1157 #endif 1158 1159 #if 0 /* XXX audio */ 1160 void 1161 sunxi_hdmi_get_info(struct sunxi_hdmi_info *info) 1162 { 1163 struct sunxi_hdmi_softc *sc; 1164 device_t dev; 1165 1166 memset(info, 0, sizeof(*info)); 1167 1168 dev = device_find_by_driver_unit("sunxihdmi", 0); 1169 if (dev == NULL) { 1170 info->display_connected = false; 1171 return; 1172 } 1173 sc = device_private(dev); 1174 1175 info->display_connected = sc->sc_display_connected; 1176 if (info->display_connected) { 1177 strlcpy(info->display_vendor, sc->sc_display_vendor, 1178 sizeof(info->display_vendor)); 1179 strlcpy(info->display_product, sc->sc_display_product, 1180 sizeof(info->display_product)); 1181 info->display_hdmimode = 1182 sc->sc_current_display_mode == DISPLAY_MODE_HDMI; 1183 } 1184 } 1185 #endif 1186 1187 #if defined(SUNXI_HDMI_DEBUG) 1188 void 1189 sunxi_hdmi_dump_regs(void) 1190 { 1191 static const struct { 1192 const char *name; 1193 uint16_t reg; 1194 } regs[] = { 1195 { "CTRL", SUNXI_HDMI_CTRL_REG }, 1196 { "INT_STATUS", SUNXI_HDMI_INT_STATUS_REG }, 1197 { "VID_CTRL", SUNXI_HDMI_VID_CTRL_REG }, 1198 { "VID_TIMING_0", SUNXI_HDMI_VID_TIMING_0_REG }, 1199 { "VID_TIMING_1", SUNXI_HDMI_VID_TIMING_1_REG }, 1200 { "VID_TIMING_2", SUNXI_HDMI_VID_TIMING_2_REG }, 1201 { "VID_TIMING_3", SUNXI_HDMI_VID_TIMING_3_REG }, 1202 { "VID_TIMING_4", SUNXI_HDMI_VID_TIMING_4_REG }, 1203 { "PAD_CTRL0", SUNXI_HDMI_PAD_CTRL0_REG }, 1204 { "PAD_CTRL1", SUNXI_HDMI_PAD_CTRL1_REG }, 1205 { "PLL_CTRL", SUNXI_HDMI_PLL_CTRL_REG }, 1206 { "PLL_DBG0", SUNXI_HDMI_PLL_DBG0_REG }, 1207 { "PLL_DBG1", SUNXI_HDMI_PLL_DBG1_REG }, 1208 }; 1209 struct sunxi_hdmi_softc *sc; 1210 device_t dev; 1211 1212 dev = device_find_by_driver_unit("sunxihdmi", 0); 1213 if (dev == NULL) 1214 return; 1215 sc = device_private(dev); 1216 1217 for (int i = 0; i < __arraycount(regs); i++) { 1218 printf("%s: 0x%08x\n", regs[i].name, 1219 HDMI_READ(sc, regs[i].reg)); 1220 } 1221 } 1222 #endif 1223