1 /* $NetBSD: sunxi_hdmi.c,v 1.3 2018/04/03 16:17:59 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmi.c,v 1.3 2018/04/03 16:17:59 bouyer Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/mutex.h> 42 #include <sys/kthread.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_port.h> 46 47 #include <dev/i2c/i2cvar.h> 48 #include <dev/i2c/ddcvar.h> 49 #include <dev/i2c/ddcreg.h> 50 #include <dev/videomode/videomode.h> 51 #include <dev/videomode/edidvar.h> 52 53 #include <arm/sunxi/sunxi_hdmireg.h> 54 #include <arm/sunxi/sunxi_display.h> 55 56 enum sunxi_hdmi_type { 57 HDMI_A10 = 1, 58 HDMI_A31, 59 }; 60 61 struct sunxi_hdmi_softc { 62 device_t sc_dev; 63 int sc_phandle; 64 enum sunxi_hdmi_type sc_type; 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 struct clk *sc_clk_ahb; 68 struct clk *sc_clk_mod; 69 struct clk *sc_clk_pll0; 70 struct clk *sc_clk_pll1; 71 void *sc_ih; 72 lwp_t *sc_thread; 73 74 struct i2c_controller sc_ic; 75 kmutex_t sc_ic_lock; 76 77 bool sc_display_connected; 78 char sc_display_vendor[16]; 79 char sc_display_product[16]; 80 81 u_int sc_display_mode; 82 u_int sc_current_display_mode; 83 #define DISPLAY_MODE_AUTO 0 84 #define DISPLAY_MODE_HDMI 1 85 #define DISPLAY_MODE_DVI 2 86 87 kmutex_t sc_pwr_lock; 88 int sc_pwr_refcount; /* reference who needs HDMI */ 89 90 uint32_t sc_ver; 91 unsigned int sc_i2c_blklen; 92 93 struct fdt_device_ports sc_ports; 94 struct fdt_endpoint *sc_in_ep; 95 struct fdt_endpoint *sc_in_rep; 96 struct fdt_endpoint *sc_out_ep; 97 }; 98 99 #define HDMI_READ(sc, reg) \ 100 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 101 #define HDMI_WRITE(sc, reg, val) \ 102 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)); 103 104 #define HDMI_1_3_P(sc) ((sc)->sc_ver == 0x00010003) 105 #define HDMI_1_4_P(sc) ((sc)->sc_ver == 0x00010004) 106 107 static const struct of_compat_data compat_data[] = { 108 {"allwinner,sun4i-a10-hdmi", HDMI_A10}, 109 {"allwinner,sun7i-a20-hdmi", HDMI_A10}, 110 {NULL} 111 }; 112 113 static int sunxi_hdmi_match(device_t, cfdata_t, void *); 114 static void sunxi_hdmi_attach(device_t, device_t, void *); 115 static void sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *); 116 static int sunxi_hdmi_i2c_acquire_bus(void *, int); 117 static void sunxi_hdmi_i2c_release_bus(void *, int); 118 static int sunxi_hdmi_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 119 size_t, void *, size_t, int); 120 static int sunxi_hdmi_i2c_xfer(void *, i2c_addr_t, uint8_t, uint8_t, 121 size_t, int, int); 122 static int sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *, int); 123 124 static int sunxi_hdmi_ep_activate(device_t, struct fdt_endpoint *, bool); 125 static int sunxi_hdmi_ep_enable(device_t, struct fdt_endpoint *, bool); 126 static void sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *); 127 static void sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *); 128 static int sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *, uint8_t *, 129 uint8_t); 130 static u_int sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *, 131 const struct edid_info *); 132 static void sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *, bool); 133 static void sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *, 134 const struct videomode *, u_int); 135 static void sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *, 136 const struct videomode *, u_int); 137 static void sunxi_hdmi_hpd(struct sunxi_hdmi_softc *); 138 static void sunxi_hdmi_thread(void *); 139 static int sunxi_hdmi_poweron(struct sunxi_hdmi_softc *, bool); 140 #if 0 141 static int sunxi_hdmi_intr(void *); 142 #endif 143 144 #if defined(DDB) 145 void sunxi_hdmi_dump_regs(void); 146 #endif 147 148 CFATTACH_DECL_NEW(sunxi_hdmi, sizeof(struct sunxi_hdmi_softc), 149 sunxi_hdmi_match, sunxi_hdmi_attach, NULL, NULL); 150 151 static int 152 sunxi_hdmi_match(device_t parent, cfdata_t cf, void *aux) 153 { 154 struct fdt_attach_args * const faa = aux; 155 156 return of_match_compat_data(faa->faa_phandle, compat_data); 157 } 158 159 static void 160 sunxi_hdmi_attach(device_t parent, device_t self, void *aux) 161 { 162 struct sunxi_hdmi_softc *sc = device_private(self); 163 struct fdt_attach_args * const faa = aux; 164 const int phandle = faa->faa_phandle; 165 bus_addr_t addr; 166 bus_size_t size; 167 uint32_t ver; 168 int error; 169 170 sc->sc_dev = self; 171 sc->sc_phandle = phandle; 172 sc->sc_bst = faa->faa_bst; 173 174 sc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 175 176 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 177 aprint_error(": couldn't get registers\n"); 178 } 179 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 180 aprint_error(": couldn't map registers\n"); 181 return; 182 } 183 184 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 185 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod"); 186 sc->sc_clk_pll0 = fdtbus_clock_get(phandle, "pll-0"); 187 sc->sc_clk_pll1 = fdtbus_clock_get(phandle, "pll-1"); 188 189 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mod == NULL 190 || sc->sc_clk_pll0 == NULL || sc->sc_clk_pll1 == NULL) { 191 aprint_error(": couldn't get clocks\n"); 192 aprint_debug_dev(self, "clk ahb %s mod %s pll-0 %s pll-1 %s\n", 193 sc->sc_clk_ahb == NULL ? "missing" : "present", 194 sc->sc_clk_mod == NULL ? "missing" : "present", 195 sc->sc_clk_pll0 == NULL ? "missing" : "present", 196 sc->sc_clk_pll1 == NULL ? "missing" : "present"); 197 return; 198 } 199 200 error = clk_disable(sc->sc_clk_mod); 201 if (error) { 202 aprint_error(": couldn't disable mod clock\n"); 203 return; 204 } 205 206 if (clk_enable(sc->sc_clk_ahb) != 0) { 207 aprint_error(": couldn't enable ahb clock\n"); 208 return; 209 } 210 #if defined(SUNXI_HDMI_DEBUG) 211 sunxi_hdmi_dump_regs(); 212 #endif 213 214 /* 215 * reset device, in case it has been setup by firmware in an 216 * incompatible way 217 */ 218 for (int i = 0; i <= 0x500; i += 4) { 219 HDMI_WRITE(sc, i, 0); 220 } 221 222 ver = HDMI_READ(sc, SUNXI_HDMI_VERSION_ID_REG); 223 224 const int vmaj = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_H); 225 const int vmin = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_L); 226 227 aprint_naive("\n"); 228 aprint_normal(": HDMI %d.%d\n", vmaj, vmin); 229 230 sc->sc_ver = ver; 231 sc->sc_i2c_blklen = 16; 232 233 sc->sc_ports.dp_ep_activate = sunxi_hdmi_ep_activate; 234 sc->sc_ports.dp_ep_enable = sunxi_hdmi_ep_enable; 235 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 236 237 mutex_init(&sc->sc_pwr_lock, MUTEX_DEFAULT, IPL_NONE); 238 sunxi_hdmi_i2c_init(sc); 239 240 if (clk_disable(sc->sc_clk_ahb) != 0) { 241 aprint_error(": couldn't disable ahb clock\n"); 242 return; 243 } 244 } 245 246 static void 247 sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *sc) 248 { 249 struct i2c_controller *ic = &sc->sc_ic; 250 251 mutex_init(&sc->sc_ic_lock, MUTEX_DEFAULT, IPL_NONE); 252 253 ic->ic_cookie = sc; 254 ic->ic_acquire_bus = sunxi_hdmi_i2c_acquire_bus; 255 ic->ic_release_bus = sunxi_hdmi_i2c_release_bus; 256 ic->ic_exec = sunxi_hdmi_i2c_exec; 257 } 258 259 static int 260 sunxi_hdmi_i2c_acquire_bus(void *priv, int flags) 261 { 262 struct sunxi_hdmi_softc *sc = priv; 263 264 if (flags & I2C_F_POLL) { 265 if (!mutex_tryenter(&sc->sc_ic_lock)) 266 return EBUSY; 267 } else { 268 mutex_enter(&sc->sc_ic_lock); 269 } 270 271 return 0; 272 } 273 274 static void 275 sunxi_hdmi_i2c_release_bus(void *priv, int flags) 276 { 277 struct sunxi_hdmi_softc *sc = priv; 278 279 mutex_exit(&sc->sc_ic_lock); 280 } 281 282 static int 283 sunxi_hdmi_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 284 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 285 { 286 struct sunxi_hdmi_softc *sc = priv; 287 uint8_t *pbuf; 288 uint8_t block; 289 int resid; 290 off_t off; 291 int err; 292 293 KASSERT(mutex_owned(&sc->sc_ic_lock)); 294 KASSERT(op == I2C_OP_READ_WITH_STOP); 295 KASSERT(addr == DDC_ADDR); 296 KASSERT(cmdlen > 0); 297 KASSERT(buf != NULL); 298 299 err = sunxi_hdmi_i2c_reset(sc, flags); 300 if (err) 301 goto done; 302 303 block = *(const uint8_t *)cmdbuf; 304 off = (block & 1) ? 128 : 0; 305 306 pbuf = buf; 307 resid = len; 308 while (resid > 0) { 309 size_t blklen = min(resid, sc->sc_i2c_blklen); 310 311 err = sunxi_hdmi_i2c_xfer(sc, addr, block >> 1, off, blklen, 312 SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD, flags); 313 if (err) 314 goto done; 315 316 if (HDMI_1_3_P(sc)) { 317 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh, 318 SUNXI_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen); 319 } else { 320 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh, 321 SUNXI_A31_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen); 322 } 323 324 #ifdef SUNXI_HDMI_DEBUG 325 printf("off=%d:", (int)off); 326 for (int i = 0; i < blklen; i++) 327 printf(" %02x", pbuf[i]); 328 printf("\n"); 329 #endif 330 331 pbuf += blklen; 332 off += blklen; 333 resid -= blklen; 334 } 335 336 done: 337 return err; 338 } 339 340 static int 341 sunxi_hdmi_i2c_xfer_1_3(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 342 size_t len, int type, int flags) 343 { 344 struct sunxi_hdmi_softc *sc = priv; 345 uint32_t val; 346 int retry; 347 348 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 349 val &= ~SUNXI_HDMI_DDC_CTRL_FIFO_DIR; 350 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val); 351 352 val |= __SHIFTIN(block, SUNXI_HDMI_DDC_SLAVE_ADDR_0); 353 val |= __SHIFTIN(0x60, SUNXI_HDMI_DDC_SLAVE_ADDR_1); 354 val |= __SHIFTIN(reg, SUNXI_HDMI_DDC_SLAVE_ADDR_2); 355 val |= __SHIFTIN(addr, SUNXI_HDMI_DDC_SLAVE_ADDR_3); 356 HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val); 357 358 val = HDMI_READ(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG); 359 val |= SUNXI_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR; 360 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val); 361 362 HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len); 363 364 HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type); 365 366 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 367 val |= SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START; 368 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val); 369 370 retry = 1000; 371 while (--retry > 0) { 372 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 373 if ((val & SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0) 374 break; 375 delay(1000); 376 } 377 if (retry == 0) 378 return ETIMEDOUT; 379 380 val = HDMI_READ(sc, SUNXI_HDMI_DDC_INT_STATUS_REG); 381 if ((val & SUNXI_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE) == 0) { 382 device_printf(sc->sc_dev, "xfer failed, status=%08x\n", val); 383 return EIO; 384 } 385 386 return 0; 387 } 388 389 static int 390 sunxi_hdmi_i2c_xfer_1_4(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 391 size_t len, int type, int flags) 392 { 393 struct sunxi_hdmi_softc *sc = priv; 394 uint32_t val; 395 int retry; 396 397 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG); 398 val |= SUNXI_A31_HDMI_DDC_FIFO_CTRL_RST; 399 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val); 400 401 val = __SHIFTIN(block, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR); 402 val |= __SHIFTIN(0x60, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD); 403 val |= __SHIFTIN(reg, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR); 404 val |= __SHIFTIN(addr, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR); 405 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val); 406 407 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_COMMAND_REG, 408 __SHIFTIN(len, SUNXI_A31_HDMI_DDC_COMMAND_DTC) | 409 __SHIFTIN(type, SUNXI_A31_HDMI_DDC_COMMAND_CMD)); 410 411 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG); 412 val |= SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START; 413 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, val); 414 415 retry = 1000; 416 while (--retry > 0) { 417 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG); 418 if ((val & SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0) 419 break; 420 if (cold) 421 delay(1000); 422 else 423 kpause("hdmiddc", false, mstohz(10), &sc->sc_ic_lock); 424 } 425 if (retry == 0) 426 return ETIMEDOUT; 427 428 return 0; 429 } 430 431 static int 432 sunxi_hdmi_i2c_xfer(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 433 size_t len, int type, int flags) 434 { 435 struct sunxi_hdmi_softc *sc = priv; 436 int rv; 437 438 if (HDMI_1_3_P(sc)) { 439 rv = sunxi_hdmi_i2c_xfer_1_3(priv, addr, block, reg, len, 440 type, flags); 441 } else { 442 rv = sunxi_hdmi_i2c_xfer_1_4(priv, addr, block, reg, len, 443 type, flags); 444 } 445 446 return rv; 447 } 448 449 static int 450 sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *sc, int flags) 451 { 452 uint32_t hpd, ctrl; 453 454 hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG); 455 if ((hpd & SUNXI_HDMI_HPD_HOTPLUG_DET) == 0) { 456 device_printf(sc->sc_dev, "no device detected\n"); 457 return ENODEV; /* no device plugged in */ 458 } 459 460 if (HDMI_1_3_P(sc)) { 461 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, 0); 462 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, 463 SUNXI_HDMI_DDC_CTRL_EN | SUNXI_HDMI_DDC_CTRL_SW_RST); 464 465 delay(1000); 466 467 ctrl = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 468 if (ctrl & SUNXI_HDMI_DDC_CTRL_SW_RST) { 469 device_printf(sc->sc_dev, "reset failed (1.3)\n"); 470 return EBUSY; 471 } 472 473 /* N=5,M=1 */ 474 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CLOCK_REG, 475 __SHIFTIN(5, SUNXI_HDMI_DDC_CLOCK_N) | 476 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_M)); 477 478 HDMI_WRITE(sc, SUNXI_HDMI_DDC_DBG_REG, 0x300); 479 } else { 480 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, 481 SUNXI_A31_HDMI_DDC_CTRL_SW_RST); 482 483 /* N=1,M=12 */ 484 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CLOCK_REG, 485 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_N) | 486 __SHIFTIN(12, SUNXI_HDMI_DDC_CLOCK_M)); 487 488 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, 489 SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_EN | 490 SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_EN | 491 SUNXI_A31_HDMI_DDC_CTRL_EN); 492 } 493 494 return 0; 495 } 496 497 static int 498 sunxi_hdmi_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 499 { 500 struct sunxi_hdmi_softc *sc = device_private(dev); 501 struct fdt_endpoint *in_ep, *out_ep; 502 int error; 503 504 /* our input is activated by tcon, we activate our output */ 505 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 506 panic("sunxi_hdmi_ep_activate: port %d", 507 fdt_endpoint_port_index(ep)); 508 } 509 510 if (!activate) 511 return EOPNOTSUPP; 512 513 /* check that out other input is not active */ 514 switch (fdt_endpoint_index(ep)) { 515 case 0: 516 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 517 SUNXI_PORT_INPUT, 1); 518 break; 519 case 1: 520 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 521 SUNXI_PORT_INPUT, 0); 522 break; 523 default: 524 in_ep = NULL; 525 panic("sunxi_hdmi_ep_activate: input index %d", 526 fdt_endpoint_index(ep)); 527 } 528 if (in_ep != NULL) { 529 if (fdt_endpoint_is_active(in_ep)) 530 return EBUSY; 531 } 532 /* only one output */ 533 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 534 SUNXI_PORT_OUTPUT, 0); 535 if (out_ep == NULL) { 536 aprint_error_dev(dev, "no output endpoint\n"); 537 return ENODEV; 538 } 539 error = fdt_endpoint_activate(out_ep, activate); 540 if (error == 0) { 541 sc->sc_in_ep = ep; 542 sc->sc_in_rep = fdt_endpoint_remote(ep); 543 sc->sc_out_ep = out_ep; 544 sunxi_hdmi_do_enable(sc); 545 return 0; 546 } 547 return error; 548 } 549 550 static int 551 sunxi_hdmi_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 552 { 553 struct sunxi_hdmi_softc *sc = device_private(dev); 554 int error; 555 556 if (fdt_endpoint_port_index(ep) == SUNXI_PORT_INPUT) { 557 KASSERT(ep == sc->sc_in_ep); 558 if (sc->sc_thread == NULL) { 559 if (enable) { 560 delay(50000); 561 mutex_enter(&sc->sc_pwr_lock); 562 sunxi_hdmi_hpd(sc); 563 mutex_exit(&sc->sc_pwr_lock); 564 kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 565 sunxi_hdmi_thread, sc, &sc->sc_thread, "%s", 566 device_xname(dev)); 567 } 568 return 0; 569 } else { 570 mutex_enter(&sc->sc_pwr_lock); 571 error = sunxi_hdmi_poweron(sc, enable); 572 mutex_exit(&sc->sc_pwr_lock); 573 return error; 574 } 575 } 576 panic("sunxi_hdmi_ep_enable"); 577 } 578 579 static void 580 sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *sc) 581 { 582 /* complete attach */ 583 struct clk *clk; 584 int error; 585 uint32_t dbg0_reg; 586 587 if (clk_enable(sc->sc_clk_ahb) != 0) { 588 aprint_error_dev(sc->sc_dev, "couldn't enable ahb clock\n"); 589 return; 590 } 591 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 592 switch(fdt_endpoint_index(sc->sc_in_ep)) { 593 case 0: 594 clk = sc->sc_clk_pll0; 595 dbg0_reg = (0<<21); 596 break; 597 case 1: 598 clk = sc->sc_clk_pll1; 599 dbg0_reg = (1<<21); 600 break; 601 default: 602 panic("sunxi_hdmi pll"); 603 } 604 error = clk_set_rate(clk, 270000000); 605 if (error) { 606 clk = clk_get_parent(clk); 607 /* probably because this is pllx2 */ 608 error = clk_set_rate(clk, 270000000); 609 } 610 if (error) { 611 aprint_error_dev(sc->sc_dev, ": couldn't init pll clock\n"); 612 return; 613 } 614 error = clk_set_parent(sc->sc_clk_mod, clk); 615 if (error) { 616 aprint_error_dev(sc->sc_dev, ": couldn't set mod clock parent\n"); 617 return; 618 } 619 error = clk_enable(sc->sc_clk_mod); 620 if (error) { 621 aprint_error_dev(sc->sc_dev, ": couldn't enable mod clock\n"); 622 return; 623 } 624 delay(1000); 625 626 HDMI_WRITE(sc, SUNXI_HDMI_CTRL_REG, SUNXI_HDMI_CTRL_MODULE_EN); 627 delay(1000); 628 if (sc->sc_type == HDMI_A10) { 629 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0xfe800000); 630 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x00d8c830); 631 } else if (sc->sc_type == HDMI_A31) { 632 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0x7e80000f); 633 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x01ded030); 634 } 635 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, dbg0_reg); 636 delay(1000); 637 } 638 639 static int 640 sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *sc, uint8_t *data, 641 uint8_t block) 642 { 643 i2c_tag_t tag = &sc->sc_ic; 644 uint8_t wbuf[2]; 645 int error; 646 647 if ((error = iic_acquire_bus(tag, I2C_F_POLL)) != 0) 648 return error; 649 650 wbuf[0] = block; /* start address */ 651 652 if ((error = iic_exec(tag, I2C_OP_READ_WITH_STOP, DDC_ADDR, wbuf, 1, 653 data, 128, I2C_F_POLL)) != 0) { 654 iic_release_bus(tag, I2C_F_POLL); 655 return error; 656 } 657 iic_release_bus(tag, I2C_F_POLL); 658 659 return 0; 660 } 661 662 static void 663 sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *sc) 664 { 665 const struct videomode *mode; 666 char edid[128]; 667 struct edid_info ei; 668 int retry = 4; 669 u_int display_mode; 670 671 memset(edid, 0, sizeof(edid)); 672 memset(&ei, 0, sizeof(ei)); 673 674 while (--retry > 0) { 675 if (!sunxi_hdmi_read_edid_block(sc, edid, 0)) 676 break; 677 } 678 if (retry == 0) { 679 device_printf(sc->sc_dev, "failed to read EDID\n"); 680 } else { 681 if (edid_parse(edid, &ei) != 0) { 682 device_printf(sc->sc_dev, "failed to parse EDID\n"); 683 } 684 #ifdef SUNXI_HDMI_DEBUG 685 else { 686 edid_print(&ei); 687 } 688 #endif 689 } 690 691 if (sc->sc_display_mode == DISPLAY_MODE_AUTO) 692 display_mode = sunxi_hdmi_get_display_mode(sc, &ei); 693 else 694 display_mode = sc->sc_display_mode; 695 696 const char *forced = sc->sc_display_mode == DISPLAY_MODE_AUTO ? 697 "auto-detected" : "forced"; 698 device_printf(sc->sc_dev, "%s mode (%s)\n", 699 display_mode == DISPLAY_MODE_HDMI ? "HDMI" : "DVI", forced); 700 701 strlcpy(sc->sc_display_vendor, ei.edid_vendorname, 702 sizeof(sc->sc_display_vendor)); 703 strlcpy(sc->sc_display_product, ei.edid_productname, 704 sizeof(sc->sc_display_product)); 705 sc->sc_current_display_mode = display_mode; 706 707 mode = ei.edid_preferred_mode; 708 if (mode == NULL) 709 mode = pick_mode_by_ref(640, 480, 60); 710 711 if (mode != NULL) { 712 sunxi_hdmi_video_enable(sc, false); 713 fdt_endpoint_enable(sc->sc_in_ep, false); 714 delay(20000); 715 716 sunxi_tcon1_set_videomode( 717 fdt_endpoint_device(sc->sc_in_rep), mode); 718 sunxi_hdmi_set_videomode(sc, mode, display_mode); 719 sunxi_hdmi_set_audiomode(sc, mode, display_mode); 720 fdt_endpoint_enable(sc->sc_in_ep, true); 721 delay(20000); 722 sunxi_hdmi_video_enable(sc, true); 723 } 724 } 725 726 static u_int 727 sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *sc, 728 const struct edid_info *ei) 729 { 730 char edid[128]; 731 bool found_hdmi = false; 732 unsigned int n, p; 733 734 /* 735 * Scan through extension blocks, looking for a CEA-861-D v3 736 * block. If an HDMI Vendor-Specific Data Block (HDMI VSDB) is 737 * found in that, assume HDMI mode. 738 */ 739 for (n = 1; n <= MIN(ei->edid_ext_block_count, 4); n++) { 740 if (sunxi_hdmi_read_edid_block(sc, edid, n)) { 741 #ifdef SUNXI_HDMI_DEBUG 742 device_printf(sc->sc_dev, 743 "Failed to read EDID block %d\n", n); 744 #endif 745 break; 746 } 747 748 #ifdef SUNXI_HDMI_DEBUG 749 device_printf(sc->sc_dev, "EDID block #%d:\n", n); 750 #endif 751 752 const uint8_t tag = edid[0]; 753 const uint8_t rev = edid[1]; 754 const uint8_t off = edid[2]; 755 756 #ifdef SUNXI_HDMI_DEBUG 757 device_printf(sc->sc_dev, " Tag %d, Revision %d, Offset %d\n", 758 tag, rev, off); 759 device_printf(sc->sc_dev, " Flags: 0x%02x\n", edid[3]); 760 #endif 761 762 /* We are looking for a CEA-861-D tag (02h) with revision 3 */ 763 if (tag != 0x02 || rev != 3) 764 continue; 765 /* 766 * CEA data block collection starts at byte 4, so the 767 * DTD blocks must start after it. 768 */ 769 if (off <= 4) 770 continue; 771 772 /* Parse the CEA data blocks */ 773 for (p = 4; p < off;) { 774 const uint8_t btag = (edid[p] >> 5) & 0x7; 775 const uint8_t blen = edid[p] & 0x1f; 776 777 #ifdef SUNXI_HDMI_DEBUG 778 device_printf(sc->sc_dev, " CEA data block @ %d\n", p); 779 device_printf(sc->sc_dev, " Tag %d, Length %d\n", 780 btag, blen); 781 #endif 782 783 /* Make sure the length is sane */ 784 if (p + blen + 1 > off) 785 break; 786 /* Looking for a VSDB tag */ 787 if (btag != 3) 788 goto next_block; 789 /* HDMI VSDB is at least 5 bytes long */ 790 if (blen < 5) 791 goto next_block; 792 793 #ifdef SUNXI_HDMI_DEBUG 794 device_printf(sc->sc_dev, " ID: %02x%02x%02x\n", 795 edid[p + 1], edid[p + 2], edid[p + 3]); 796 #endif 797 798 /* HDMI 24-bit IEEE registration ID is 0x000C03 */ 799 if (memcmp(&edid[p + 1], "\x03\x0c\x00", 3) == 0) 800 found_hdmi = true; 801 802 next_block: 803 p += (1 + blen); 804 } 805 } 806 807 return found_hdmi ? DISPLAY_MODE_HDMI : DISPLAY_MODE_DVI; 808 } 809 810 static void 811 sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *sc, bool enable) 812 { 813 uint32_t val; 814 815 fdt_endpoint_enable(sc->sc_out_ep, enable); 816 817 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG); 818 val &= ~SUNXI_HDMI_VID_CTRL_SRC_SEL; 819 #ifdef SUNXI_HDMI_CBGEN 820 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_CBGEN, 821 SUNXI_HDMI_VID_CTRL_SRC_SEL); 822 #else 823 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_RGB, 824 SUNXI_HDMI_VID_CTRL_SRC_SEL); 825 #endif 826 if (enable) { 827 val |= SUNXI_HDMI_VID_CTRL_VIDEO_EN; 828 } else { 829 val &= ~SUNXI_HDMI_VID_CTRL_VIDEO_EN; 830 } 831 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val); 832 833 #if defined(SUNXI_HDMI_DEBUG) 834 sunxi_hdmi_dump_regs(); 835 #endif 836 } 837 838 static void 839 sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *sc, 840 const struct videomode *mode, u_int display_mode) 841 { 842 uint32_t val; 843 const u_int dblscan_p = !!(mode->flags & VID_DBLSCAN); 844 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 845 const u_int phsync_p = !!(mode->flags & VID_PHSYNC); 846 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC); 847 const u_int hfp = mode->hsync_start - mode->hdisplay; 848 const u_int hspw = mode->hsync_end - mode->hsync_start; 849 const u_int hbp = mode->htotal - mode->hsync_start; 850 const u_int vfp = mode->vsync_start - mode->vdisplay; 851 const u_int vspw = mode->vsync_end - mode->vsync_start; 852 const u_int vbp = mode->vtotal - mode->vsync_start; 853 struct clk *clk_pll; 854 int parent_rate; 855 int best_div, best_dbl, best_diff; 856 int target_rate = mode->dot_clock * 1000; 857 858 #ifdef SUNXI_HDMI_DEBUG 859 device_printf(sc->sc_dev, 860 "dblscan %d, interlace %d, phsync %d, pvsync %d\n", 861 dblscan_p, interlace_p, phsync_p, pvsync_p); 862 device_printf(sc->sc_dev, "h: %u %u %u %u\n", 863 mode->hdisplay, hbp, hfp, hspw); 864 device_printf(sc->sc_dev, "v: %u %u %u %u\n", 865 mode->vdisplay, vbp, vfp, vspw); 866 #endif 867 868 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, 0xffffffff); 869 870 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 871 switch(fdt_endpoint_index(sc->sc_in_ep)) { 872 case 0: 873 clk_pll = sc->sc_clk_pll0; 874 break; 875 case 1: 876 clk_pll = sc->sc_clk_pll1; 877 break; 878 default: 879 panic("sunxi_hdmi pll"); 880 } 881 parent_rate = clk_get_rate(clk_pll); 882 KASSERT(parent_rate > 0); 883 best_div = best_dbl = 0; 884 best_diff = INT_MAX; 885 for (int d = 2; d > 0 && best_diff != 0; d--) { 886 for (int m = 1; m <= 16 && best_diff != 0; m++) { 887 int cur_rate = parent_rate / m / d; 888 int diff = abs(target_rate - cur_rate); 889 if (diff >= 0 && diff < best_diff) { 890 best_diff = diff; 891 best_div = m; 892 best_dbl = d; 893 } 894 } 895 } 896 897 #ifdef SUNXI_HDMI_DEBUG 898 device_printf(sc->sc_dev, "parent rate: %d\n", parent_rate); 899 device_printf(sc->sc_dev, "dot_clock: %d\n", mode->dot_clock); 900 device_printf(sc->sc_dev, "clkdiv: %d\n", best_div); 901 device_printf(sc->sc_dev, "clkdbl: %c\n", (best_dbl == 1) ? 'Y' : 'N'); 902 #endif 903 904 if (best_div == 0) { 905 device_printf(sc->sc_dev, "ERROR: TCON clk not configured\n"); 906 return; 907 } 908 909 uint32_t pll_ctrl, pad_ctrl0, pad_ctrl1; 910 if (HDMI_1_4_P(sc)) { 911 pad_ctrl0 = 0x7e8000ff; 912 pad_ctrl1 = 0x01ded030; 913 pll_ctrl = 0xba48a308; 914 pll_ctrl |= __SHIFTIN(best_div - 1, SUNXI_HDMI_PLL_CTRL_PREDIV); 915 } else { 916 pad_ctrl0 = 0xfe800000; 917 pad_ctrl1 = 0x00d8c830; 918 pll_ctrl = 0xfa4ef708; 919 pll_ctrl |= __SHIFTIN(best_div, SUNXI_HDMI_PLL_CTRL_PREDIV); 920 } 921 if (best_dbl == 2) 922 pad_ctrl1 |= 0x40; 923 924 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, pad_ctrl0); 925 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, pad_ctrl1); 926 HDMI_WRITE(sc, SUNXI_HDMI_PLL_CTRL_REG, pll_ctrl); 927 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 928 switch(fdt_endpoint_index(sc->sc_in_ep)) { 929 case 0: 930 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (0<<21)); 931 break; 932 case 1: 933 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (1<<21)); 934 break; 935 default: 936 panic("sunxi_hdmi pll"); 937 } 938 939 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG); 940 val &= ~SUNXI_HDMI_VID_CTRL_HDMI_MODE; 941 if (display_mode == DISPLAY_MODE_DVI) { 942 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_DVI, 943 SUNXI_HDMI_VID_CTRL_HDMI_MODE); 944 } else { 945 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_HDMI, 946 SUNXI_HDMI_VID_CTRL_HDMI_MODE); 947 } 948 val &= ~SUNXI_HDMI_VID_CTRL_REPEATER_SEL; 949 if (dblscan_p) { 950 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_REPEATER_SEL_2X, 951 SUNXI_HDMI_VID_CTRL_REPEATER_SEL); 952 } 953 val &= ~SUNXI_HDMI_VID_CTRL_OUTPUT_FMT; 954 if (interlace_p) { 955 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE, 956 SUNXI_HDMI_VID_CTRL_OUTPUT_FMT); 957 } 958 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val); 959 960 val = __SHIFTIN((mode->hdisplay << dblscan_p) - 1, 961 SUNXI_HDMI_VID_TIMING_0_ACT_H); 962 val |= __SHIFTIN(mode->vdisplay - 1, 963 SUNXI_HDMI_VID_TIMING_0_ACT_V); 964 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_0_REG, val); 965 966 val = __SHIFTIN((hbp << dblscan_p) - 1, 967 SUNXI_HDMI_VID_TIMING_1_HBP); 968 val |= __SHIFTIN(vbp - 1, 969 SUNXI_HDMI_VID_TIMING_1_VBP); 970 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_1_REG, val); 971 972 val = __SHIFTIN((hfp << dblscan_p) - 1, 973 SUNXI_HDMI_VID_TIMING_2_HFP); 974 val |= __SHIFTIN(vfp - 1, 975 SUNXI_HDMI_VID_TIMING_2_VFP); 976 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_2_REG, val); 977 978 val = __SHIFTIN((hspw << dblscan_p) - 1, 979 SUNXI_HDMI_VID_TIMING_3_HSPW); 980 val |= __SHIFTIN(vspw - 1, 981 SUNXI_HDMI_VID_TIMING_3_VSPW); 982 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_3_REG, val); 983 984 val = 0; 985 if (phsync_p) { 986 val |= SUNXI_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL; 987 } 988 if (pvsync_p) { 989 val |= SUNXI_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL; 990 } 991 val |= __SHIFTIN(SUNXI_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL, 992 SUNXI_HDMI_VID_TIMING_4_TX_CLOCK); 993 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_4_REG, val); 994 995 /* Packet control */ 996 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT0_REG, 0); 997 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT1_REG, 0); 998 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL0_REG, 0x00005321); 999 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL1_REG, 0x0000000f); 1000 } 1001 1002 static void 1003 sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *sc, 1004 const struct videomode *mode, u_int display_mode) 1005 { 1006 uint32_t cts, n, val; 1007 1008 /* 1009 * Before changing audio parameters, disable and reset the 1010 * audio module. Wait for the soft reset bit to clear before 1011 * configuring the audio parameters. 1012 */ 1013 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1014 val &= ~SUNXI_HDMI_AUD_CTRL_EN; 1015 val |= SUNXI_HDMI_AUD_CTRL_RST; 1016 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val); 1017 do { 1018 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1019 } while (val & SUNXI_HDMI_AUD_CTRL_RST); 1020 1021 /* No audio support in DVI mode */ 1022 if (display_mode != DISPLAY_MODE_HDMI) { 1023 return; 1024 } 1025 1026 /* DMA & FIFO control */ 1027 val = HDMI_READ(sc, SUNXI_HDMI_ADMA_CTRL_REG); 1028 if (sc->sc_type == HDMI_A31) { 1029 val |= SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* NDMA */ 1030 } else { 1031 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* DDMA */ 1032 } 1033 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_SAMPLE_RATE; 1034 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_SAMPLE_LAYOUT; 1035 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_WORD_LEN; 1036 val &= ~SUNXI_HDMI_ADMA_CTRL_DATA_SEL; 1037 HDMI_WRITE(sc, SUNXI_HDMI_ADMA_CTRL_REG, val); 1038 1039 /* Audio format control */ 1040 val = HDMI_READ(sc, SUNXI_HDMI_AUD_FMT_REG); 1041 val &= ~SUNXI_HDMI_AUD_FMT_SRC_SEL; 1042 val &= ~SUNXI_HDMI_AUD_FMT_SEL; 1043 val &= ~SUNXI_HDMI_AUD_FMT_DSD_FMT; 1044 val &= ~SUNXI_HDMI_AUD_FMT_LAYOUT; 1045 val &= ~SUNXI_HDMI_AUD_FMT_SRC_CH_CFG; 1046 val |= __SHIFTIN(1, SUNXI_HDMI_AUD_FMT_SRC_CH_CFG); 1047 HDMI_WRITE(sc, SUNXI_HDMI_AUD_FMT_REG, val); 1048 1049 /* PCM control (channel map) */ 1050 HDMI_WRITE(sc, SUNXI_HDMI_AUD_PCM_CTRL_REG, 0x76543210); 1051 1052 /* Clock setup */ 1053 n = 6144; /* 48 kHz */ 1054 cts = ((mode->dot_clock * 10) * (n / 128)) / 480; 1055 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts); 1056 HDMI_WRITE(sc, SUNXI_HDMI_AUD_N_REG, n); 1057 1058 /* Audio PCM channel status 0 */ 1059 val = __SHIFTIN(SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_48, 1060 SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ); 1061 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS0_REG, val); 1062 1063 /* Audio PCM channel status 1 */ 1064 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG); 1065 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_CGMS_A; 1066 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_ORIGINAL_FS; 1067 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN; 1068 val |= __SHIFTIN(5, SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN); 1069 val |= SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN_MAX; 1070 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG, val); 1071 1072 /* Re-enable */ 1073 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1074 val |= SUNXI_HDMI_AUD_CTRL_EN; 1075 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val); 1076 1077 #if defined(SUNXI_HDMI_DEBUG) 1078 sunxi_hdmi_dump_regs(); 1079 #endif 1080 } 1081 1082 static void 1083 sunxi_hdmi_hpd(struct sunxi_hdmi_softc *sc) 1084 { 1085 uint32_t hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG); 1086 bool con = !!(hpd & SUNXI_HDMI_HPD_HOTPLUG_DET); 1087 1088 KASSERT(mutex_owned(&sc->sc_pwr_lock)); 1089 if (sc->sc_display_connected == con) 1090 return; 1091 1092 if (con) { 1093 device_printf(sc->sc_dev, "display connected\n"); 1094 sc->sc_pwr_refcount = 1; 1095 sunxi_hdmi_read_edid(sc); 1096 } else { 1097 device_printf(sc->sc_dev, "display disconnected\n"); 1098 sc->sc_pwr_refcount = 0; 1099 sunxi_hdmi_video_enable(sc, false); 1100 fdt_endpoint_enable(sc->sc_in_ep, false); 1101 sunxi_tcon1_set_videomode( 1102 fdt_endpoint_device(sc->sc_in_rep), NULL); 1103 } 1104 1105 sc->sc_display_connected = con; 1106 } 1107 1108 static void 1109 sunxi_hdmi_thread(void *priv) 1110 { 1111 struct sunxi_hdmi_softc *sc = priv; 1112 1113 for (;;) { 1114 mutex_enter(&sc->sc_pwr_lock); 1115 sunxi_hdmi_hpd(sc); 1116 mutex_exit(&sc->sc_pwr_lock); 1117 kpause("hdmihotplug", false, mstohz(1000), NULL); 1118 } 1119 } 1120 1121 static int 1122 sunxi_hdmi_poweron(struct sunxi_hdmi_softc *sc, bool enable) 1123 { 1124 int error = 0; 1125 KASSERT(mutex_owned(&sc->sc_pwr_lock)); 1126 if (!sc->sc_display_connected) 1127 return EOPNOTSUPP; 1128 if (enable) { 1129 KASSERT(sc->sc_pwr_refcount >= 0); 1130 if (sc->sc_pwr_refcount == 0) { 1131 error = fdt_endpoint_enable(sc->sc_in_ep, true); 1132 if (error) 1133 return error; 1134 sunxi_hdmi_video_enable(sc, true); 1135 } 1136 sc->sc_pwr_refcount++; 1137 } else { 1138 sc->sc_pwr_refcount--; 1139 KASSERT(sc->sc_pwr_refcount >= 0); 1140 if (sc->sc_pwr_refcount == 0) { 1141 sunxi_hdmi_video_enable(sc, false); 1142 error = fdt_endpoint_enable(sc->sc_in_ep, false); 1143 } 1144 } 1145 return error; 1146 } 1147 #if 0 1148 static int 1149 sunxi_hdmi_intr(void *priv) 1150 { 1151 struct sunxi_hdmi_softc *sc = priv; 1152 uint32_t intsts; 1153 1154 intsts = HDMI_READ(sc, SUNXI_HDMI_INT_STATUS_REG); 1155 if (!(intsts & 0x73)) 1156 return 0; 1157 1158 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, intsts); 1159 1160 device_printf(sc->sc_dev, "INT_STATUS %08X\n", intsts); 1161 1162 return 1; 1163 } 1164 #endif 1165 1166 #if 0 /* XXX audio */ 1167 void 1168 sunxi_hdmi_get_info(struct sunxi_hdmi_info *info) 1169 { 1170 struct sunxi_hdmi_softc *sc; 1171 device_t dev; 1172 1173 memset(info, 0, sizeof(*info)); 1174 1175 dev = device_find_by_driver_unit("sunxihdmi", 0); 1176 if (dev == NULL) { 1177 info->display_connected = false; 1178 return; 1179 } 1180 sc = device_private(dev); 1181 1182 info->display_connected = sc->sc_display_connected; 1183 if (info->display_connected) { 1184 strlcpy(info->display_vendor, sc->sc_display_vendor, 1185 sizeof(info->display_vendor)); 1186 strlcpy(info->display_product, sc->sc_display_product, 1187 sizeof(info->display_product)); 1188 info->display_hdmimode = 1189 sc->sc_current_display_mode == DISPLAY_MODE_HDMI; 1190 } 1191 } 1192 #endif 1193 1194 #if defined(SUNXI_HDMI_DEBUG) 1195 void 1196 sunxi_hdmi_dump_regs(void) 1197 { 1198 static const struct { 1199 const char *name; 1200 uint16_t reg; 1201 } regs[] = { 1202 { "CTRL", SUNXI_HDMI_CTRL_REG }, 1203 { "INT_STATUS", SUNXI_HDMI_INT_STATUS_REG }, 1204 { "VID_CTRL", SUNXI_HDMI_VID_CTRL_REG }, 1205 { "VID_TIMING_0", SUNXI_HDMI_VID_TIMING_0_REG }, 1206 { "VID_TIMING_1", SUNXI_HDMI_VID_TIMING_1_REG }, 1207 { "VID_TIMING_2", SUNXI_HDMI_VID_TIMING_2_REG }, 1208 { "VID_TIMING_3", SUNXI_HDMI_VID_TIMING_3_REG }, 1209 { "VID_TIMING_4", SUNXI_HDMI_VID_TIMING_4_REG }, 1210 { "PAD_CTRL0", SUNXI_HDMI_PAD_CTRL0_REG }, 1211 { "PAD_CTRL1", SUNXI_HDMI_PAD_CTRL1_REG }, 1212 { "PLL_CTRL", SUNXI_HDMI_PLL_CTRL_REG }, 1213 { "PLL_DBG0", SUNXI_HDMI_PLL_DBG0_REG }, 1214 { "PLL_DBG1", SUNXI_HDMI_PLL_DBG1_REG }, 1215 }; 1216 struct sunxi_hdmi_softc *sc; 1217 device_t dev; 1218 1219 dev = device_find_by_driver_unit("sunxihdmi", 0); 1220 if (dev == NULL) 1221 return; 1222 sc = device_private(dev); 1223 1224 for (int i = 0; i < __arraycount(regs); i++) { 1225 printf("%s: 0x%08x\n", regs[i].name, 1226 HDMI_READ(sc, regs[i].reg)); 1227 } 1228 } 1229 #endif 1230