1 /* $NetBSD: sunxi_hdmi.c,v 1.4 2018/06/01 17:18:44 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_hdmi.c,v 1.4 2018/06/01 17:18:44 bouyer Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/proc.h> 41 #include <sys/mutex.h> 42 #include <sys/kthread.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_port.h> 46 47 #include <dev/i2c/i2cvar.h> 48 #include <dev/i2c/ddcvar.h> 49 #include <dev/i2c/ddcreg.h> 50 #include <dev/videomode/videomode.h> 51 #include <dev/videomode/edidvar.h> 52 53 #include <arm/sunxi/sunxi_hdmireg.h> 54 #include <arm/sunxi/sunxi_display.h> 55 56 enum sunxi_hdmi_type { 57 HDMI_A10 = 1, 58 HDMI_A31, 59 }; 60 61 struct sunxi_hdmi_softc { 62 device_t sc_dev; 63 int sc_phandle; 64 enum sunxi_hdmi_type sc_type; 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 struct clk *sc_clk_ahb; 68 struct clk *sc_clk_mod; 69 struct clk *sc_clk_pll0; 70 struct clk *sc_clk_pll1; 71 void *sc_ih; 72 lwp_t *sc_thread; 73 74 struct i2c_controller sc_ic; 75 kmutex_t sc_ic_lock; 76 77 bool sc_display_connected; 78 char sc_display_vendor[16]; 79 char sc_display_product[16]; 80 81 u_int sc_display_mode; 82 u_int sc_current_display_mode; 83 #define DISPLAY_MODE_AUTO 0 84 #define DISPLAY_MODE_HDMI 1 85 #define DISPLAY_MODE_DVI 2 86 87 kmutex_t sc_pwr_lock; 88 int sc_pwr_refcount; /* reference who needs HDMI */ 89 90 uint32_t sc_ver; 91 unsigned int sc_i2c_blklen; 92 93 struct fdt_device_ports sc_ports; 94 struct fdt_endpoint *sc_in_ep; 95 struct fdt_endpoint *sc_in_rep; 96 struct fdt_endpoint *sc_out_ep; 97 }; 98 99 #define HDMI_READ(sc, reg) \ 100 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 101 #define HDMI_WRITE(sc, reg, val) \ 102 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)); 103 104 #define HDMI_1_3_P(sc) ((sc)->sc_ver == 0x00010003) 105 #define HDMI_1_4_P(sc) ((sc)->sc_ver == 0x00010004) 106 107 static const struct of_compat_data compat_data[] = { 108 {"allwinner,sun4i-a10-hdmi", HDMI_A10}, 109 {"allwinner,sun7i-a20-hdmi", HDMI_A10}, 110 {NULL} 111 }; 112 113 static int sunxi_hdmi_match(device_t, cfdata_t, void *); 114 static void sunxi_hdmi_attach(device_t, device_t, void *); 115 static void sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *); 116 static int sunxi_hdmi_i2c_acquire_bus(void *, int); 117 static void sunxi_hdmi_i2c_release_bus(void *, int); 118 static int sunxi_hdmi_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 119 size_t, void *, size_t, int); 120 static int sunxi_hdmi_i2c_xfer(void *, i2c_addr_t, uint8_t, uint8_t, 121 size_t, int, int); 122 static int sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *, int); 123 124 static int sunxi_hdmi_ep_activate(device_t, struct fdt_endpoint *, bool); 125 static int sunxi_hdmi_ep_enable(device_t, struct fdt_endpoint *, bool); 126 static void sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *); 127 static void sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *); 128 static int sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *, uint8_t *, 129 uint8_t); 130 static u_int sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *, 131 const struct edid_info *); 132 static void sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *, bool); 133 static void sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *, 134 const struct videomode *, u_int); 135 static void sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *, 136 const struct videomode *, u_int); 137 static void sunxi_hdmi_hpd(struct sunxi_hdmi_softc *); 138 static void sunxi_hdmi_thread(void *); 139 static int sunxi_hdmi_poweron(struct sunxi_hdmi_softc *, bool); 140 #if 0 141 static int sunxi_hdmi_intr(void *); 142 #endif 143 144 #if defined(DDB) 145 void sunxi_hdmi_dump_regs(void); 146 #endif 147 148 CFATTACH_DECL_NEW(sunxi_hdmi, sizeof(struct sunxi_hdmi_softc), 149 sunxi_hdmi_match, sunxi_hdmi_attach, NULL, NULL); 150 151 static int 152 sunxi_hdmi_match(device_t parent, cfdata_t cf, void *aux) 153 { 154 struct fdt_attach_args * const faa = aux; 155 156 return of_match_compat_data(faa->faa_phandle, compat_data); 157 } 158 159 static void 160 sunxi_hdmi_attach(device_t parent, device_t self, void *aux) 161 { 162 struct sunxi_hdmi_softc *sc = device_private(self); 163 struct fdt_attach_args * const faa = aux; 164 const int phandle = faa->faa_phandle; 165 bus_addr_t addr; 166 bus_size_t size; 167 uint32_t ver; 168 169 sc->sc_dev = self; 170 sc->sc_phandle = phandle; 171 sc->sc_bst = faa->faa_bst; 172 173 sc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 174 175 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 176 aprint_error(": couldn't get registers\n"); 177 } 178 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 179 aprint_error(": couldn't map registers\n"); 180 return; 181 } 182 183 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 184 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod"); 185 sc->sc_clk_pll0 = fdtbus_clock_get(phandle, "pll-0"); 186 sc->sc_clk_pll1 = fdtbus_clock_get(phandle, "pll-1"); 187 188 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mod == NULL 189 || sc->sc_clk_pll0 == NULL || sc->sc_clk_pll1 == NULL) { 190 aprint_error(": couldn't get clocks\n"); 191 aprint_debug_dev(self, "clk ahb %s mod %s pll-0 %s pll-1 %s\n", 192 sc->sc_clk_ahb == NULL ? "missing" : "present", 193 sc->sc_clk_mod == NULL ? "missing" : "present", 194 sc->sc_clk_pll0 == NULL ? "missing" : "present", 195 sc->sc_clk_pll1 == NULL ? "missing" : "present"); 196 return; 197 } 198 199 if (clk_enable(sc->sc_clk_ahb) != 0) { 200 aprint_error(": couldn't enable ahb clock\n"); 201 return; 202 } 203 ver = HDMI_READ(sc, SUNXI_HDMI_VERSION_ID_REG); 204 205 const int vmaj = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_H); 206 const int vmin = __SHIFTOUT(ver, SUNXI_HDMI_VERSION_ID_L); 207 208 aprint_naive("\n"); 209 aprint_normal(": HDMI %d.%d\n", vmaj, vmin); 210 211 sc->sc_ver = ver; 212 sc->sc_i2c_blklen = 16; 213 214 sc->sc_ports.dp_ep_activate = sunxi_hdmi_ep_activate; 215 sc->sc_ports.dp_ep_enable = sunxi_hdmi_ep_enable; 216 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 217 218 mutex_init(&sc->sc_pwr_lock, MUTEX_DEFAULT, IPL_NONE); 219 sunxi_hdmi_i2c_init(sc); 220 } 221 222 void 223 sunxi_hdmi_doreset(void) 224 { 225 device_t dev; 226 struct sunxi_hdmi_softc *sc; 227 int error; 228 229 for (int i = 0;;i++) { 230 dev = device_find_by_driver_unit("sunxihdmi", i); 231 if (dev == NULL) 232 return; 233 sc = device_private(dev); 234 235 error = clk_disable(sc->sc_clk_mod); 236 if (error) { 237 aprint_error_dev(dev, ": couldn't disable mod clock\n"); 238 return; 239 } 240 241 #if defined(SUNXI_HDMI_DEBUG) 242 sunxi_hdmi_dump_regs(); 243 #endif 244 245 /* 246 * reset device, in case it has been setup by firmware in an 247 * incompatible way 248 */ 249 for (int j = 0; j <= 0x500; j += 4) { 250 HDMI_WRITE(sc, j, 0); 251 } 252 253 if (clk_disable(sc->sc_clk_ahb) != 0) { 254 aprint_error_dev(dev, ": couldn't disable ahb clock\n"); 255 return; 256 } 257 } 258 } 259 260 static void 261 sunxi_hdmi_i2c_init(struct sunxi_hdmi_softc *sc) 262 { 263 struct i2c_controller *ic = &sc->sc_ic; 264 265 mutex_init(&sc->sc_ic_lock, MUTEX_DEFAULT, IPL_NONE); 266 267 ic->ic_cookie = sc; 268 ic->ic_acquire_bus = sunxi_hdmi_i2c_acquire_bus; 269 ic->ic_release_bus = sunxi_hdmi_i2c_release_bus; 270 ic->ic_exec = sunxi_hdmi_i2c_exec; 271 } 272 273 static int 274 sunxi_hdmi_i2c_acquire_bus(void *priv, int flags) 275 { 276 struct sunxi_hdmi_softc *sc = priv; 277 278 if (flags & I2C_F_POLL) { 279 if (!mutex_tryenter(&sc->sc_ic_lock)) 280 return EBUSY; 281 } else { 282 mutex_enter(&sc->sc_ic_lock); 283 } 284 285 return 0; 286 } 287 288 static void 289 sunxi_hdmi_i2c_release_bus(void *priv, int flags) 290 { 291 struct sunxi_hdmi_softc *sc = priv; 292 293 mutex_exit(&sc->sc_ic_lock); 294 } 295 296 static int 297 sunxi_hdmi_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 298 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 299 { 300 struct sunxi_hdmi_softc *sc = priv; 301 uint8_t *pbuf; 302 uint8_t block; 303 int resid; 304 off_t off; 305 int err; 306 307 KASSERT(mutex_owned(&sc->sc_ic_lock)); 308 KASSERT(op == I2C_OP_READ_WITH_STOP); 309 KASSERT(addr == DDC_ADDR); 310 KASSERT(cmdlen > 0); 311 KASSERT(buf != NULL); 312 313 err = sunxi_hdmi_i2c_reset(sc, flags); 314 if (err) 315 goto done; 316 317 block = *(const uint8_t *)cmdbuf; 318 off = (block & 1) ? 128 : 0; 319 320 pbuf = buf; 321 resid = len; 322 while (resid > 0) { 323 size_t blklen = min(resid, sc->sc_i2c_blklen); 324 325 err = sunxi_hdmi_i2c_xfer(sc, addr, block >> 1, off, blklen, 326 SUNXI_HDMI_DDC_COMMAND_ACCESS_CMD_EOREAD, flags); 327 if (err) 328 goto done; 329 330 if (HDMI_1_3_P(sc)) { 331 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh, 332 SUNXI_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen); 333 } else { 334 bus_space_read_multi_1(sc->sc_bst, sc->sc_bsh, 335 SUNXI_A31_HDMI_DDC_FIFO_ACCESS_REG, pbuf, blklen); 336 } 337 338 #ifdef SUNXI_HDMI_DEBUG 339 printf("off=%d:", (int)off); 340 for (int i = 0; i < blklen; i++) 341 printf(" %02x", pbuf[i]); 342 printf("\n"); 343 #endif 344 345 pbuf += blklen; 346 off += blklen; 347 resid -= blklen; 348 } 349 350 done: 351 return err; 352 } 353 354 static int 355 sunxi_hdmi_i2c_xfer_1_3(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 356 size_t len, int type, int flags) 357 { 358 struct sunxi_hdmi_softc *sc = priv; 359 uint32_t val; 360 int retry; 361 362 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 363 val &= ~SUNXI_HDMI_DDC_CTRL_FIFO_DIR; 364 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val); 365 366 val |= __SHIFTIN(block, SUNXI_HDMI_DDC_SLAVE_ADDR_0); 367 val |= __SHIFTIN(0x60, SUNXI_HDMI_DDC_SLAVE_ADDR_1); 368 val |= __SHIFTIN(reg, SUNXI_HDMI_DDC_SLAVE_ADDR_2); 369 val |= __SHIFTIN(addr, SUNXI_HDMI_DDC_SLAVE_ADDR_3); 370 HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val); 371 372 val = HDMI_READ(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG); 373 val |= SUNXI_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR; 374 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val); 375 376 HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len); 377 378 HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type); 379 380 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 381 val |= SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START; 382 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val); 383 384 retry = 1000; 385 while (--retry > 0) { 386 val = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 387 if ((val & SUNXI_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0) 388 break; 389 delay(1000); 390 } 391 if (retry == 0) 392 return ETIMEDOUT; 393 394 val = HDMI_READ(sc, SUNXI_HDMI_DDC_INT_STATUS_REG); 395 if ((val & SUNXI_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE) == 0) { 396 device_printf(sc->sc_dev, "xfer failed, status=%08x\n", val); 397 return EIO; 398 } 399 400 return 0; 401 } 402 403 static int 404 sunxi_hdmi_i2c_xfer_1_4(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 405 size_t len, int type, int flags) 406 { 407 struct sunxi_hdmi_softc *sc = priv; 408 uint32_t val; 409 int retry; 410 411 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG); 412 val |= SUNXI_A31_HDMI_DDC_FIFO_CTRL_RST; 413 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val); 414 415 val = __SHIFTIN(block, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_SEG_PTR); 416 val |= __SHIFTIN(0x60, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DDC_CMD); 417 val |= __SHIFTIN(reg, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_OFF_ADR); 418 val |= __SHIFTIN(addr, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_DEV_ADR); 419 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val); 420 421 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_COMMAND_REG, 422 __SHIFTIN(len, SUNXI_A31_HDMI_DDC_COMMAND_DTC) | 423 __SHIFTIN(type, SUNXI_A31_HDMI_DDC_COMMAND_CMD)); 424 425 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG); 426 val |= SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START; 427 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, val); 428 429 retry = 1000; 430 while (--retry > 0) { 431 val = HDMI_READ(sc, SUNXI_A31_HDMI_DDC_CTRL_REG); 432 if ((val & SUNXI_A31_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0) 433 break; 434 if (cold) 435 delay(1000); 436 else 437 kpause("hdmiddc", false, mstohz(10), &sc->sc_ic_lock); 438 } 439 if (retry == 0) 440 return ETIMEDOUT; 441 442 return 0; 443 } 444 445 static int 446 sunxi_hdmi_i2c_xfer(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg, 447 size_t len, int type, int flags) 448 { 449 struct sunxi_hdmi_softc *sc = priv; 450 int rv; 451 452 if (HDMI_1_3_P(sc)) { 453 rv = sunxi_hdmi_i2c_xfer_1_3(priv, addr, block, reg, len, 454 type, flags); 455 } else { 456 rv = sunxi_hdmi_i2c_xfer_1_4(priv, addr, block, reg, len, 457 type, flags); 458 } 459 460 return rv; 461 } 462 463 static int 464 sunxi_hdmi_i2c_reset(struct sunxi_hdmi_softc *sc, int flags) 465 { 466 uint32_t hpd, ctrl; 467 468 hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG); 469 if ((hpd & SUNXI_HDMI_HPD_HOTPLUG_DET) == 0) { 470 device_printf(sc->sc_dev, "no device detected\n"); 471 return ENODEV; /* no device plugged in */ 472 } 473 474 if (HDMI_1_3_P(sc)) { 475 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, 0); 476 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, 477 SUNXI_HDMI_DDC_CTRL_EN | SUNXI_HDMI_DDC_CTRL_SW_RST); 478 479 delay(1000); 480 481 ctrl = HDMI_READ(sc, SUNXI_HDMI_DDC_CTRL_REG); 482 if (ctrl & SUNXI_HDMI_DDC_CTRL_SW_RST) { 483 device_printf(sc->sc_dev, "reset failed (1.3)\n"); 484 return EBUSY; 485 } 486 487 /* N=5,M=1 */ 488 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CLOCK_REG, 489 __SHIFTIN(5, SUNXI_HDMI_DDC_CLOCK_N) | 490 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_M)); 491 492 HDMI_WRITE(sc, SUNXI_HDMI_DDC_DBG_REG, 0x300); 493 } else { 494 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, 495 SUNXI_A31_HDMI_DDC_CTRL_SW_RST); 496 497 /* N=1,M=12 */ 498 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CLOCK_REG, 499 __SHIFTIN(1, SUNXI_HDMI_DDC_CLOCK_N) | 500 __SHIFTIN(12, SUNXI_HDMI_DDC_CLOCK_M)); 501 502 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, 503 SUNXI_A31_HDMI_DDC_CTRL_SDA_PAD_EN | 504 SUNXI_A31_HDMI_DDC_CTRL_SCL_PAD_EN | 505 SUNXI_A31_HDMI_DDC_CTRL_EN); 506 } 507 508 return 0; 509 } 510 511 static int 512 sunxi_hdmi_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 513 { 514 struct sunxi_hdmi_softc *sc = device_private(dev); 515 struct fdt_endpoint *in_ep, *out_ep; 516 int error; 517 518 /* our input is activated by tcon, we activate our output */ 519 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 520 panic("sunxi_hdmi_ep_activate: port %d", 521 fdt_endpoint_port_index(ep)); 522 } 523 524 if (!activate) 525 return EOPNOTSUPP; 526 527 /* check that out other input is not active */ 528 switch (fdt_endpoint_index(ep)) { 529 case 0: 530 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 531 SUNXI_PORT_INPUT, 1); 532 break; 533 case 1: 534 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 535 SUNXI_PORT_INPUT, 0); 536 break; 537 default: 538 in_ep = NULL; 539 panic("sunxi_hdmi_ep_activate: input index %d", 540 fdt_endpoint_index(ep)); 541 } 542 if (in_ep != NULL) { 543 if (fdt_endpoint_is_active(in_ep)) 544 return EBUSY; 545 } 546 /* only one output */ 547 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 548 SUNXI_PORT_OUTPUT, 0); 549 if (out_ep == NULL) { 550 aprint_error_dev(dev, "no output endpoint\n"); 551 return ENODEV; 552 } 553 error = fdt_endpoint_activate(out_ep, activate); 554 if (error == 0) { 555 sc->sc_in_ep = ep; 556 sc->sc_in_rep = fdt_endpoint_remote(ep); 557 sc->sc_out_ep = out_ep; 558 sunxi_hdmi_do_enable(sc); 559 return 0; 560 } 561 return error; 562 } 563 564 static int 565 sunxi_hdmi_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 566 { 567 struct sunxi_hdmi_softc *sc = device_private(dev); 568 int error; 569 570 if (fdt_endpoint_port_index(ep) == SUNXI_PORT_INPUT) { 571 KASSERT(ep == sc->sc_in_ep); 572 if (sc->sc_thread == NULL) { 573 if (enable) { 574 delay(50000); 575 mutex_enter(&sc->sc_pwr_lock); 576 sunxi_hdmi_hpd(sc); 577 mutex_exit(&sc->sc_pwr_lock); 578 kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL, 579 sunxi_hdmi_thread, sc, &sc->sc_thread, "%s", 580 device_xname(dev)); 581 } 582 return 0; 583 } else { 584 mutex_enter(&sc->sc_pwr_lock); 585 error = sunxi_hdmi_poweron(sc, enable); 586 mutex_exit(&sc->sc_pwr_lock); 587 return error; 588 } 589 } 590 panic("sunxi_hdmi_ep_enable"); 591 } 592 593 static void 594 sunxi_hdmi_do_enable(struct sunxi_hdmi_softc *sc) 595 { 596 /* complete attach */ 597 struct clk *clk; 598 int error; 599 uint32_t dbg0_reg; 600 601 if (clk_enable(sc->sc_clk_ahb) != 0) { 602 aprint_error_dev(sc->sc_dev, "couldn't enable ahb clock\n"); 603 return; 604 } 605 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 606 switch(fdt_endpoint_index(sc->sc_in_ep)) { 607 case 0: 608 clk = sc->sc_clk_pll0; 609 dbg0_reg = (0<<21); 610 break; 611 case 1: 612 clk = sc->sc_clk_pll1; 613 dbg0_reg = (1<<21); 614 break; 615 default: 616 panic("sunxi_hdmi pll"); 617 } 618 error = clk_set_rate(clk, 270000000); 619 if (error) { 620 clk = clk_get_parent(clk); 621 /* probably because this is pllx2 */ 622 error = clk_set_rate(clk, 270000000); 623 } 624 if (error) { 625 aprint_error_dev(sc->sc_dev, ": couldn't init pll clock\n"); 626 return; 627 } 628 error = clk_set_parent(sc->sc_clk_mod, clk); 629 if (error) { 630 aprint_error_dev(sc->sc_dev, ": couldn't set mod clock parent\n"); 631 return; 632 } 633 error = clk_enable(sc->sc_clk_mod); 634 if (error) { 635 aprint_error_dev(sc->sc_dev, ": couldn't enable mod clock\n"); 636 return; 637 } 638 delay(1000); 639 640 HDMI_WRITE(sc, SUNXI_HDMI_CTRL_REG, SUNXI_HDMI_CTRL_MODULE_EN); 641 delay(1000); 642 if (sc->sc_type == HDMI_A10) { 643 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0xfe800000); 644 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x00d8c830); 645 } else if (sc->sc_type == HDMI_A31) { 646 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0x7e80000f); 647 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x01ded030); 648 } 649 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, dbg0_reg); 650 delay(1000); 651 } 652 653 static int 654 sunxi_hdmi_read_edid_block(struct sunxi_hdmi_softc *sc, uint8_t *data, 655 uint8_t block) 656 { 657 i2c_tag_t tag = &sc->sc_ic; 658 uint8_t wbuf[2]; 659 int error; 660 661 if ((error = iic_acquire_bus(tag, I2C_F_POLL)) != 0) 662 return error; 663 664 wbuf[0] = block; /* start address */ 665 666 if ((error = iic_exec(tag, I2C_OP_READ_WITH_STOP, DDC_ADDR, wbuf, 1, 667 data, 128, I2C_F_POLL)) != 0) { 668 iic_release_bus(tag, I2C_F_POLL); 669 return error; 670 } 671 iic_release_bus(tag, I2C_F_POLL); 672 673 return 0; 674 } 675 676 static void 677 sunxi_hdmi_read_edid(struct sunxi_hdmi_softc *sc) 678 { 679 const struct videomode *mode; 680 char edid[128]; 681 struct edid_info ei; 682 int retry = 4; 683 u_int display_mode; 684 685 memset(edid, 0, sizeof(edid)); 686 memset(&ei, 0, sizeof(ei)); 687 688 while (--retry > 0) { 689 if (!sunxi_hdmi_read_edid_block(sc, edid, 0)) 690 break; 691 } 692 if (retry == 0) { 693 device_printf(sc->sc_dev, "failed to read EDID\n"); 694 } else { 695 if (edid_parse(edid, &ei) != 0) { 696 device_printf(sc->sc_dev, "failed to parse EDID\n"); 697 } 698 #ifdef SUNXI_HDMI_DEBUG 699 else { 700 edid_print(&ei); 701 } 702 #endif 703 } 704 705 if (sc->sc_display_mode == DISPLAY_MODE_AUTO) 706 display_mode = sunxi_hdmi_get_display_mode(sc, &ei); 707 else 708 display_mode = sc->sc_display_mode; 709 710 const char *forced = sc->sc_display_mode == DISPLAY_MODE_AUTO ? 711 "auto-detected" : "forced"; 712 device_printf(sc->sc_dev, "%s mode (%s)\n", 713 display_mode == DISPLAY_MODE_HDMI ? "HDMI" : "DVI", forced); 714 715 strlcpy(sc->sc_display_vendor, ei.edid_vendorname, 716 sizeof(sc->sc_display_vendor)); 717 strlcpy(sc->sc_display_product, ei.edid_productname, 718 sizeof(sc->sc_display_product)); 719 sc->sc_current_display_mode = display_mode; 720 721 mode = ei.edid_preferred_mode; 722 if (mode == NULL) 723 mode = pick_mode_by_ref(640, 480, 60); 724 725 if (mode != NULL) { 726 sunxi_hdmi_video_enable(sc, false); 727 fdt_endpoint_enable(sc->sc_in_ep, false); 728 delay(20000); 729 730 sunxi_tcon1_set_videomode( 731 fdt_endpoint_device(sc->sc_in_rep), mode); 732 sunxi_hdmi_set_videomode(sc, mode, display_mode); 733 sunxi_hdmi_set_audiomode(sc, mode, display_mode); 734 fdt_endpoint_enable(sc->sc_in_ep, true); 735 delay(20000); 736 sunxi_hdmi_video_enable(sc, true); 737 } 738 } 739 740 static u_int 741 sunxi_hdmi_get_display_mode(struct sunxi_hdmi_softc *sc, 742 const struct edid_info *ei) 743 { 744 char edid[128]; 745 bool found_hdmi = false; 746 unsigned int n, p; 747 748 /* 749 * Scan through extension blocks, looking for a CEA-861-D v3 750 * block. If an HDMI Vendor-Specific Data Block (HDMI VSDB) is 751 * found in that, assume HDMI mode. 752 */ 753 for (n = 1; n <= MIN(ei->edid_ext_block_count, 4); n++) { 754 if (sunxi_hdmi_read_edid_block(sc, edid, n)) { 755 #ifdef SUNXI_HDMI_DEBUG 756 device_printf(sc->sc_dev, 757 "Failed to read EDID block %d\n", n); 758 #endif 759 break; 760 } 761 762 #ifdef SUNXI_HDMI_DEBUG 763 device_printf(sc->sc_dev, "EDID block #%d:\n", n); 764 #endif 765 766 const uint8_t tag = edid[0]; 767 const uint8_t rev = edid[1]; 768 const uint8_t off = edid[2]; 769 770 #ifdef SUNXI_HDMI_DEBUG 771 device_printf(sc->sc_dev, " Tag %d, Revision %d, Offset %d\n", 772 tag, rev, off); 773 device_printf(sc->sc_dev, " Flags: 0x%02x\n", edid[3]); 774 #endif 775 776 /* We are looking for a CEA-861-D tag (02h) with revision 3 */ 777 if (tag != 0x02 || rev != 3) 778 continue; 779 /* 780 * CEA data block collection starts at byte 4, so the 781 * DTD blocks must start after it. 782 */ 783 if (off <= 4) 784 continue; 785 786 /* Parse the CEA data blocks */ 787 for (p = 4; p < off;) { 788 const uint8_t btag = (edid[p] >> 5) & 0x7; 789 const uint8_t blen = edid[p] & 0x1f; 790 791 #ifdef SUNXI_HDMI_DEBUG 792 device_printf(sc->sc_dev, " CEA data block @ %d\n", p); 793 device_printf(sc->sc_dev, " Tag %d, Length %d\n", 794 btag, blen); 795 #endif 796 797 /* Make sure the length is sane */ 798 if (p + blen + 1 > off) 799 break; 800 /* Looking for a VSDB tag */ 801 if (btag != 3) 802 goto next_block; 803 /* HDMI VSDB is at least 5 bytes long */ 804 if (blen < 5) 805 goto next_block; 806 807 #ifdef SUNXI_HDMI_DEBUG 808 device_printf(sc->sc_dev, " ID: %02x%02x%02x\n", 809 edid[p + 1], edid[p + 2], edid[p + 3]); 810 #endif 811 812 /* HDMI 24-bit IEEE registration ID is 0x000C03 */ 813 if (memcmp(&edid[p + 1], "\x03\x0c\x00", 3) == 0) 814 found_hdmi = true; 815 816 next_block: 817 p += (1 + blen); 818 } 819 } 820 821 return found_hdmi ? DISPLAY_MODE_HDMI : DISPLAY_MODE_DVI; 822 } 823 824 static void 825 sunxi_hdmi_video_enable(struct sunxi_hdmi_softc *sc, bool enable) 826 { 827 uint32_t val; 828 829 fdt_endpoint_enable(sc->sc_out_ep, enable); 830 831 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG); 832 val &= ~SUNXI_HDMI_VID_CTRL_SRC_SEL; 833 #ifdef SUNXI_HDMI_CBGEN 834 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_CBGEN, 835 SUNXI_HDMI_VID_CTRL_SRC_SEL); 836 #else 837 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_SRC_SEL_RGB, 838 SUNXI_HDMI_VID_CTRL_SRC_SEL); 839 #endif 840 if (enable) { 841 val |= SUNXI_HDMI_VID_CTRL_VIDEO_EN; 842 } else { 843 val &= ~SUNXI_HDMI_VID_CTRL_VIDEO_EN; 844 } 845 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val); 846 847 #if defined(SUNXI_HDMI_DEBUG) 848 sunxi_hdmi_dump_regs(); 849 #endif 850 } 851 852 static void 853 sunxi_hdmi_set_videomode(struct sunxi_hdmi_softc *sc, 854 const struct videomode *mode, u_int display_mode) 855 { 856 uint32_t val; 857 const u_int dblscan_p = !!(mode->flags & VID_DBLSCAN); 858 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 859 const u_int phsync_p = !!(mode->flags & VID_PHSYNC); 860 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC); 861 const u_int hfp = mode->hsync_start - mode->hdisplay; 862 const u_int hspw = mode->hsync_end - mode->hsync_start; 863 const u_int hbp = mode->htotal - mode->hsync_start; 864 const u_int vfp = mode->vsync_start - mode->vdisplay; 865 const u_int vspw = mode->vsync_end - mode->vsync_start; 866 const u_int vbp = mode->vtotal - mode->vsync_start; 867 struct clk *clk_pll; 868 int parent_rate; 869 int best_div, best_dbl, best_diff; 870 int target_rate = mode->dot_clock * 1000; 871 872 #ifdef SUNXI_HDMI_DEBUG 873 device_printf(sc->sc_dev, 874 "dblscan %d, interlace %d, phsync %d, pvsync %d\n", 875 dblscan_p, interlace_p, phsync_p, pvsync_p); 876 device_printf(sc->sc_dev, "h: %u %u %u %u\n", 877 mode->hdisplay, hbp, hfp, hspw); 878 device_printf(sc->sc_dev, "v: %u %u %u %u\n", 879 mode->vdisplay, vbp, vfp, vspw); 880 #endif 881 882 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, 0xffffffff); 883 884 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 885 switch(fdt_endpoint_index(sc->sc_in_ep)) { 886 case 0: 887 clk_pll = sc->sc_clk_pll0; 888 break; 889 case 1: 890 clk_pll = sc->sc_clk_pll1; 891 break; 892 default: 893 panic("sunxi_hdmi pll"); 894 } 895 parent_rate = clk_get_rate(clk_pll); 896 KASSERT(parent_rate > 0); 897 best_div = best_dbl = 0; 898 best_diff = INT_MAX; 899 for (int d = 2; d > 0 && best_diff != 0; d--) { 900 for (int m = 1; m <= 16 && best_diff != 0; m++) { 901 int cur_rate = parent_rate / m / d; 902 int diff = abs(target_rate - cur_rate); 903 if (diff >= 0 && diff < best_diff) { 904 best_diff = diff; 905 best_div = m; 906 best_dbl = d; 907 } 908 } 909 } 910 911 #ifdef SUNXI_HDMI_DEBUG 912 device_printf(sc->sc_dev, "parent rate: %d\n", parent_rate); 913 device_printf(sc->sc_dev, "dot_clock: %d\n", mode->dot_clock); 914 device_printf(sc->sc_dev, "clkdiv: %d\n", best_div); 915 device_printf(sc->sc_dev, "clkdbl: %c\n", (best_dbl == 1) ? 'Y' : 'N'); 916 #endif 917 918 if (best_div == 0) { 919 device_printf(sc->sc_dev, "ERROR: TCON clk not configured\n"); 920 return; 921 } 922 923 uint32_t pll_ctrl, pad_ctrl0, pad_ctrl1; 924 if (HDMI_1_4_P(sc)) { 925 pad_ctrl0 = 0x7e8000ff; 926 pad_ctrl1 = 0x01ded030; 927 pll_ctrl = 0xba48a308; 928 pll_ctrl |= __SHIFTIN(best_div - 1, SUNXI_HDMI_PLL_CTRL_PREDIV); 929 } else { 930 pad_ctrl0 = 0xfe800000; 931 pad_ctrl1 = 0x00d8c830; 932 pll_ctrl = 0xfa4ef708; 933 pll_ctrl |= __SHIFTIN(best_div, SUNXI_HDMI_PLL_CTRL_PREDIV); 934 } 935 if (best_dbl == 2) 936 pad_ctrl1 |= 0x40; 937 938 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, pad_ctrl0); 939 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, pad_ctrl1); 940 HDMI_WRITE(sc, SUNXI_HDMI_PLL_CTRL_REG, pll_ctrl); 941 /* assume tcon0 uses pll3, tcon1 uses pll7 */ 942 switch(fdt_endpoint_index(sc->sc_in_ep)) { 943 case 0: 944 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (0<<21)); 945 break; 946 case 1: 947 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (1<<21)); 948 break; 949 default: 950 panic("sunxi_hdmi pll"); 951 } 952 953 val = HDMI_READ(sc, SUNXI_HDMI_VID_CTRL_REG); 954 val &= ~SUNXI_HDMI_VID_CTRL_HDMI_MODE; 955 if (display_mode == DISPLAY_MODE_DVI) { 956 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_DVI, 957 SUNXI_HDMI_VID_CTRL_HDMI_MODE); 958 } else { 959 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_HDMI_MODE_HDMI, 960 SUNXI_HDMI_VID_CTRL_HDMI_MODE); 961 } 962 val &= ~SUNXI_HDMI_VID_CTRL_REPEATER_SEL; 963 if (dblscan_p) { 964 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_REPEATER_SEL_2X, 965 SUNXI_HDMI_VID_CTRL_REPEATER_SEL); 966 } 967 val &= ~SUNXI_HDMI_VID_CTRL_OUTPUT_FMT; 968 if (interlace_p) { 969 val |= __SHIFTIN(SUNXI_HDMI_VID_CTRL_OUTPUT_FMT_INTERLACE, 970 SUNXI_HDMI_VID_CTRL_OUTPUT_FMT); 971 } 972 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val); 973 974 val = __SHIFTIN((mode->hdisplay << dblscan_p) - 1, 975 SUNXI_HDMI_VID_TIMING_0_ACT_H); 976 val |= __SHIFTIN(mode->vdisplay - 1, 977 SUNXI_HDMI_VID_TIMING_0_ACT_V); 978 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_0_REG, val); 979 980 val = __SHIFTIN((hbp << dblscan_p) - 1, 981 SUNXI_HDMI_VID_TIMING_1_HBP); 982 val |= __SHIFTIN(vbp - 1, 983 SUNXI_HDMI_VID_TIMING_1_VBP); 984 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_1_REG, val); 985 986 val = __SHIFTIN((hfp << dblscan_p) - 1, 987 SUNXI_HDMI_VID_TIMING_2_HFP); 988 val |= __SHIFTIN(vfp - 1, 989 SUNXI_HDMI_VID_TIMING_2_VFP); 990 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_2_REG, val); 991 992 val = __SHIFTIN((hspw << dblscan_p) - 1, 993 SUNXI_HDMI_VID_TIMING_3_HSPW); 994 val |= __SHIFTIN(vspw - 1, 995 SUNXI_HDMI_VID_TIMING_3_VSPW); 996 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_3_REG, val); 997 998 val = 0; 999 if (phsync_p) { 1000 val |= SUNXI_HDMI_VID_TIMING_4_HSYNC_ACTIVE_SEL; 1001 } 1002 if (pvsync_p) { 1003 val |= SUNXI_HDMI_VID_TIMING_4_VSYNC_ACTIVE_SEL; 1004 } 1005 val |= __SHIFTIN(SUNXI_HDMI_VID_TIMING_4_TX_CLOCK_NORMAL, 1006 SUNXI_HDMI_VID_TIMING_4_TX_CLOCK); 1007 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_4_REG, val); 1008 1009 /* Packet control */ 1010 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT0_REG, 0); 1011 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT1_REG, 0); 1012 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL0_REG, 0x00005321); 1013 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL1_REG, 0x0000000f); 1014 } 1015 1016 static void 1017 sunxi_hdmi_set_audiomode(struct sunxi_hdmi_softc *sc, 1018 const struct videomode *mode, u_int display_mode) 1019 { 1020 uint32_t cts, n, val; 1021 1022 /* 1023 * Before changing audio parameters, disable and reset the 1024 * audio module. Wait for the soft reset bit to clear before 1025 * configuring the audio parameters. 1026 */ 1027 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1028 val &= ~SUNXI_HDMI_AUD_CTRL_EN; 1029 val |= SUNXI_HDMI_AUD_CTRL_RST; 1030 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val); 1031 do { 1032 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1033 } while (val & SUNXI_HDMI_AUD_CTRL_RST); 1034 1035 /* No audio support in DVI mode */ 1036 if (display_mode != DISPLAY_MODE_HDMI) { 1037 return; 1038 } 1039 1040 /* DMA & FIFO control */ 1041 val = HDMI_READ(sc, SUNXI_HDMI_ADMA_CTRL_REG); 1042 if (sc->sc_type == HDMI_A31) { 1043 val |= SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* NDMA */ 1044 } else { 1045 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_MODE; /* DDMA */ 1046 } 1047 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_DMA_SAMPLE_RATE; 1048 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_SAMPLE_LAYOUT; 1049 val &= ~SUNXI_HDMI_ADMA_CTRL_SRC_WORD_LEN; 1050 val &= ~SUNXI_HDMI_ADMA_CTRL_DATA_SEL; 1051 HDMI_WRITE(sc, SUNXI_HDMI_ADMA_CTRL_REG, val); 1052 1053 /* Audio format control */ 1054 val = HDMI_READ(sc, SUNXI_HDMI_AUD_FMT_REG); 1055 val &= ~SUNXI_HDMI_AUD_FMT_SRC_SEL; 1056 val &= ~SUNXI_HDMI_AUD_FMT_SEL; 1057 val &= ~SUNXI_HDMI_AUD_FMT_DSD_FMT; 1058 val &= ~SUNXI_HDMI_AUD_FMT_LAYOUT; 1059 val &= ~SUNXI_HDMI_AUD_FMT_SRC_CH_CFG; 1060 val |= __SHIFTIN(1, SUNXI_HDMI_AUD_FMT_SRC_CH_CFG); 1061 HDMI_WRITE(sc, SUNXI_HDMI_AUD_FMT_REG, val); 1062 1063 /* PCM control (channel map) */ 1064 HDMI_WRITE(sc, SUNXI_HDMI_AUD_PCM_CTRL_REG, 0x76543210); 1065 1066 /* Clock setup */ 1067 n = 6144; /* 48 kHz */ 1068 cts = ((mode->dot_clock * 10) * (n / 128)) / 480; 1069 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts); 1070 HDMI_WRITE(sc, SUNXI_HDMI_AUD_N_REG, n); 1071 1072 /* Audio PCM channel status 0 */ 1073 val = __SHIFTIN(SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ_48, 1074 SUNXI_HDMI_AUD_CH_STATUS0_FS_FREQ); 1075 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS0_REG, val); 1076 1077 /* Audio PCM channel status 1 */ 1078 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG); 1079 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_CGMS_A; 1080 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_ORIGINAL_FS; 1081 val &= ~SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN; 1082 val |= __SHIFTIN(5, SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN); 1083 val |= SUNXI_HDMI_AUD_CH_STATUS1_WORD_LEN_MAX; 1084 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG, val); 1085 1086 /* Re-enable */ 1087 val = HDMI_READ(sc, SUNXI_HDMI_AUD_CTRL_REG); 1088 val |= SUNXI_HDMI_AUD_CTRL_EN; 1089 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val); 1090 1091 #if defined(SUNXI_HDMI_DEBUG) 1092 sunxi_hdmi_dump_regs(); 1093 #endif 1094 } 1095 1096 static void 1097 sunxi_hdmi_hpd(struct sunxi_hdmi_softc *sc) 1098 { 1099 uint32_t hpd = HDMI_READ(sc, SUNXI_HDMI_HPD_REG); 1100 bool con = !!(hpd & SUNXI_HDMI_HPD_HOTPLUG_DET); 1101 1102 KASSERT(mutex_owned(&sc->sc_pwr_lock)); 1103 if (sc->sc_display_connected == con) 1104 return; 1105 1106 if (con) { 1107 device_printf(sc->sc_dev, "display connected\n"); 1108 sc->sc_pwr_refcount = 1; 1109 sunxi_hdmi_read_edid(sc); 1110 } else { 1111 device_printf(sc->sc_dev, "display disconnected\n"); 1112 sc->sc_pwr_refcount = 0; 1113 sunxi_hdmi_video_enable(sc, false); 1114 fdt_endpoint_enable(sc->sc_in_ep, false); 1115 sunxi_tcon1_set_videomode( 1116 fdt_endpoint_device(sc->sc_in_rep), NULL); 1117 } 1118 1119 sc->sc_display_connected = con; 1120 } 1121 1122 static void 1123 sunxi_hdmi_thread(void *priv) 1124 { 1125 struct sunxi_hdmi_softc *sc = priv; 1126 1127 for (;;) { 1128 mutex_enter(&sc->sc_pwr_lock); 1129 sunxi_hdmi_hpd(sc); 1130 mutex_exit(&sc->sc_pwr_lock); 1131 kpause("hdmihotplug", false, mstohz(1000), NULL); 1132 } 1133 } 1134 1135 static int 1136 sunxi_hdmi_poweron(struct sunxi_hdmi_softc *sc, bool enable) 1137 { 1138 int error = 0; 1139 KASSERT(mutex_owned(&sc->sc_pwr_lock)); 1140 if (!sc->sc_display_connected) 1141 return EOPNOTSUPP; 1142 if (enable) { 1143 KASSERT(sc->sc_pwr_refcount >= 0); 1144 if (sc->sc_pwr_refcount == 0) { 1145 error = fdt_endpoint_enable(sc->sc_in_ep, true); 1146 if (error) 1147 return error; 1148 sunxi_hdmi_video_enable(sc, true); 1149 } 1150 sc->sc_pwr_refcount++; 1151 } else { 1152 sc->sc_pwr_refcount--; 1153 KASSERT(sc->sc_pwr_refcount >= 0); 1154 if (sc->sc_pwr_refcount == 0) { 1155 sunxi_hdmi_video_enable(sc, false); 1156 error = fdt_endpoint_enable(sc->sc_in_ep, false); 1157 } 1158 } 1159 return error; 1160 } 1161 #if 0 1162 static int 1163 sunxi_hdmi_intr(void *priv) 1164 { 1165 struct sunxi_hdmi_softc *sc = priv; 1166 uint32_t intsts; 1167 1168 intsts = HDMI_READ(sc, SUNXI_HDMI_INT_STATUS_REG); 1169 if (!(intsts & 0x73)) 1170 return 0; 1171 1172 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, intsts); 1173 1174 device_printf(sc->sc_dev, "INT_STATUS %08X\n", intsts); 1175 1176 return 1; 1177 } 1178 #endif 1179 1180 #if 0 /* XXX audio */ 1181 void 1182 sunxi_hdmi_get_info(struct sunxi_hdmi_info *info) 1183 { 1184 struct sunxi_hdmi_softc *sc; 1185 device_t dev; 1186 1187 memset(info, 0, sizeof(*info)); 1188 1189 dev = device_find_by_driver_unit("sunxihdmi", 0); 1190 if (dev == NULL) { 1191 info->display_connected = false; 1192 return; 1193 } 1194 sc = device_private(dev); 1195 1196 info->display_connected = sc->sc_display_connected; 1197 if (info->display_connected) { 1198 strlcpy(info->display_vendor, sc->sc_display_vendor, 1199 sizeof(info->display_vendor)); 1200 strlcpy(info->display_product, sc->sc_display_product, 1201 sizeof(info->display_product)); 1202 info->display_hdmimode = 1203 sc->sc_current_display_mode == DISPLAY_MODE_HDMI; 1204 } 1205 } 1206 #endif 1207 1208 #if defined(SUNXI_HDMI_DEBUG) 1209 void 1210 sunxi_hdmi_dump_regs(void) 1211 { 1212 static const struct { 1213 const char *name; 1214 uint16_t reg; 1215 } regs[] = { 1216 { "CTRL", SUNXI_HDMI_CTRL_REG }, 1217 { "INT_STATUS", SUNXI_HDMI_INT_STATUS_REG }, 1218 { "VID_CTRL", SUNXI_HDMI_VID_CTRL_REG }, 1219 { "VID_TIMING_0", SUNXI_HDMI_VID_TIMING_0_REG }, 1220 { "VID_TIMING_1", SUNXI_HDMI_VID_TIMING_1_REG }, 1221 { "VID_TIMING_2", SUNXI_HDMI_VID_TIMING_2_REG }, 1222 { "VID_TIMING_3", SUNXI_HDMI_VID_TIMING_3_REG }, 1223 { "VID_TIMING_4", SUNXI_HDMI_VID_TIMING_4_REG }, 1224 { "PAD_CTRL0", SUNXI_HDMI_PAD_CTRL0_REG }, 1225 { "PAD_CTRL1", SUNXI_HDMI_PAD_CTRL1_REG }, 1226 { "PLL_CTRL", SUNXI_HDMI_PLL_CTRL_REG }, 1227 { "PLL_DBG0", SUNXI_HDMI_PLL_DBG0_REG }, 1228 { "PLL_DBG1", SUNXI_HDMI_PLL_DBG1_REG }, 1229 }; 1230 struct sunxi_hdmi_softc *sc; 1231 device_t dev; 1232 1233 dev = device_find_by_driver_unit("sunxihdmi", 0); 1234 if (dev == NULL) 1235 return; 1236 sc = device_private(dev); 1237 1238 for (int i = 0; i < __arraycount(regs); i++) { 1239 printf("%s: 0x%08x\n", regs[i].name, 1240 HDMI_READ(sc, regs[i].reg)); 1241 } 1242 } 1243 #endif 1244