1 /* $NetBSD: sunxi_gpio.c,v 1.25 2019/05/30 18:19:36 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.25 2019/05/30 18:19:36 tnn Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 #include <sys/bitops.h> 43 #include <sys/lwp.h> 44 45 #include <dev/fdt/fdtvar.h> 46 #include <dev/gpio/gpiovar.h> 47 48 #include <arm/sunxi/sunxi_gpio.h> 49 50 #define SUNXI_GPIO_MAX_EINT_BANK 5 51 #define SUNXI_GPIO_MAX_EINT 32 52 53 #define SUNXI_GPIO_MAX_BANK 26 54 55 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 56 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 57 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7 << (((pin) % 8) * 4)) 58 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 59 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 60 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 61 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 62 #define SUNXI_GPIO_PULL_DISABLE 0 63 #define SUNXI_GPIO_PULL_UP 1 64 #define SUNXI_GPIO_PULL_DOWN 2 65 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 66 #define SUNXI_GPIO_INT_CFG(bank, eint) (0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8))) 67 #define SUNXI_GPIO_INT_MODEMASK(eint) (0xf << (((eint) % 8) * 4)) 68 #define SUNXI_GPIO_INT_MODE_POS_EDGE 0x0 69 #define SUNXI_GPIO_INT_MODE_NEG_EDGE 0x1 70 #define SUNXI_GPIO_INT_MODE_HIGH_LEVEL 0x2 71 #define SUNXI_GPIO_INT_MODE_LOW_LEVEL 0x3 72 #define SUNXI_GPIO_INT_MODE_DOUBLE_EDGE 0x4 73 #define SUNXI_GPIO_INT_CTL(bank) (0x210 + 0x20 * (bank)) 74 #define SUNXI_GPIO_INT_STATUS(bank) (0x214 + 0x20 * (bank)) 75 #define SUNXI_GPIO_GRP_CONFIG(bank) (0x300 + 0x4 * (bank)) 76 #define SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK 0xf 77 78 static const struct of_compat_data compat_data[] = { 79 #ifdef SOC_SUN4I_A10 80 { "allwinner,sun4i-a10-pinctrl", (uintptr_t)&sun4i_a10_padconf }, 81 #endif 82 #ifdef SOC_SUN5I_A13 83 { "allwinner,sun5i-a13-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 84 { "nextthing,gr8-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 85 #endif 86 #ifdef SOC_SUN6I_A31 87 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 88 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 89 #endif 90 #ifdef SOC_SUN7I_A20 91 { "allwinner,sun7i-a20-pinctrl", (uintptr_t)&sun7i_a20_padconf }, 92 #endif 93 #ifdef SOC_SUN8I_A83T 94 { "allwinner,sun8i-a83t-pinctrl", (uintptr_t)&sun8i_a83t_padconf }, 95 { "allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&sun8i_a83t_r_padconf }, 96 #endif 97 #ifdef SOC_SUN8I_H3 98 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 99 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 100 #endif 101 #ifdef SOC_SUN9I_A80 102 { "allwinner,sun9i-a80-pinctrl", (uintptr_t)&sun9i_a80_padconf }, 103 { "allwinner,sun9i-a80-r-pinctrl", (uintptr_t)&sun9i_a80_r_padconf }, 104 #endif 105 #ifdef SOC_SUN50I_A64 106 { "allwinner,sun50i-a64-pinctrl", (uintptr_t)&sun50i_a64_padconf }, 107 { "allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&sun50i_a64_r_padconf }, 108 #endif 109 #ifdef SOC_SUN50I_H5 110 { "allwinner,sun50i-h5-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 111 { "allwinner,sun50i-h5-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 112 #endif 113 #ifdef SOC_SUN50I_H6 114 { "allwinner,sun50i-h6-pinctrl", (uintptr_t)&sun50i_h6_padconf }, 115 { "allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&sun50i_h6_r_padconf }, 116 #endif 117 { NULL } 118 }; 119 120 struct sunxi_gpio_eint { 121 int (*eint_func)(void *); 122 void *eint_arg; 123 bool eint_mpsafe; 124 int eint_bank; 125 int eint_num; 126 }; 127 128 struct sunxi_gpio_softc { 129 device_t sc_dev; 130 bus_space_tag_t sc_bst; 131 bus_space_handle_t sc_bsh; 132 int sc_phandle; 133 const struct sunxi_gpio_padconf *sc_padconf; 134 kmutex_t sc_lock; 135 136 struct gpio_chipset_tag sc_gp; 137 gpio_pin_t *sc_pins; 138 device_t sc_gpiodev; 139 140 struct fdtbus_regulator *sc_pin_supply[SUNXI_GPIO_MAX_BANK]; 141 142 u_int sc_eint_bank_max; 143 144 void *sc_ih; 145 struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT_BANK][SUNXI_GPIO_MAX_EINT]; 146 }; 147 148 struct sunxi_gpio_pin { 149 struct sunxi_gpio_softc *pin_sc; 150 const struct sunxi_gpio_pins *pin_def; 151 int pin_flags; 152 bool pin_actlo; 153 }; 154 155 #define GPIO_READ(sc, reg) \ 156 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 157 #define GPIO_WRITE(sc, reg, val) \ 158 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 159 160 static int sunxi_gpio_match(device_t, cfdata_t, void *); 161 static void sunxi_gpio_attach(device_t, device_t, void *); 162 163 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 164 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 165 166 static const struct sunxi_gpio_pins * 167 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 168 { 169 const struct sunxi_gpio_pins *pin_def; 170 u_int n; 171 172 for (n = 0; n < sc->sc_padconf->npins; n++) { 173 pin_def = &sc->sc_padconf->pins[n]; 174 if (pin_def->port == port && pin_def->pin == pin) 175 return pin_def; 176 } 177 178 return NULL; 179 } 180 181 static const struct sunxi_gpio_pins * 182 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 183 { 184 const struct sunxi_gpio_pins *pin_def; 185 u_int n; 186 187 for (n = 0; n < sc->sc_padconf->npins; n++) { 188 pin_def = &sc->sc_padconf->pins[n]; 189 if (strcmp(pin_def->name, name) == 0) 190 return pin_def; 191 } 192 193 return NULL; 194 } 195 196 static int 197 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 198 const struct sunxi_gpio_pins *pin_def, const char *func) 199 { 200 uint32_t cfg; 201 u_int n; 202 203 KASSERT(mutex_owned(&sc->sc_lock)); 204 205 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 206 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 207 208 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 209 if (pin_def->functions[n] == NULL) 210 continue; 211 if (strcmp(pin_def->functions[n], func) == 0) { 212 cfg = GPIO_READ(sc, cfg_reg); 213 cfg &= ~cfg_mask; 214 cfg |= __SHIFTIN(n, cfg_mask); 215 #ifdef SUNXI_GPIO_DEBUG 216 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 217 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 218 #endif 219 GPIO_WRITE(sc, cfg_reg, cfg); 220 return 0; 221 } 222 } 223 224 /* Function not found */ 225 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 226 func, pin_def->port + 'A', pin_def->pin); 227 228 return ENXIO; 229 } 230 231 static int 232 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 233 const struct sunxi_gpio_pins *pin_def, int flags) 234 { 235 uint32_t pull; 236 237 KASSERT(mutex_owned(&sc->sc_lock)); 238 239 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 240 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 241 242 pull = GPIO_READ(sc, pull_reg); 243 pull &= ~pull_mask; 244 if (flags & GPIO_PIN_PULLUP) 245 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 246 else if (flags & GPIO_PIN_PULLDOWN) 247 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 248 else 249 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 250 #ifdef SUNXI_GPIO_DEBUG 251 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 252 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 253 #endif 254 GPIO_WRITE(sc, pull_reg, pull); 255 256 return 0; 257 } 258 259 static int 260 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 261 const struct sunxi_gpio_pins *pin_def, int drive_strength) 262 { 263 uint32_t drv; 264 265 KASSERT(mutex_owned(&sc->sc_lock)); 266 267 if (drive_strength < 10 || drive_strength > 40) 268 return EINVAL; 269 270 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 271 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 272 273 drv = GPIO_READ(sc, drv_reg); 274 drv &= ~drv_mask; 275 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 276 #ifdef SUNXI_GPIO_DEBUG 277 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 278 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 279 #endif 280 GPIO_WRITE(sc, drv_reg, drv); 281 282 return 0; 283 } 284 285 static int 286 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 287 int flags) 288 { 289 KASSERT(mutex_owned(&sc->sc_lock)); 290 291 if (flags & GPIO_PIN_INPUT) 292 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 293 if (flags & GPIO_PIN_OUTPUT) 294 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 295 296 return EINVAL; 297 } 298 299 static void * 300 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 301 { 302 struct sunxi_gpio_softc * const sc = device_private(dev); 303 const struct sunxi_gpio_pins *pin_def; 304 struct sunxi_gpio_pin *gpin; 305 const u_int *gpio = data; 306 int error; 307 308 if (len != 16) 309 return NULL; 310 311 const uint8_t port = be32toh(gpio[1]) & 0xff; 312 const uint8_t pin = be32toh(gpio[2]) & 0xff; 313 const bool actlo = be32toh(gpio[3]) & 1; 314 315 pin_def = sunxi_gpio_lookup(sc, port, pin); 316 if (pin_def == NULL) 317 return NULL; 318 319 mutex_enter(&sc->sc_lock); 320 error = sunxi_gpio_ctl(sc, pin_def, flags); 321 mutex_exit(&sc->sc_lock); 322 323 if (error != 0) 324 return NULL; 325 326 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 327 gpin->pin_sc = sc; 328 gpin->pin_def = pin_def; 329 gpin->pin_flags = flags; 330 gpin->pin_actlo = actlo; 331 332 return gpin; 333 } 334 335 static void 336 sunxi_gpio_release(device_t dev, void *priv) 337 { 338 struct sunxi_gpio_softc * const sc = device_private(dev); 339 struct sunxi_gpio_pin *pin = priv; 340 341 mutex_enter(&sc->sc_lock); 342 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 343 mutex_exit(&sc->sc_lock); 344 345 kmem_free(pin, sizeof(*pin)); 346 } 347 348 static int 349 sunxi_gpio_read(device_t dev, void *priv, bool raw) 350 { 351 struct sunxi_gpio_softc * const sc = device_private(dev); 352 struct sunxi_gpio_pin *pin = priv; 353 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 354 uint32_t data; 355 int val; 356 357 KASSERT(sc == pin->pin_sc); 358 359 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 360 const uint32_t data_mask = __BIT(pin_def->pin); 361 362 /* No lock required for reads */ 363 data = GPIO_READ(sc, data_reg); 364 val = __SHIFTOUT(data, data_mask); 365 if (!raw && pin->pin_actlo) 366 val = !val; 367 368 #ifdef SUNXI_GPIO_DEBUG 369 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 370 pin_def->port + 'A', pin_def->pin, data, 371 __SHIFTOUT(val, data_mask), val); 372 #endif 373 374 return val; 375 } 376 377 static void 378 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 379 { 380 struct sunxi_gpio_softc * const sc = device_private(dev); 381 struct sunxi_gpio_pin *pin = priv; 382 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 383 uint32_t data; 384 385 KASSERT(sc == pin->pin_sc); 386 387 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 388 const uint32_t data_mask = __BIT(pin_def->pin); 389 390 if (!raw && pin->pin_actlo) 391 val = !val; 392 393 mutex_enter(&sc->sc_lock); 394 data = GPIO_READ(sc, data_reg); 395 data &= ~data_mask; 396 data |= __SHIFTIN(val, data_mask); 397 #ifdef SUNXI_GPIO_DEBUG 398 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 399 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 400 #endif 401 GPIO_WRITE(sc, data_reg, data); 402 mutex_exit(&sc->sc_lock); 403 } 404 405 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 406 .acquire = sunxi_gpio_acquire, 407 .release = sunxi_gpio_release, 408 .read = sunxi_gpio_read, 409 .write = sunxi_gpio_write, 410 }; 411 412 static int 413 sunxi_gpio_intr(void *priv) 414 { 415 struct sunxi_gpio_softc * const sc = priv; 416 struct sunxi_gpio_eint *eint; 417 uint32_t status, bit; 418 u_int bank; 419 int ret = 0; 420 421 for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) { 422 status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank)); 423 if (status == 0) 424 continue; 425 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status); 426 427 while ((bit = ffs32(status)) != 0) { 428 status &= ~__BIT(bit - 1); 429 eint = &sc->sc_eint[bank][bit - 1]; 430 if (eint->eint_func == NULL) 431 continue; 432 if (!eint->eint_mpsafe) 433 KERNEL_LOCK(1, curlwp); 434 ret |= eint->eint_func(eint->eint_arg); 435 if (!eint->eint_mpsafe) 436 KERNEL_UNLOCK_ONE(curlwp); 437 } 438 } 439 440 return ret; 441 } 442 443 static void * 444 sunxi_intr_enable(struct sunxi_gpio_softc *sc, 445 const struct sunxi_gpio_pins *pin_def, u_int mode, bool mpsafe, 446 int (*func)(void *), void *arg) 447 { 448 uint32_t val; 449 struct sunxi_gpio_eint *eint; 450 451 if (pin_def->functions[pin_def->eint_func] == NULL || 452 strcmp(pin_def->functions[pin_def->eint_func], "irq") != 0) 453 return NULL; 454 455 KASSERT(pin_def->eint_num < SUNXI_GPIO_MAX_EINT); 456 457 mutex_enter(&sc->sc_lock); 458 459 eint = &sc->sc_eint[pin_def->eint_bank][pin_def->eint_num]; 460 if (eint->eint_func != NULL) { 461 mutex_exit(&sc->sc_lock); 462 return NULL; /* in use */ 463 } 464 465 /* Set function */ 466 if (sunxi_gpio_setfunc(sc, pin_def, "irq") != 0) { 467 mutex_exit(&sc->sc_lock); 468 return NULL; 469 } 470 471 eint->eint_func = func; 472 eint->eint_arg = arg; 473 eint->eint_mpsafe = mpsafe; 474 eint->eint_bank = pin_def->eint_bank; 475 eint->eint_num = pin_def->eint_num; 476 477 /* Configure eint mode */ 478 val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num)); 479 val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num); 480 val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num)); 481 GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val); 482 483 /* Enable eint */ 484 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 485 val |= __BIT(eint->eint_num); 486 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 487 488 mutex_exit(&sc->sc_lock); 489 490 return eint; 491 } 492 493 static void 494 sunxi_intr_disable(struct sunxi_gpio_softc *sc, struct sunxi_gpio_eint *eint) 495 { 496 uint32_t val; 497 498 KASSERT(eint->eint_func != NULL); 499 500 mutex_enter(&sc->sc_lock); 501 502 /* Disable eint */ 503 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 504 val &= ~__BIT(eint->eint_num); 505 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 506 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num)); 507 508 eint->eint_func = NULL; 509 eint->eint_arg = NULL; 510 eint->eint_mpsafe = false; 511 512 mutex_exit(&sc->sc_lock); 513 } 514 515 static void * 516 sunxi_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 517 int (*func)(void *), void *arg) 518 { 519 struct sunxi_gpio_softc * const sc = device_private(dev); 520 bool mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 521 const struct sunxi_gpio_pins *pin_def; 522 u_int mode; 523 524 if (ipl != IPL_VM) { 525 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 526 __func__, ipl, IPL_VM); 527 return NULL; 528 } 529 530 /* 1st cell is the bank */ 531 /* 2nd cell is the pin */ 532 /* 3rd cell is flags */ 533 const u_int port = be32toh(specifier[0]); 534 const u_int pin = be32toh(specifier[1]); 535 const u_int type = be32toh(specifier[2]) & 0xf; 536 537 switch (type) { 538 case FDT_INTR_TYPE_POS_EDGE: 539 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 540 break; 541 case FDT_INTR_TYPE_NEG_EDGE: 542 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 543 break; 544 case FDT_INTR_TYPE_DOUBLE_EDGE: 545 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 546 break; 547 case FDT_INTR_TYPE_HIGH_LEVEL: 548 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 549 break; 550 case FDT_INTR_TYPE_LOW_LEVEL: 551 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 552 break; 553 default: 554 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 555 __func__, type); 556 return NULL; 557 } 558 559 pin_def = sunxi_gpio_lookup(sc, port, pin); 560 if (pin_def == NULL) 561 return NULL; 562 563 return sunxi_intr_enable(sc, pin_def, mode, mpsafe, func, arg); 564 } 565 566 static void 567 sunxi_fdt_intr_disestablish(device_t dev, void *ih) 568 { 569 struct sunxi_gpio_softc * const sc = device_private(dev); 570 struct sunxi_gpio_eint * const eint = ih; 571 572 sunxi_intr_disable(sc, eint); 573 } 574 575 static bool 576 sunxi_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 577 { 578 struct sunxi_gpio_softc * const sc = device_private(dev); 579 const struct sunxi_gpio_pins *pin_def; 580 581 /* 1st cell is the bank */ 582 /* 2nd cell is the pin */ 583 /* 3rd cell is flags */ 584 if (!specifier) 585 return false; 586 const u_int port = be32toh(specifier[0]); 587 const u_int pin = be32toh(specifier[1]); 588 589 pin_def = sunxi_gpio_lookup(sc, port, pin); 590 if (pin_def == NULL) 591 return false; 592 593 snprintf(buf, buflen, "GPIO %s", pin_def->name); 594 595 return true; 596 } 597 598 static struct fdtbus_interrupt_controller_func sunxi_gpio_intrfuncs = { 599 .establish = sunxi_fdt_intr_establish, 600 .disestablish = sunxi_fdt_intr_disestablish, 601 .intrstr = sunxi_fdt_intrstr, 602 }; 603 604 static void * 605 sunxi_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 606 int (*func)(void *), void *arg) 607 { 608 struct sunxi_gpio_softc * const sc = vsc; 609 bool mpsafe = (irqmode & GPIO_INTR_MPSAFE) != 0; 610 int type = irqmode & GPIO_INTR_MODE_MASK; 611 const struct sunxi_gpio_pins *pin_def; 612 u_int mode; 613 614 switch (type) { 615 case GPIO_INTR_POS_EDGE: 616 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 617 break; 618 case GPIO_INTR_NEG_EDGE: 619 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 620 break; 621 case GPIO_INTR_DOUBLE_EDGE: 622 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 623 break; 624 case GPIO_INTR_HIGH_LEVEL: 625 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 626 break; 627 case GPIO_INTR_LOW_LEVEL: 628 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 629 break; 630 default: 631 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 632 __func__, type); 633 return NULL; 634 } 635 636 if (pin < 0 || pin >= sc->sc_padconf->npins) 637 return NULL; 638 pin_def = &sc->sc_padconf->pins[pin]; 639 640 return sunxi_intr_enable(sc, pin_def, mode, mpsafe, func, arg); 641 } 642 643 static void 644 sunxi_gpio_intr_disestablish(void *vsc, void *ih) 645 { 646 struct sunxi_gpio_softc * const sc = vsc; 647 struct sunxi_gpio_eint * const eint = ih; 648 649 sunxi_intr_disable(sc, eint); 650 } 651 652 static bool 653 sunxi_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 654 { 655 struct sunxi_gpio_softc * const sc = vsc; 656 const struct sunxi_gpio_pins *pin_def; 657 658 if (pin < 0 || pin >= sc->sc_padconf->npins) 659 return NULL; 660 pin_def = &sc->sc_padconf->pins[pin]; 661 662 snprintf(buf, buflen, "GPIO %s", pin_def->name); 663 664 return true; 665 } 666 667 static const char * 668 sunxi_pinctrl_parse_function(int phandle) 669 { 670 const char *function; 671 672 function = fdtbus_pinctrl_parse_function(phandle); 673 if (function != NULL) 674 return function; 675 676 return fdtbus_get_string(phandle, "allwinner,function"); 677 } 678 679 static const char * 680 sunxi_pinctrl_parse_pins(int phandle, int *pins_len) 681 { 682 const char *pins; 683 int len; 684 685 pins = fdtbus_pinctrl_parse_pins(phandle, pins_len); 686 if (pins != NULL) 687 return pins; 688 689 len = OF_getproplen(phandle, "allwinner,pins"); 690 if (len > 0) { 691 *pins_len = len; 692 return fdtbus_get_prop(phandle, "allwinner,pins", pins_len); 693 } 694 695 return NULL; 696 } 697 698 static int 699 sunxi_pinctrl_parse_bias(int phandle) 700 { 701 u_int pull; 702 int bias; 703 704 bias = fdtbus_pinctrl_parse_bias(phandle, NULL); 705 if (bias != -1) 706 return bias; 707 708 if (of_getprop_uint32(phandle, "allwinner,pull", &pull) == 0) { 709 switch (pull) { 710 case 0: 711 bias = 0; 712 break; 713 case 1: 714 bias = GPIO_PIN_PULLUP; 715 break; 716 case 2: 717 bias = GPIO_PIN_PULLDOWN; 718 break; 719 } 720 } 721 722 return bias; 723 } 724 725 static int 726 sunxi_pinctrl_parse_drive_strength(int phandle) 727 { 728 int val; 729 730 val = fdtbus_pinctrl_parse_drive_strength(phandle); 731 if (val != -1) 732 return val; 733 734 if (of_getprop_uint32(phandle, "allwinner,drive", &val) == 0) 735 return (val + 1) * 10; 736 737 return -1; 738 } 739 740 static void 741 sunxi_pinctrl_enable_regulator(struct sunxi_gpio_softc *sc, 742 const struct sunxi_gpio_pins *pin_def) 743 { 744 char supply_prop[16]; 745 uint32_t val; 746 u_int uvol; 747 int error; 748 749 const char c = tolower(pin_def->name[1]); 750 if (c < 'a' || c > 'z') 751 return; 752 const int index = c - 'a'; 753 754 if (sc->sc_pin_supply[index] != NULL) { 755 /* Already enabled */ 756 return; 757 } 758 759 snprintf(supply_prop, sizeof(supply_prop), "vcc-p%c-supply", c); 760 sc->sc_pin_supply[index] = fdtbus_regulator_acquire(sc->sc_phandle, supply_prop); 761 if (sc->sc_pin_supply[index] == NULL) 762 return; 763 764 aprint_debug_dev(sc->sc_dev, "enable \"%s\"\n", supply_prop); 765 error = fdtbus_regulator_enable(sc->sc_pin_supply[index]); 766 if (error != 0) 767 aprint_error_dev(sc->sc_dev, "failed to enable %s: %d\n", supply_prop, error); 768 769 if (sc->sc_padconf->has_io_bias_config) { 770 error = fdtbus_regulator_get_voltage(sc->sc_pin_supply[index], &uvol); 771 if (error != 0) { 772 aprint_error_dev(sc->sc_dev, "failed to get %s voltage: %d\n", 773 supply_prop, error); 774 uvol = 0; 775 } 776 if (uvol != 0) { 777 if (uvol <= 1800000) 778 val = 0x0; /* 1.8V */ 779 else if (uvol <= 2500000) 780 val = 0x6; /* 2.5V */ 781 else if (uvol <= 2800000) 782 val = 0x9; /* 2.8V */ 783 else if (uvol <= 3000000) 784 val = 0xa; /* 3.0V */ 785 else 786 val = 0xd; /* 3.3V */ 787 788 aprint_debug_dev(sc->sc_dev, "set io bias config for port %d to 0x%x\n", 789 pin_def->port, val); 790 val = GPIO_READ(sc, SUNXI_GPIO_GRP_CONFIG(pin_def->port)); 791 val &= ~SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK; 792 val |= __SHIFTIN(val, SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK); 793 GPIO_WRITE(sc, SUNXI_GPIO_GRP_CONFIG(pin_def->port), val); 794 } 795 } 796 } 797 798 static int 799 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 800 { 801 struct sunxi_gpio_softc * const sc = device_private(dev); 802 const struct sunxi_gpio_pins *pin_def; 803 int pins_len; 804 805 if (len != 4) 806 return -1; 807 808 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 809 810 /* 811 * Required: pins, function 812 * Optional: bias, drive strength 813 */ 814 815 const char *function = sunxi_pinctrl_parse_function(phandle); 816 if (function == NULL) 817 return -1; 818 const char *pins = sunxi_pinctrl_parse_pins(phandle, &pins_len); 819 if (pins == NULL) 820 return -1; 821 822 const int bias = sunxi_pinctrl_parse_bias(phandle); 823 const int drive_strength = sunxi_pinctrl_parse_drive_strength(phandle); 824 825 mutex_enter(&sc->sc_lock); 826 827 for (; pins_len > 0; 828 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 829 pin_def = sunxi_gpio_lookup_byname(sc, pins); 830 if (pin_def == NULL) { 831 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 832 continue; 833 } 834 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 835 continue; 836 837 if (bias != -1) 838 sunxi_gpio_setpull(sc, pin_def, bias); 839 840 if (drive_strength != -1) 841 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 842 843 sunxi_pinctrl_enable_regulator(sc, pin_def); 844 } 845 846 mutex_exit(&sc->sc_lock); 847 848 return 0; 849 } 850 851 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 852 .set_config = sunxi_pinctrl_set_config, 853 }; 854 855 static int 856 sunxi_gpio_pin_read(void *priv, int pin) 857 { 858 struct sunxi_gpio_softc * const sc = priv; 859 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 860 uint32_t data; 861 int val; 862 863 KASSERT(pin < sc->sc_padconf->npins); 864 865 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 866 const uint32_t data_mask = __BIT(pin_def->pin); 867 868 /* No lock required for reads */ 869 data = GPIO_READ(sc, data_reg); 870 val = __SHIFTOUT(data, data_mask); 871 872 return val; 873 } 874 875 static void 876 sunxi_gpio_pin_write(void *priv, int pin, int val) 877 { 878 struct sunxi_gpio_softc * const sc = priv; 879 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 880 uint32_t data; 881 882 KASSERT(pin < sc->sc_padconf->npins); 883 884 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 885 const uint32_t data_mask = __BIT(pin_def->pin); 886 887 mutex_enter(&sc->sc_lock); 888 data = GPIO_READ(sc, data_reg); 889 if (val) 890 data |= data_mask; 891 else 892 data &= ~data_mask; 893 GPIO_WRITE(sc, data_reg, data); 894 mutex_exit(&sc->sc_lock); 895 } 896 897 static void 898 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 899 { 900 struct sunxi_gpio_softc * const sc = priv; 901 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 902 903 KASSERT(pin < sc->sc_padconf->npins); 904 905 mutex_enter(&sc->sc_lock); 906 sunxi_gpio_ctl(sc, pin_def, flags); 907 sunxi_gpio_setpull(sc, pin_def, flags); 908 mutex_exit(&sc->sc_lock); 909 } 910 911 static void 912 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 913 { 914 const struct sunxi_gpio_pins *pin_def; 915 struct gpio_chipset_tag *gp = &sc->sc_gp; 916 struct gpiobus_attach_args gba; 917 u_int pin; 918 919 gp->gp_cookie = sc; 920 gp->gp_pin_read = sunxi_gpio_pin_read; 921 gp->gp_pin_write = sunxi_gpio_pin_write; 922 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 923 gp->gp_intr_establish = sunxi_gpio_intr_establish; 924 gp->gp_intr_disestablish = sunxi_gpio_intr_disestablish; 925 gp->gp_intr_str = sunxi_gpio_intrstr; 926 927 const u_int npins = sc->sc_padconf->npins; 928 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 929 930 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 931 pin_def = &sc->sc_padconf->pins[pin]; 932 sc->sc_pins[pin].pin_num = pin; 933 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 934 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 935 if (pin_def->functions[pin_def->eint_func] != NULL && 936 strcmp(pin_def->functions[pin_def->eint_func], "irq") == 0) { 937 sc->sc_pins[pin].pin_intrcaps = 938 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 939 GPIO_INTR_HIGH_LEVEL | GPIO_INTR_LOW_LEVEL | 940 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_MPSAFE; 941 } 942 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 943 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 944 sizeof(sc->sc_pins[pin].pin_defname)); 945 } 946 947 memset(&gba, 0, sizeof(gba)); 948 gba.gba_gc = gp; 949 gba.gba_pins = sc->sc_pins; 950 gba.gba_npins = npins; 951 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 952 } 953 954 static int 955 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 956 { 957 struct fdt_attach_args * const faa = aux; 958 959 return of_match_compat_data(faa->faa_phandle, compat_data); 960 } 961 962 static void 963 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 964 { 965 struct sunxi_gpio_softc * const sc = device_private(self); 966 struct fdt_attach_args * const faa = aux; 967 const int phandle = faa->faa_phandle; 968 char intrstr[128]; 969 struct fdtbus_reset *rst; 970 struct clk *clk; 971 bus_addr_t addr; 972 bus_size_t size; 973 int child; 974 975 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 976 aprint_error(": couldn't get registers\n"); 977 return; 978 } 979 980 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 981 if (clk_enable(clk) != 0) { 982 aprint_error(": couldn't enable clock\n"); 983 return; 984 } 985 986 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 987 if (fdtbus_reset_deassert(rst) != 0) { 988 aprint_error(": couldn't de-assert reset\n"); 989 return; 990 } 991 992 sc->sc_dev = self; 993 sc->sc_phandle = phandle; 994 sc->sc_bst = faa->faa_bst; 995 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 996 aprint_error(": couldn't map registers\n"); 997 return; 998 } 999 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 1000 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 1001 1002 aprint_naive("\n"); 1003 aprint_normal(": PIO\n"); 1004 1005 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 1006 1007 for (child = OF_child(phandle); child; child = OF_peer(child)) { 1008 bool is_valid = 1009 (of_hasprop(child, "function") && of_hasprop(child, "pins")) || 1010 (of_hasprop(child, "allwinner,function") && of_hasprop(child, "allwinner,pins")); 1011 if (!is_valid) 1012 continue; 1013 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 1014 } 1015 1016 fdtbus_pinctrl_configure(); 1017 1018 sunxi_gpio_attach_ports(sc); 1019 1020 /* Disable all external interrupts */ 1021 for (int i = 0; i < sc->sc_padconf->npins; i++) { 1022 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[i]; 1023 if (pin_def->eint_func == 0) 1024 continue; 1025 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num)); 1026 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num)); 1027 1028 if (sc->sc_eint_bank_max < pin_def->eint_bank) 1029 sc->sc_eint_bank_max = pin_def->eint_bank; 1030 } 1031 KASSERT(sc->sc_eint_bank_max < SUNXI_GPIO_MAX_EINT_BANK); 1032 1033 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1034 aprint_error_dev(self, "failed to decode interrupt\n"); 1035 return; 1036 } 1037 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 1038 sunxi_gpio_intr, sc); 1039 if (sc->sc_ih == NULL) { 1040 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1041 intrstr); 1042 return; 1043 } 1044 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1045 fdtbus_register_interrupt_controller(self, phandle, 1046 &sunxi_gpio_intrfuncs); 1047 } 1048