1 /* $NetBSD: sunxi_emac.c,v 1.16 2018/06/30 12:36:13 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.16 2018/06/30 12:36:13 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 #include <dev/fdt/syscon.h> 59 60 #include <arm/sunxi/sunxi_emac.h> 61 62 #ifdef NET_MPSAFE 63 #define EMAC_MPSAFE 1 64 #define CALLOUT_FLAGS CALLOUT_MPSAFE 65 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 66 #else 67 #define CALLOUT_FLAGS 0 68 #define FDT_INTR_FLAGS 0 69 #endif 70 71 #define EMAC_IFNAME "emac%d" 72 73 #define ETHER_ALIGN 2 74 75 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 76 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 77 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 78 79 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 80 #define TX_DESC_COUNT 1024 81 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 82 #define RX_DESC_COUNT 256 83 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 84 85 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 89 90 #define TX_MAX_SEGS 128 91 92 #define SOFT_RST_RETRY 1000 93 #define MII_BUSY_RETRY 1000 94 #define MDIO_FREQ 2500000 95 96 #define BURST_LEN_DEFAULT 8 97 #define RX_TX_PRI_DEFAULT 0 98 #define PAUSE_TIME_DEFAULT 0x400 99 100 /* syscon EMAC clock register */ 101 #define EMAC_CLK_REG 0x30 102 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 103 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 104 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 105 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 106 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 107 #define EMAC_CLK_RMII_EN (1 << 13) 108 #define EMAC_CLK_ETXDC (0x7 << 10) 109 #define EMAC_CLK_ETXDC_SHIFT 10 110 #define EMAC_CLK_ERXDC (0x1f << 5) 111 #define EMAC_CLK_ERXDC_SHIFT 5 112 #define EMAC_CLK_PIT (0x1 << 2) 113 #define EMAC_CLK_PIT_MII (0 << 2) 114 #define EMAC_CLK_PIT_RGMII (1 << 2) 115 #define EMAC_CLK_SRC (0x3 << 0) 116 #define EMAC_CLK_SRC_MII (0 << 0) 117 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 118 #define EMAC_CLK_SRC_RGMII (2 << 0) 119 120 /* Burst length of RX and TX DMA transfers */ 121 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 122 123 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 124 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 125 126 /* Pause time field in the transmitted control frame */ 127 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 128 129 enum sunxi_emac_type { 130 EMAC_A64 = 1, 131 EMAC_A83T, 132 EMAC_H3, 133 EMAC_H6, 134 }; 135 136 static const struct of_compat_data compat_data[] = { 137 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 138 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 139 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 140 { "allwinner,sun50i-h6-emac", EMAC_H6 }, 141 { NULL } 142 }; 143 144 struct sunxi_emac_bufmap { 145 bus_dmamap_t map; 146 struct mbuf *mbuf; 147 }; 148 149 struct sunxi_emac_txring { 150 bus_dma_tag_t desc_tag; 151 bus_dmamap_t desc_map; 152 bus_dma_segment_t desc_dmaseg; 153 struct sunxi_emac_desc *desc_ring; 154 bus_addr_t desc_ring_paddr; 155 bus_dma_tag_t buf_tag; 156 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 157 u_int cur, next, queued; 158 }; 159 160 struct sunxi_emac_rxring { 161 bus_dma_tag_t desc_tag; 162 bus_dmamap_t desc_map; 163 bus_dma_segment_t desc_dmaseg; 164 struct sunxi_emac_desc *desc_ring; 165 bus_addr_t desc_ring_paddr; 166 bus_dma_tag_t buf_tag; 167 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 168 u_int cur; 169 }; 170 171 struct sunxi_emac_softc { 172 device_t dev; 173 int phandle; 174 enum sunxi_emac_type type; 175 bus_space_tag_t bst; 176 bus_dma_tag_t dmat; 177 178 bus_space_handle_t bsh; 179 struct clk *clk_ahb; 180 struct clk *clk_ephy; 181 struct fdtbus_reset *rst_ahb; 182 struct fdtbus_reset *rst_ephy; 183 struct fdtbus_regulator *reg_phy; 184 struct fdtbus_gpio_pin *pin_reset; 185 186 struct syscon *syscon; 187 188 int phy_id; 189 190 kmutex_t mtx; 191 struct ethercom ec; 192 struct mii_data mii; 193 callout_t stat_ch; 194 void *ih; 195 u_int mdc_div_ratio_m; 196 197 struct sunxi_emac_txring tx; 198 struct sunxi_emac_rxring rx; 199 }; 200 201 #define RD4(sc, reg) \ 202 bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) 203 #define WR4(sc, reg, val) \ 204 bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) 205 206 static int 207 sunxi_emac_mii_readreg(device_t dev, int phy, int reg) 208 { 209 struct sunxi_emac_softc *sc = device_private(dev); 210 int retry, val; 211 212 val = 0; 213 214 WR4(sc, EMAC_MII_CMD, 215 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 216 (phy << PHY_ADDR_SHIFT) | 217 (reg << PHY_REG_ADDR_SHIFT) | 218 MII_BUSY); 219 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 220 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 221 val = RD4(sc, EMAC_MII_DATA); 222 break; 223 } 224 delay(10); 225 } 226 227 if (retry == 0) 228 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 229 phy, reg); 230 231 return val; 232 } 233 234 static void 235 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, int val) 236 { 237 struct sunxi_emac_softc *sc = device_private(dev); 238 int retry; 239 240 WR4(sc, EMAC_MII_DATA, val); 241 WR4(sc, EMAC_MII_CMD, 242 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 243 (phy << PHY_ADDR_SHIFT) | 244 (reg << PHY_REG_ADDR_SHIFT) | 245 MII_WR | MII_BUSY); 246 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 247 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 248 break; 249 delay(10); 250 } 251 252 if (retry == 0) 253 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 254 phy, reg); 255 } 256 257 static void 258 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 259 { 260 struct mii_data *mii = &sc->mii; 261 uint32_t val; 262 263 val = RD4(sc, EMAC_BASIC_CTL_0); 264 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 265 266 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 267 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 268 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 269 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 270 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 271 else 272 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 273 274 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 275 val |= BASIC_CTL_DUPLEX; 276 277 WR4(sc, EMAC_BASIC_CTL_0, val); 278 279 val = RD4(sc, EMAC_RX_CTL_0); 280 val &= ~RX_FLOW_CTL_EN; 281 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 282 val |= RX_FLOW_CTL_EN; 283 WR4(sc, EMAC_RX_CTL_0, val); 284 285 val = RD4(sc, EMAC_TX_FLOW_CTL); 286 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 287 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 288 val |= TX_FLOW_CTL_EN; 289 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 290 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 291 WR4(sc, EMAC_TX_FLOW_CTL, val); 292 } 293 294 static void 295 sunxi_emac_mii_statchg(struct ifnet *ifp) 296 { 297 struct sunxi_emac_softc * const sc = ifp->if_softc; 298 299 sunxi_emac_update_link(sc); 300 } 301 302 static void 303 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 304 bus_dmamap_t map, int start, int end, int total, int flags) 305 { 306 if (end > start) { 307 bus_dmamap_sync(dmat, map, DESC_OFF(start), 308 DESC_OFF(end) - DESC_OFF(start), flags); 309 } else { 310 bus_dmamap_sync(dmat, map, DESC_OFF(start), 311 DESC_OFF(total) - DESC_OFF(start), flags); 312 if (DESC_OFF(end) - DESC_OFF(0) > 0) 313 bus_dmamap_sync(dmat, map, DESC_OFF(0), 314 DESC_OFF(end) - DESC_OFF(0), flags); 315 } 316 } 317 318 static void 319 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 320 bus_addr_t paddr, u_int len) 321 { 322 uint32_t status, size; 323 324 if (paddr == 0 || len == 0) { 325 status = 0; 326 size = 0; 327 --sc->tx.queued; 328 } else { 329 status = TX_DESC_CTL; 330 size = flags | len; 331 ++sc->tx.queued; 332 } 333 334 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 335 sc->tx.desc_ring[index].size = htole32(size); 336 sc->tx.desc_ring[index].status = htole32(status); 337 } 338 339 static int 340 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 341 { 342 bus_dma_segment_t *segs; 343 int error, nsegs, cur, i, flags; 344 u_int csum_flags; 345 346 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 347 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 348 if (error == EFBIG) { 349 device_printf(sc->dev, 350 "TX packet needs too many DMA segments, dropping...\n"); 351 m_freem(m); 352 return 0; 353 } 354 if (error != 0) 355 return 0; 356 357 segs = sc->tx.buf_map[index].map->dm_segs; 358 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 359 360 flags = TX_FIR_DESC; 361 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 362 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 363 csum_flags = TX_CHECKSUM_CTL_FULL; 364 else 365 csum_flags = TX_CHECKSUM_CTL_IP; 366 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 367 } 368 369 for (cur = index, i = 0; i < nsegs; i++) { 370 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 371 if (i == nsegs - 1) 372 flags |= TX_LAST_DESC | TX_INT_CTL; 373 374 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 375 segs[i].ds_len); 376 flags &= ~TX_FIR_DESC; 377 cur = TX_NEXT(cur); 378 } 379 380 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 381 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 382 383 return nsegs; 384 } 385 386 static void 387 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 388 bus_addr_t paddr) 389 { 390 uint32_t status, size; 391 392 status = RX_DESC_CTL; 393 size = MCLBYTES - 1; 394 395 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 396 sc->rx.desc_ring[index].size = htole32(size); 397 sc->rx.desc_ring[index].next = 398 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 399 sc->rx.desc_ring[index].status = htole32(status); 400 } 401 402 static int 403 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 404 { 405 int error; 406 407 m_adj(m, ETHER_ALIGN); 408 409 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 410 sc->rx.buf_map[index].map, m, BUS_DMA_READ|BUS_DMA_NOWAIT); 411 if (error != 0) 412 return error; 413 414 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 415 0, sc->rx.buf_map[index].map->dm_mapsize, 416 BUS_DMASYNC_PREREAD); 417 418 sc->rx.buf_map[index].mbuf = m; 419 sunxi_emac_setup_rxdesc(sc, index, 420 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 421 422 return 0; 423 } 424 425 static struct mbuf * 426 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 427 { 428 struct mbuf *m; 429 430 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 431 if (m != NULL) 432 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 433 434 return m; 435 } 436 437 static void 438 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 439 { 440 struct ifnet *ifp = &sc->ec.ec_if; 441 struct mbuf *m; 442 uint32_t val; 443 int cnt, nsegs, start; 444 445 EMAC_ASSERT_LOCKED(sc); 446 447 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 448 return; 449 450 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 451 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 452 ifp->if_flags |= IFF_OACTIVE; 453 break; 454 } 455 456 IFQ_POLL(&ifp->if_snd, m); 457 if (m == NULL) 458 break; 459 460 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 461 if (nsegs == 0) { 462 ifp->if_flags |= IFF_OACTIVE; 463 break; 464 } 465 IFQ_DEQUEUE(&ifp->if_snd, m); 466 bpf_mtap(ifp, m, BPF_D_OUT); 467 468 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 469 } 470 471 if (cnt != 0) { 472 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 473 start, sc->tx.cur, TX_DESC_COUNT, 474 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 475 476 /* Start and run TX DMA */ 477 val = RD4(sc, EMAC_TX_CTL_1); 478 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 479 } 480 } 481 482 static void 483 sunxi_emac_start(struct ifnet *ifp) 484 { 485 struct sunxi_emac_softc *sc = ifp->if_softc; 486 487 EMAC_LOCK(sc); 488 sunxi_emac_start_locked(sc); 489 EMAC_UNLOCK(sc); 490 } 491 492 static void 493 sunxi_emac_tick(void *softc) 494 { 495 struct sunxi_emac_softc *sc = softc; 496 struct mii_data *mii = &sc->mii; 497 #ifndef EMAC_MPSAFE 498 int s = splnet(); 499 #endif 500 501 EMAC_LOCK(sc); 502 mii_tick(mii); 503 callout_schedule(&sc->stat_ch, hz); 504 EMAC_UNLOCK(sc); 505 506 #ifndef EMAC_MPSAFE 507 splx(s); 508 #endif 509 } 510 511 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 512 static uint32_t 513 bitrev32(uint32_t x) 514 { 515 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 516 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 517 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 518 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 519 520 return (x >> 16) | (x << 16); 521 } 522 523 static void 524 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 525 { 526 struct ifnet *ifp = &sc->ec.ec_if; 527 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 528 struct ether_multi *enm; 529 struct ether_multistep step; 530 const uint8_t *eaddr; 531 532 EMAC_ASSERT_LOCKED(sc); 533 534 val = 0; 535 hash[0] = hash[1] = 0; 536 537 if ((ifp->if_flags & IFF_PROMISC) != 0) 538 val |= DIS_ADDR_FILTER; 539 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 540 val |= RX_ALL_MULTICAST; 541 hash[0] = hash[1] = ~0; 542 } else { 543 val |= HASH_MULTICAST; 544 ETHER_FIRST_MULTI(step, &sc->ec, enm); 545 while (enm != NULL) { 546 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 547 crc &= 0x7f; 548 crc = bitrev32(~crc) >> 26; 549 hashreg = (crc >> 5); 550 hashbit = (crc & 0x1f); 551 hash[hashreg] |= (1 << hashbit); 552 ETHER_NEXT_MULTI(step, enm); 553 } 554 } 555 556 /* Write our unicast address */ 557 eaddr = CLLADDR(ifp->if_sadl); 558 machi = (eaddr[5] << 8) | eaddr[4]; 559 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 560 (eaddr[0] << 0); 561 WR4(sc, EMAC_ADDR_HIGH(0), machi); 562 WR4(sc, EMAC_ADDR_LOW(0), maclo); 563 564 /* Multicast hash filters */ 565 WR4(sc, EMAC_RX_HASH_0, hash[1]); 566 WR4(sc, EMAC_RX_HASH_1, hash[0]); 567 568 /* RX frame filter config */ 569 WR4(sc, EMAC_RX_FRM_FLT, val); 570 } 571 572 static void 573 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 574 { 575 /* Enable interrupts */ 576 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 577 } 578 579 static void 580 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 581 { 582 /* Disable interrupts */ 583 WR4(sc, EMAC_INT_EN, 0); 584 } 585 586 static int 587 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 588 { 589 struct ifnet *ifp = &sc->ec.ec_if; 590 struct mii_data *mii = &sc->mii; 591 uint32_t val; 592 593 EMAC_ASSERT_LOCKED(sc); 594 595 if ((ifp->if_flags & IFF_RUNNING) != 0) 596 return 0; 597 598 sunxi_emac_setup_rxfilter(sc); 599 600 /* Configure DMA burst length and priorities */ 601 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 602 if (sunxi_emac_rx_tx_pri) 603 val |= BASIC_CTL_RX_TX_PRI; 604 WR4(sc, EMAC_BASIC_CTL_1, val); 605 606 /* Enable interrupts */ 607 sunxi_emac_enable_intr(sc); 608 609 /* Enable transmit DMA */ 610 val = RD4(sc, EMAC_TX_CTL_1); 611 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 612 613 /* Enable receive DMA */ 614 val = RD4(sc, EMAC_RX_CTL_1); 615 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 616 617 /* Enable transmitter */ 618 val = RD4(sc, EMAC_TX_CTL_0); 619 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 620 621 /* Enable receiver */ 622 val = RD4(sc, EMAC_RX_CTL_0); 623 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 624 625 ifp->if_flags |= IFF_RUNNING; 626 ifp->if_flags &= ~IFF_OACTIVE; 627 628 mii_mediachg(mii); 629 callout_schedule(&sc->stat_ch, hz); 630 631 return 0; 632 } 633 634 static int 635 sunxi_emac_init(struct ifnet *ifp) 636 { 637 struct sunxi_emac_softc *sc = ifp->if_softc; 638 int error; 639 640 EMAC_LOCK(sc); 641 error = sunxi_emac_init_locked(sc); 642 EMAC_UNLOCK(sc); 643 644 return error; 645 } 646 647 static void 648 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 649 { 650 struct ifnet *ifp = &sc->ec.ec_if; 651 uint32_t val; 652 653 EMAC_ASSERT_LOCKED(sc); 654 655 callout_stop(&sc->stat_ch); 656 657 mii_down(&sc->mii); 658 659 /* Stop transmit DMA and flush data in the TX FIFO */ 660 val = RD4(sc, EMAC_TX_CTL_1); 661 val &= ~TX_DMA_EN; 662 val |= FLUSH_TX_FIFO; 663 WR4(sc, EMAC_TX_CTL_1, val); 664 665 /* Disable transmitter */ 666 val = RD4(sc, EMAC_TX_CTL_0); 667 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 668 669 /* Disable receiver */ 670 val = RD4(sc, EMAC_RX_CTL_0); 671 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 672 673 /* Disable interrupts */ 674 sunxi_emac_disable_intr(sc); 675 676 /* Disable transmit DMA */ 677 val = RD4(sc, EMAC_TX_CTL_1); 678 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 679 680 /* Disable receive DMA */ 681 val = RD4(sc, EMAC_RX_CTL_1); 682 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 683 684 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 685 } 686 687 static void 688 sunxi_emac_stop(struct ifnet *ifp, int disable) 689 { 690 struct sunxi_emac_softc * const sc = ifp->if_softc; 691 692 EMAC_LOCK(sc); 693 sunxi_emac_stop_locked(sc, disable); 694 EMAC_UNLOCK(sc); 695 } 696 697 static int 698 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 699 { 700 struct ifnet *ifp = &sc->ec.ec_if; 701 int error, index, len, npkt; 702 struct mbuf *m, *m0; 703 uint32_t status; 704 705 npkt = 0; 706 707 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 708 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 709 index, index + 1, 710 RX_DESC_COUNT, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 711 712 status = le32toh(sc->rx.desc_ring[index].status); 713 if ((status & RX_DESC_CTL) != 0) 714 break; 715 716 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 717 0, sc->rx.buf_map[index].map->dm_mapsize, 718 BUS_DMASYNC_POSTREAD); 719 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 720 721 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 722 if (len != 0) { 723 m = sc->rx.buf_map[index].mbuf; 724 m_set_rcvif(m, ifp); 725 m->m_flags |= M_HASFCS; 726 m->m_pkthdr.len = len; 727 m->m_len = len; 728 m->m_nextpkt = NULL; 729 730 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 731 (status & RX_FRM_TYPE) != 0) { 732 m->m_pkthdr.csum_flags = M_CSUM_IPv4 | 733 M_CSUM_TCPv4 | M_CSUM_UDPv4; 734 if ((status & RX_HEADER_ERR) != 0) 735 m->m_pkthdr.csum_flags |= 736 M_CSUM_IPv4_BAD; 737 if ((status & RX_PAYLOAD_ERR) != 0) 738 m->m_pkthdr.csum_flags |= 739 M_CSUM_TCP_UDP_BAD; 740 } 741 742 ++npkt; 743 744 if_percpuq_enqueue(ifp->if_percpuq, m); 745 } 746 747 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 748 error = sunxi_emac_setup_rxbuf(sc, index, m0); 749 if (error != 0) { 750 /* XXX hole in RX ring */ 751 } 752 } else 753 ifp->if_ierrors++; 754 755 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 756 index, index + 1, 757 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 758 } 759 760 sc->rx.cur = index; 761 762 return npkt; 763 } 764 765 static void 766 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 767 { 768 struct ifnet *ifp = &sc->ec.ec_if; 769 struct sunxi_emac_bufmap *bmap; 770 struct sunxi_emac_desc *desc; 771 uint32_t status; 772 int i; 773 774 EMAC_ASSERT_LOCKED(sc); 775 776 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 777 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 778 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 779 i, i + 1, TX_DESC_COUNT, 780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 781 desc = &sc->tx.desc_ring[i]; 782 status = le32toh(desc->status); 783 if ((status & TX_DESC_CTL) != 0) 784 break; 785 bmap = &sc->tx.buf_map[i]; 786 if (bmap->mbuf != NULL) { 787 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 788 0, bmap->map->dm_mapsize, 789 BUS_DMASYNC_POSTWRITE); 790 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 791 m_freem(bmap->mbuf); 792 bmap->mbuf = NULL; 793 } 794 795 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 796 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 797 i, i + 1, TX_DESC_COUNT, 798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 799 800 ifp->if_flags &= ~IFF_OACTIVE; 801 ifp->if_opackets++; 802 } 803 804 sc->tx.next = i; 805 } 806 807 static int 808 sunxi_emac_intr(void *arg) 809 { 810 struct sunxi_emac_softc *sc = arg; 811 struct ifnet *ifp = &sc->ec.ec_if; 812 uint32_t val; 813 814 EMAC_LOCK(sc); 815 816 val = RD4(sc, EMAC_INT_STA); 817 WR4(sc, EMAC_INT_STA, val); 818 819 if (val & RX_INT) 820 sunxi_emac_rxintr(sc); 821 822 if (val & (TX_INT|TX_BUF_UA_INT)) { 823 sunxi_emac_txintr(sc); 824 if_schedule_deferred_start(ifp); 825 } 826 827 EMAC_UNLOCK(sc); 828 829 return 1; 830 } 831 832 static int 833 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 834 { 835 struct sunxi_emac_softc *sc = ifp->if_softc; 836 struct mii_data *mii = &sc->mii; 837 struct ifreq *ifr = data; 838 int error, s; 839 840 #ifndef EMAC_MPSAFE 841 s = splnet(); 842 #endif 843 844 switch (cmd) { 845 case SIOCSIFMEDIA: 846 case SIOCGIFMEDIA: 847 #ifdef EMAC_MPSAFE 848 s = splnet(); 849 #endif 850 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 851 #ifdef EMAC_MPSAFE 852 splx(s); 853 #endif 854 break; 855 default: 856 #ifdef EMAC_MPSAFE 857 s = splnet(); 858 #endif 859 error = ether_ioctl(ifp, cmd, data); 860 #ifdef EMAC_MPSAFE 861 splx(s); 862 #endif 863 if (error != ENETRESET) 864 break; 865 866 error = 0; 867 868 if (cmd == SIOCSIFCAP) 869 error = (*ifp->if_init)(ifp); 870 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 871 ; 872 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 873 EMAC_LOCK(sc); 874 sunxi_emac_setup_rxfilter(sc); 875 EMAC_UNLOCK(sc); 876 } 877 break; 878 } 879 880 #ifndef EMAC_MPSAFE 881 splx(s); 882 #endif 883 884 return error; 885 } 886 887 static bool 888 sunxi_emac_has_internal_phy(struct sunxi_emac_softc *sc) 889 { 890 const char * mdio_internal_compat[] = { 891 "allwinner,sun8i-h3-mdio-internal", 892 NULL 893 }; 894 int phy; 895 896 /* Non-standard property, for compatible with old dts files */ 897 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) 898 return true; 899 900 phy = fdtbus_get_phandle(sc->phandle, "phy-handle"); 901 if (phy == -1) 902 return false; 903 904 /* For internal PHY, check compatible string of parent node */ 905 return of_compatible(OF_parent(phy), mdio_internal_compat) >= 0; 906 } 907 908 static int 909 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 910 { 911 uint32_t reg, tx_delay, rx_delay; 912 const char *phy_type; 913 914 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 915 if (phy_type == NULL) 916 return 0; 917 918 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 919 920 syscon_lock(sc->syscon); 921 reg = syscon_read_4(sc->syscon, EMAC_CLK_REG); 922 923 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 924 if (strcmp(phy_type, "rgmii") == 0) 925 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 926 else if (strcmp(phy_type, "rmii") == 0) 927 reg |= EMAC_CLK_RMII_EN; 928 else 929 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 930 931 if (of_getprop_uint32(sc->phandle, "allwinner,tx-delay-ps", 932 &tx_delay) == 0) { 933 reg &= ~EMAC_CLK_ETXDC; 934 reg |= ((tx_delay / 100) << EMAC_CLK_ETXDC_SHIFT); 935 } else if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 936 reg &= ~EMAC_CLK_ETXDC; 937 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 938 } 939 if (of_getprop_uint32(sc->phandle, "allwinner,rx-delay-ps", 940 &rx_delay) == 0) { 941 reg &= ~EMAC_CLK_ERXDC; 942 reg |= ((rx_delay / 100) << EMAC_CLK_ERXDC_SHIFT); 943 } else if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 944 reg &= ~EMAC_CLK_ERXDC; 945 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 946 } 947 948 if (sc->type == EMAC_H3 || sc->type == EMAC_H6) { 949 if (sunxi_emac_has_internal_phy(sc)) { 950 reg |= EMAC_CLK_EPHY_SELECT; 951 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 952 if (of_hasprop(sc->phandle, 953 "allwinner,leds-active-low")) 954 reg |= EMAC_CLK_EPHY_LED_POL; 955 else 956 reg &= ~EMAC_CLK_EPHY_LED_POL; 957 958 /* Set internal PHY addr to 1 */ 959 reg &= ~EMAC_CLK_EPHY_ADDR; 960 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 961 } else { 962 reg &= ~EMAC_CLK_EPHY_SELECT; 963 } 964 } 965 966 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 967 968 syscon_write_4(sc->syscon, EMAC_CLK_REG, reg); 969 syscon_unlock(sc->syscon); 970 971 return 0; 972 } 973 974 static int 975 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 976 { 977 u_int freq; 978 int error, div; 979 980 /* Configure PHY for MII or RGMII mode */ 981 if (sunxi_emac_setup_phy(sc) != 0) 982 return ENXIO; 983 984 /* Enable clocks */ 985 error = clk_enable(sc->clk_ahb); 986 if (error != 0) { 987 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 988 return error; 989 } 990 991 if (sc->clk_ephy != NULL) { 992 error = clk_enable(sc->clk_ephy); 993 if (error != 0) { 994 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 995 return error; 996 } 997 } 998 999 /* De-assert reset */ 1000 error = fdtbus_reset_deassert(sc->rst_ahb); 1001 if (error != 0) { 1002 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 1003 return error; 1004 } 1005 if (sc->rst_ephy != NULL) { 1006 error = fdtbus_reset_deassert(sc->rst_ephy); 1007 if (error != 0) { 1008 aprint_error_dev(sc->dev, 1009 "cannot de-assert ephy reset\n"); 1010 return error; 1011 } 1012 } 1013 1014 /* Enable PHY regulator if applicable */ 1015 if (sc->reg_phy != NULL) { 1016 error = fdtbus_regulator_enable(sc->reg_phy); 1017 if (error != 0) { 1018 aprint_error_dev(sc->dev, 1019 "cannot enable PHY regulator\n"); 1020 return error; 1021 } 1022 } 1023 1024 /* Determine MDC clock divide ratio based on AHB clock */ 1025 freq = clk_get_rate(sc->clk_ahb); 1026 if (freq == 0) { 1027 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1028 return ENXIO; 1029 } 1030 div = freq / MDIO_FREQ; 1031 if (div <= 16) 1032 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1033 else if (div <= 32) 1034 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1035 else if (div <= 64) 1036 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1037 else if (div <= 128) 1038 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1039 else { 1040 aprint_error_dev(sc->dev, 1041 "cannot determine MDC clock divide ratio\n"); 1042 return ENXIO; 1043 } 1044 1045 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1046 freq, sc->mdc_div_ratio_m); 1047 1048 return 0; 1049 } 1050 1051 static void 1052 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1053 { 1054 uint32_t maclo, machi; 1055 #if notyet 1056 u_char rootkey[16]; 1057 #endif 1058 1059 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1060 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1061 1062 if (maclo == 0xffffffff && machi == 0xffff) { 1063 #if notyet 1064 /* MAC address in hardware is invalid, create one */ 1065 if (aw_sid_get_rootkey(rootkey) == 0 && 1066 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1067 rootkey[15]) != 0) { 1068 /* MAC address is derived from the root key in SID */ 1069 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1070 (rootkey[3] << 8) | 0x02; 1071 machi = (rootkey[15] << 8) | rootkey[14]; 1072 } else { 1073 #endif 1074 /* Create one */ 1075 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1076 machi = cprng_strong32() & 0xffff; 1077 #if notyet 1078 } 1079 #endif 1080 } 1081 1082 eaddr[0] = maclo & 0xff; 1083 eaddr[1] = (maclo >> 8) & 0xff; 1084 eaddr[2] = (maclo >> 16) & 0xff; 1085 eaddr[3] = (maclo >> 24) & 0xff; 1086 eaddr[4] = machi & 0xff; 1087 eaddr[5] = (machi >> 8) & 0xff; 1088 } 1089 1090 #ifdef SUNXI_EMAC_DEBUG 1091 static void 1092 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 1093 { 1094 static const struct { 1095 const char *name; 1096 u_int reg; 1097 } regs[] = { 1098 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1099 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1100 { "INT_STA", EMAC_INT_STA }, 1101 { "INT_EN", EMAC_INT_EN }, 1102 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1103 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1104 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1105 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1106 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1107 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1108 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1109 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1110 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1111 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1112 { "MII_CMD", EMAC_MII_CMD }, 1113 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1114 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1115 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1116 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1117 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1118 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1119 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1120 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1121 { "RGMII_STA", EMAC_RGMII_STA }, 1122 }; 1123 u_int n; 1124 1125 for (n = 0; n < __arraycount(regs); n++) 1126 device_printf(dev, " %-20s %08x\n", regs[n].name, 1127 RD4(sc, regs[n].reg)); 1128 } 1129 #endif 1130 1131 static int 1132 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1133 { 1134 uint32_t delay_prop[3]; 1135 int pin_value; 1136 1137 if (sc->pin_reset == NULL) 1138 return 0; 1139 1140 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1141 sizeof(delay_prop)) <= 0) 1142 return ENXIO; 1143 1144 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1145 1146 fdtbus_gpio_write(sc->pin_reset, pin_value); 1147 delay(htole32(delay_prop[0])); 1148 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1149 delay(htole32(delay_prop[1])); 1150 fdtbus_gpio_write(sc->pin_reset, pin_value); 1151 delay(htole32(delay_prop[2])); 1152 1153 return 0; 1154 } 1155 1156 static int 1157 sunxi_emac_reset(struct sunxi_emac_softc *sc) 1158 { 1159 int retry; 1160 1161 /* Reset PHY if necessary */ 1162 if (sunxi_emac_phy_reset(sc) != 0) { 1163 aprint_error_dev(sc->dev, "failed to reset PHY\n"); 1164 return ENXIO; 1165 } 1166 1167 /* Soft reset all registers and logic */ 1168 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1169 1170 /* Wait for soft reset bit to self-clear */ 1171 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1172 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1173 break; 1174 delay(10); 1175 } 1176 if (retry == 0) { 1177 aprint_error_dev(sc->dev, "soft reset timed out\n"); 1178 #ifdef SUNXI_EMAC_DEBUG 1179 sunxi_emac_dump_regs(sc); 1180 #endif 1181 return ETIMEDOUT; 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int 1188 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1189 { 1190 struct mbuf *m; 1191 int error, nsegs, i; 1192 1193 /* Setup TX ring */ 1194 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1195 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1196 BUS_DMA_WAITOK, &sc->tx.desc_map); 1197 if (error) 1198 return error; 1199 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1200 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1201 if (error) 1202 return error; 1203 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1204 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1205 BUS_DMA_WAITOK); 1206 if (error) 1207 return error; 1208 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1209 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1210 if (error) 1211 return error; 1212 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1213 1214 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1215 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1217 1218 for (i = 0; i < TX_DESC_COUNT; i++) 1219 sc->tx.desc_ring[i].next = 1220 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1221 1222 sc->tx.queued = TX_DESC_COUNT; 1223 for (i = 0; i < TX_DESC_COUNT; i++) { 1224 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1225 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1226 &sc->tx.buf_map[i].map); 1227 if (error != 0) { 1228 device_printf(sc->dev, "cannot create TX buffer map\n"); 1229 return error; 1230 } 1231 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1232 } 1233 1234 /* Setup RX ring */ 1235 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1236 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1237 BUS_DMA_WAITOK, &sc->rx.desc_map); 1238 if (error) 1239 return error; 1240 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1241 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1242 if (error) 1243 return error; 1244 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1245 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1246 BUS_DMA_WAITOK); 1247 if (error) 1248 return error; 1249 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1250 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1251 if (error) 1252 return error; 1253 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1254 1255 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1256 1257 for (i = 0; i < RX_DESC_COUNT; i++) { 1258 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1259 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1260 &sc->rx.buf_map[i].map); 1261 if (error != 0) { 1262 device_printf(sc->dev, "cannot create RX buffer map\n"); 1263 return error; 1264 } 1265 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1266 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1267 return ENOMEM; 1268 } 1269 error = sunxi_emac_setup_rxbuf(sc, i, m); 1270 if (error != 0) { 1271 device_printf(sc->dev, "cannot create RX buffer\n"); 1272 return error; 1273 } 1274 } 1275 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1276 0, sc->rx.desc_map->dm_mapsize, 1277 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1278 1279 /* Write transmit and receive descriptor base address registers */ 1280 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1281 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1282 1283 return 0; 1284 } 1285 1286 static int 1287 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1288 { 1289 const int phandle = sc->phandle; 1290 bus_addr_t addr, size; 1291 1292 /* Map EMAC registers */ 1293 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) 1294 return ENXIO; 1295 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh) != 0) 1296 return ENXIO; 1297 1298 /* Get SYSCON registers */ 1299 sc->syscon = fdtbus_syscon_acquire(phandle, "syscon"); 1300 if (sc->syscon == NULL) 1301 return ENXIO; 1302 1303 /* The "ahb"/"stmmaceth" clock and reset is required */ 1304 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL && 1305 (sc->clk_ahb = fdtbus_clock_get(phandle, "stmmaceth")) == NULL) 1306 return ENXIO; 1307 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL && 1308 (sc->rst_ahb = fdtbus_reset_get(phandle, "stmmaceth")) == NULL) 1309 return ENXIO; 1310 1311 /* Internal PHY clock and reset are optional properties. */ 1312 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1313 if (sc->clk_ephy == NULL) { 1314 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1315 if (phy_phandle != -1) 1316 sc->clk_ephy = fdtbus_clock_get_index(phy_phandle, 0); 1317 } 1318 sc->rst_ephy = fdtbus_reset_get(phandle, "ephy"); 1319 if (sc->rst_ephy == NULL) { 1320 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1321 if (phy_phandle != -1) 1322 sc->rst_ephy = fdtbus_reset_get_index(phy_phandle, 0); 1323 } 1324 1325 /* Regulator is optional */ 1326 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1327 1328 /* Reset GPIO is optional */ 1329 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1330 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1331 1332 return 0; 1333 } 1334 1335 static int 1336 sunxi_emac_get_phyid(struct sunxi_emac_softc *sc) 1337 { 1338 bus_addr_t addr; 1339 int phy_phandle; 1340 1341 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy"); 1342 if (phy_phandle == -1) 1343 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy-handle"); 1344 if (phy_phandle == -1) 1345 return MII_PHY_ANY; 1346 1347 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 1348 return MII_PHY_ANY; 1349 1350 return (int)addr; 1351 } 1352 1353 static int 1354 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1355 { 1356 struct fdt_attach_args * const faa = aux; 1357 1358 return of_match_compat_data(faa->faa_phandle, compat_data); 1359 } 1360 1361 static void 1362 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1363 { 1364 struct fdt_attach_args * const faa = aux; 1365 struct sunxi_emac_softc * const sc = device_private(self); 1366 const int phandle = faa->faa_phandle; 1367 struct mii_data *mii = &sc->mii; 1368 struct ifnet *ifp = &sc->ec.ec_if; 1369 uint8_t eaddr[ETHER_ADDR_LEN]; 1370 char intrstr[128]; 1371 1372 sc->dev = self; 1373 sc->phandle = phandle; 1374 sc->bst = faa->faa_bst; 1375 sc->dmat = faa->faa_dmat; 1376 sc->type = of_search_compatible(phandle, compat_data)->data; 1377 sc->phy_id = sunxi_emac_get_phyid(sc); 1378 1379 if (sunxi_emac_get_resources(sc) != 0) { 1380 aprint_error(": cannot allocate resources for device\n"); 1381 return; 1382 } 1383 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1384 aprint_error(": cannot decode interrupt\n"); 1385 return; 1386 } 1387 1388 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1389 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1390 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1391 1392 aprint_naive("\n"); 1393 aprint_normal(": EMAC\n"); 1394 1395 /* Setup clocks and regulators */ 1396 if (sunxi_emac_setup_resources(sc) != 0) 1397 return; 1398 1399 /* Read MAC address before resetting the chip */ 1400 sunxi_emac_get_eaddr(sc, eaddr); 1401 1402 /* Soft reset EMAC core */ 1403 if (sunxi_emac_reset(sc) != 0) 1404 return; 1405 1406 /* Setup DMA descriptors */ 1407 if (sunxi_emac_setup_dma(sc) != 0) { 1408 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1409 return; 1410 } 1411 1412 /* Install interrupt handler */ 1413 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1414 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1415 if (sc->ih == NULL) { 1416 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1417 intrstr); 1418 return; 1419 } 1420 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1421 1422 /* Setup ethernet interface */ 1423 ifp->if_softc = sc; 1424 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1425 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1426 #ifdef EMAC_MPSAFE 1427 ifp->if_extflags = IFEF_MPSAFE; 1428 #endif 1429 ifp->if_start = sunxi_emac_start; 1430 ifp->if_ioctl = sunxi_emac_ioctl; 1431 ifp->if_init = sunxi_emac_init; 1432 ifp->if_stop = sunxi_emac_stop; 1433 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1434 IFCAP_CSUM_IPv4_Tx | 1435 IFCAP_CSUM_TCPv4_Rx | 1436 IFCAP_CSUM_TCPv4_Tx | 1437 IFCAP_CSUM_UDPv4_Rx | 1438 IFCAP_CSUM_UDPv4_Tx; 1439 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1440 IFQ_SET_READY(&ifp->if_snd); 1441 1442 /* 802.1Q VLAN-sized frames are supported */ 1443 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1444 1445 /* Attach MII driver */ 1446 sc->ec.ec_mii = mii; 1447 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1448 mii->mii_ifp = ifp; 1449 mii->mii_readreg = sunxi_emac_mii_readreg; 1450 mii->mii_writereg = sunxi_emac_mii_writereg; 1451 mii->mii_statchg = sunxi_emac_mii_statchg; 1452 mii_attach(self, mii, 0xffffffff, sc->phy_id, MII_OFFSET_ANY, 1453 MIIF_DOPAUSE); 1454 1455 if (LIST_EMPTY(&mii->mii_phys)) { 1456 aprint_error_dev(self, "no PHY found!\n"); 1457 return; 1458 } 1459 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 1460 1461 /* Attach interface */ 1462 if_attach(ifp); 1463 if_deferred_start_init(ifp, NULL); 1464 1465 /* Attach ethernet interface */ 1466 ether_ifattach(ifp, eaddr); 1467 } 1468 1469 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1470 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1471