1 /* $NetBSD: sunxi_emac.c,v 1.9 2017/11/16 03:07:17 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.9 2017/11/16 03:07:17 ozaki-r Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 59 #include <arm/sunxi/sunxi_emac.h> 60 61 #ifdef NET_MPSAFE 62 #define EMAC_MPSAFE 1 63 #define CALLOUT_FLAGS CALLOUT_MPSAFE 64 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 65 #else 66 #define CALLOUT_FLAGS 0 67 #define FDT_INTR_FLAGS 0 68 #endif 69 70 #define EMAC_IFNAME "emac%d" 71 72 #define ETHER_ALIGN 2 73 74 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 75 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 76 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 77 78 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 79 #define TX_DESC_COUNT 1024 80 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 81 #define RX_DESC_COUNT 256 82 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 83 84 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 85 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 86 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 87 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 88 89 #define TX_MAX_SEGS 128 90 91 #define SOFT_RST_RETRY 1000 92 #define MII_BUSY_RETRY 1000 93 #define MDIO_FREQ 2500000 94 95 #define BURST_LEN_DEFAULT 8 96 #define RX_TX_PRI_DEFAULT 0 97 #define PAUSE_TIME_DEFAULT 0x400 98 99 /* syscon EMAC clock register */ 100 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 101 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 102 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 103 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 104 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 105 #define EMAC_CLK_RMII_EN (1 << 13) 106 #define EMAC_CLK_ETXDC (0x7 << 10) 107 #define EMAC_CLK_ETXDC_SHIFT 10 108 #define EMAC_CLK_ERXDC (0x1f << 5) 109 #define EMAC_CLK_ERXDC_SHIFT 5 110 #define EMAC_CLK_PIT (0x1 << 2) 111 #define EMAC_CLK_PIT_MII (0 << 2) 112 #define EMAC_CLK_PIT_RGMII (1 << 2) 113 #define EMAC_CLK_SRC (0x3 << 0) 114 #define EMAC_CLK_SRC_MII (0 << 0) 115 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 116 #define EMAC_CLK_SRC_RGMII (2 << 0) 117 118 /* Burst length of RX and TX DMA transfers */ 119 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 120 121 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 122 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 123 124 /* Pause time field in the transmitted control frame */ 125 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 126 127 enum sunxi_emac_type { 128 EMAC_A83T = 1, 129 EMAC_H3, 130 EMAC_A64, 131 }; 132 133 static const struct of_compat_data compat_data[] = { 134 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 135 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 136 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 137 { NULL } 138 }; 139 140 struct sunxi_emac_bufmap { 141 bus_dmamap_t map; 142 struct mbuf *mbuf; 143 }; 144 145 struct sunxi_emac_txring { 146 bus_dma_tag_t desc_tag; 147 bus_dmamap_t desc_map; 148 bus_dma_segment_t desc_dmaseg; 149 struct sunxi_emac_desc *desc_ring; 150 bus_addr_t desc_ring_paddr; 151 bus_dma_tag_t buf_tag; 152 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 153 u_int cur, next, queued; 154 }; 155 156 struct sunxi_emac_rxring { 157 bus_dma_tag_t desc_tag; 158 bus_dmamap_t desc_map; 159 bus_dma_segment_t desc_dmaseg; 160 struct sunxi_emac_desc *desc_ring; 161 bus_addr_t desc_ring_paddr; 162 bus_dma_tag_t buf_tag; 163 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 164 u_int cur; 165 }; 166 167 enum { 168 _RES_EMAC, 169 _RES_SYSCON, 170 _RES_NITEMS 171 }; 172 173 struct sunxi_emac_softc { 174 device_t dev; 175 int phandle; 176 enum sunxi_emac_type type; 177 bus_space_tag_t bst; 178 bus_dma_tag_t dmat; 179 180 bus_space_handle_t bsh[_RES_NITEMS]; 181 struct clk *clk_ahb; 182 struct clk *clk_ephy; 183 struct fdtbus_reset *rst_ahb; 184 struct fdtbus_reset *rst_ephy; 185 struct fdtbus_regulator *reg_phy; 186 struct fdtbus_gpio_pin *pin_reset; 187 188 int phy_id; 189 190 kmutex_t mtx; 191 struct ethercom ec; 192 struct mii_data mii; 193 callout_t stat_ch; 194 void *ih; 195 u_int mdc_div_ratio_m; 196 197 struct sunxi_emac_txring tx; 198 struct sunxi_emac_rxring rx; 199 }; 200 201 #define RD4(sc, reg) \ 202 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg)) 203 #define WR4(sc, reg, val) \ 204 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg), (val)) 205 206 #define SYSCONRD4(sc, reg) \ 207 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg)) 208 #define SYSCONWR4(sc, reg, val) \ 209 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg), (val)) 210 211 static int 212 sunxi_emac_mii_readreg(device_t dev, int phy, int reg) 213 { 214 struct sunxi_emac_softc *sc = device_private(dev); 215 int retry, val; 216 217 val = 0; 218 219 WR4(sc, EMAC_MII_CMD, 220 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 221 (phy << PHY_ADDR_SHIFT) | 222 (reg << PHY_REG_ADDR_SHIFT) | 223 MII_BUSY); 224 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 225 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 226 val = RD4(sc, EMAC_MII_DATA); 227 break; 228 } 229 delay(10); 230 } 231 232 if (retry == 0) 233 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 234 phy, reg); 235 236 return val; 237 } 238 239 static void 240 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, int val) 241 { 242 struct sunxi_emac_softc *sc = device_private(dev); 243 int retry; 244 245 WR4(sc, EMAC_MII_DATA, val); 246 WR4(sc, EMAC_MII_CMD, 247 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 248 (phy << PHY_ADDR_SHIFT) | 249 (reg << PHY_REG_ADDR_SHIFT) | 250 MII_WR | MII_BUSY); 251 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 252 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 253 break; 254 delay(10); 255 } 256 257 if (retry == 0) 258 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 259 phy, reg); 260 } 261 262 static void 263 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 264 { 265 struct mii_data *mii = &sc->mii; 266 uint32_t val; 267 268 val = RD4(sc, EMAC_BASIC_CTL_0); 269 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 270 271 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 272 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 273 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 274 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 275 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 276 else 277 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 278 279 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 280 val |= BASIC_CTL_DUPLEX; 281 282 WR4(sc, EMAC_BASIC_CTL_0, val); 283 284 val = RD4(sc, EMAC_RX_CTL_0); 285 val &= ~RX_FLOW_CTL_EN; 286 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 287 val |= RX_FLOW_CTL_EN; 288 WR4(sc, EMAC_RX_CTL_0, val); 289 290 val = RD4(sc, EMAC_TX_FLOW_CTL); 291 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 292 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 293 val |= TX_FLOW_CTL_EN; 294 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 295 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 296 WR4(sc, EMAC_TX_FLOW_CTL, val); 297 } 298 299 static void 300 sunxi_emac_mii_statchg(struct ifnet *ifp) 301 { 302 struct sunxi_emac_softc * const sc = ifp->if_softc; 303 304 sunxi_emac_update_link(sc); 305 } 306 307 static void 308 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 309 bus_dmamap_t map, int start, int end, int total, int flags) 310 { 311 if (end > start) { 312 bus_dmamap_sync(dmat, map, DESC_OFF(start), 313 DESC_OFF(end) - DESC_OFF(start), flags); 314 } else { 315 bus_dmamap_sync(dmat, map, DESC_OFF(start), 316 DESC_OFF(total) - DESC_OFF(start), flags); 317 if (DESC_OFF(end) - DESC_OFF(0) > 0) 318 bus_dmamap_sync(dmat, map, DESC_OFF(0), 319 DESC_OFF(end) - DESC_OFF(0), flags); 320 } 321 } 322 323 static void 324 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 325 bus_addr_t paddr, u_int len) 326 { 327 uint32_t status, size; 328 329 if (paddr == 0 || len == 0) { 330 status = 0; 331 size = 0; 332 --sc->tx.queued; 333 } else { 334 status = TX_DESC_CTL; 335 size = flags | len; 336 ++sc->tx.queued; 337 } 338 339 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 340 sc->tx.desc_ring[index].size = htole32(size); 341 sc->tx.desc_ring[index].status = htole32(status); 342 } 343 344 static int 345 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 346 { 347 bus_dma_segment_t *segs; 348 int error, nsegs, cur, i, flags; 349 u_int csum_flags; 350 351 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 352 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 353 if (error == EFBIG) { 354 device_printf(sc->dev, 355 "TX packet needs too many DMA segments, dropping...\n"); 356 m_freem(m); 357 return 0; 358 } 359 if (error != 0) 360 return 0; 361 362 segs = sc->tx.buf_map[index].map->dm_segs; 363 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 364 365 flags = TX_FIR_DESC; 366 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 367 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 368 csum_flags = TX_CHECKSUM_CTL_FULL; 369 else 370 csum_flags = TX_CHECKSUM_CTL_IP; 371 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 372 } 373 374 for (cur = index, i = 0; i < nsegs; i++) { 375 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 376 if (i == nsegs - 1) 377 flags |= TX_LAST_DESC | TX_INT_CTL; 378 379 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 380 segs[i].ds_len); 381 flags &= ~TX_FIR_DESC; 382 cur = TX_NEXT(cur); 383 } 384 385 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 386 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 387 388 return nsegs; 389 } 390 391 static void 392 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 393 bus_addr_t paddr) 394 { 395 uint32_t status, size; 396 397 status = RX_DESC_CTL; 398 size = MCLBYTES - 1; 399 400 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 401 sc->rx.desc_ring[index].size = htole32(size); 402 sc->rx.desc_ring[index].next = 403 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 404 sc->rx.desc_ring[index].status = htole32(status); 405 } 406 407 static int 408 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 409 { 410 int error; 411 412 m_adj(m, ETHER_ALIGN); 413 414 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 415 sc->rx.buf_map[index].map, m, BUS_DMA_READ|BUS_DMA_NOWAIT); 416 if (error != 0) 417 return error; 418 419 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 420 0, sc->rx.buf_map[index].map->dm_mapsize, 421 BUS_DMASYNC_PREREAD); 422 423 sc->rx.buf_map[index].mbuf = m; 424 sunxi_emac_setup_rxdesc(sc, index, 425 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 426 427 return 0; 428 } 429 430 static struct mbuf * 431 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 432 { 433 struct mbuf *m; 434 435 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 436 if (m != NULL) 437 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 438 439 return m; 440 } 441 442 static void 443 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 444 { 445 struct ifnet *ifp = &sc->ec.ec_if; 446 struct mbuf *m; 447 uint32_t val; 448 int cnt, nsegs, start; 449 450 EMAC_ASSERT_LOCKED(sc); 451 452 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 453 return; 454 455 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 456 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 457 ifp->if_flags |= IFF_OACTIVE; 458 break; 459 } 460 461 IFQ_POLL(&ifp->if_snd, m); 462 if (m == NULL) 463 break; 464 465 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 466 if (nsegs == 0) { 467 ifp->if_flags |= IFF_OACTIVE; 468 break; 469 } 470 IFQ_DEQUEUE(&ifp->if_snd, m); 471 bpf_mtap(ifp, m); 472 473 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 474 } 475 476 if (cnt != 0) { 477 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 478 start, sc->tx.cur, TX_DESC_COUNT, 479 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 480 481 /* Start and run TX DMA */ 482 val = RD4(sc, EMAC_TX_CTL_1); 483 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 484 } 485 } 486 487 static void 488 sunxi_emac_start(struct ifnet *ifp) 489 { 490 struct sunxi_emac_softc *sc = ifp->if_softc; 491 492 EMAC_LOCK(sc); 493 sunxi_emac_start_locked(sc); 494 EMAC_UNLOCK(sc); 495 } 496 497 static void 498 sunxi_emac_tick(void *softc) 499 { 500 struct sunxi_emac_softc *sc = softc; 501 struct mii_data *mii = &sc->mii; 502 #ifndef EMAC_MPSAFE 503 int s = splnet(); 504 #endif 505 506 EMAC_LOCK(sc); 507 mii_tick(mii); 508 callout_schedule(&sc->stat_ch, hz); 509 EMAC_UNLOCK(sc); 510 511 #ifndef EMAC_MPSAFE 512 splx(s); 513 #endif 514 } 515 516 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 517 static uint32_t 518 bitrev32(uint32_t x) 519 { 520 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 521 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 522 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 523 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 524 525 return (x >> 16) | (x << 16); 526 } 527 528 static void 529 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 530 { 531 struct ifnet *ifp = &sc->ec.ec_if; 532 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 533 struct ether_multi *enm; 534 struct ether_multistep step; 535 const uint8_t *eaddr; 536 537 EMAC_ASSERT_LOCKED(sc); 538 539 val = 0; 540 hash[0] = hash[1] = 0; 541 542 if ((ifp->if_flags & IFF_PROMISC) != 0) 543 val |= DIS_ADDR_FILTER; 544 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 545 val |= RX_ALL_MULTICAST; 546 hash[0] = hash[1] = ~0; 547 } else { 548 val |= HASH_MULTICAST; 549 ETHER_FIRST_MULTI(step, &sc->ec, enm); 550 while (enm != NULL) { 551 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 552 crc &= 0x7f; 553 crc = bitrev32(~crc) >> 26; 554 hashreg = (crc >> 5); 555 hashbit = (crc & 0x1f); 556 hash[hashreg] |= (1 << hashbit); 557 ETHER_NEXT_MULTI(step, enm); 558 } 559 } 560 561 /* Write our unicast address */ 562 eaddr = CLLADDR(ifp->if_sadl); 563 machi = (eaddr[5] << 8) | eaddr[4]; 564 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 565 (eaddr[0] << 0); 566 WR4(sc, EMAC_ADDR_HIGH(0), machi); 567 WR4(sc, EMAC_ADDR_LOW(0), maclo); 568 569 /* Multicast hash filters */ 570 WR4(sc, EMAC_RX_HASH_0, hash[1]); 571 WR4(sc, EMAC_RX_HASH_1, hash[0]); 572 573 /* RX frame filter config */ 574 WR4(sc, EMAC_RX_FRM_FLT, val); 575 } 576 577 static void 578 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 579 { 580 /* Enable interrupts */ 581 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 582 } 583 584 static void 585 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 586 { 587 /* Disable interrupts */ 588 WR4(sc, EMAC_INT_EN, 0); 589 } 590 591 static int 592 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 593 { 594 struct ifnet *ifp = &sc->ec.ec_if; 595 struct mii_data *mii = &sc->mii; 596 uint32_t val; 597 598 EMAC_ASSERT_LOCKED(sc); 599 600 if ((ifp->if_flags & IFF_RUNNING) != 0) 601 return 0; 602 603 sunxi_emac_setup_rxfilter(sc); 604 605 /* Configure DMA burst length and priorities */ 606 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 607 if (sunxi_emac_rx_tx_pri) 608 val |= BASIC_CTL_RX_TX_PRI; 609 WR4(sc, EMAC_BASIC_CTL_1, val); 610 611 /* Enable interrupts */ 612 sunxi_emac_enable_intr(sc); 613 614 /* Enable transmit DMA */ 615 val = RD4(sc, EMAC_TX_CTL_1); 616 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 617 618 /* Enable receive DMA */ 619 val = RD4(sc, EMAC_RX_CTL_1); 620 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 621 622 /* Enable transmitter */ 623 val = RD4(sc, EMAC_TX_CTL_0); 624 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 625 626 /* Enable receiver */ 627 val = RD4(sc, EMAC_RX_CTL_0); 628 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 629 630 ifp->if_flags |= IFF_RUNNING; 631 ifp->if_flags &= ~IFF_OACTIVE; 632 633 mii_mediachg(mii); 634 callout_schedule(&sc->stat_ch, hz); 635 636 return 0; 637 } 638 639 static int 640 sunxi_emac_init(struct ifnet *ifp) 641 { 642 struct sunxi_emac_softc *sc = ifp->if_softc; 643 int error; 644 645 EMAC_LOCK(sc); 646 error = sunxi_emac_init_locked(sc); 647 EMAC_UNLOCK(sc); 648 649 return error; 650 } 651 652 static void 653 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 654 { 655 struct ifnet *ifp = &sc->ec.ec_if; 656 uint32_t val; 657 658 EMAC_ASSERT_LOCKED(sc); 659 660 callout_stop(&sc->stat_ch); 661 662 mii_down(&sc->mii); 663 664 /* Stop transmit DMA and flush data in the TX FIFO */ 665 val = RD4(sc, EMAC_TX_CTL_1); 666 val &= ~TX_DMA_EN; 667 val |= FLUSH_TX_FIFO; 668 WR4(sc, EMAC_TX_CTL_1, val); 669 670 /* Disable transmitter */ 671 val = RD4(sc, EMAC_TX_CTL_0); 672 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 673 674 /* Disable receiver */ 675 val = RD4(sc, EMAC_RX_CTL_0); 676 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 677 678 /* Disable interrupts */ 679 sunxi_emac_disable_intr(sc); 680 681 /* Disable transmit DMA */ 682 val = RD4(sc, EMAC_TX_CTL_1); 683 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 684 685 /* Disable receive DMA */ 686 val = RD4(sc, EMAC_RX_CTL_1); 687 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 688 689 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 690 } 691 692 static void 693 sunxi_emac_stop(struct ifnet *ifp, int disable) 694 { 695 struct sunxi_emac_softc * const sc = ifp->if_softc; 696 697 EMAC_LOCK(sc); 698 sunxi_emac_stop_locked(sc, disable); 699 EMAC_UNLOCK(sc); 700 } 701 702 static int 703 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 704 { 705 struct ifnet *ifp = &sc->ec.ec_if; 706 int error, index, len, npkt; 707 struct mbuf *m, *m0; 708 uint32_t status; 709 710 npkt = 0; 711 712 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 713 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 714 index, index + 1, 715 RX_DESC_COUNT, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 716 717 status = le32toh(sc->rx.desc_ring[index].status); 718 if ((status & RX_DESC_CTL) != 0) 719 break; 720 721 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 722 0, sc->rx.buf_map[index].map->dm_mapsize, 723 BUS_DMASYNC_POSTREAD); 724 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 725 726 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 727 if (len != 0) { 728 m = sc->rx.buf_map[index].mbuf; 729 m_set_rcvif(m, ifp); 730 m->m_flags |= M_HASFCS; 731 m->m_pkthdr.len = len; 732 m->m_len = len; 733 m->m_nextpkt = NULL; 734 735 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 736 (status & RX_FRM_TYPE) != 0) { 737 m->m_pkthdr.csum_flags = M_CSUM_IPv4 | 738 M_CSUM_TCPv4 | M_CSUM_UDPv4; 739 if ((status & RX_HEADER_ERR) != 0) 740 m->m_pkthdr.csum_flags |= 741 M_CSUM_IPv4_BAD; 742 if ((status & RX_PAYLOAD_ERR) != 0) 743 m->m_pkthdr.csum_flags |= 744 M_CSUM_TCP_UDP_BAD; 745 } 746 747 ++npkt; 748 749 if_percpuq_enqueue(ifp->if_percpuq, m); 750 } 751 752 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 753 error = sunxi_emac_setup_rxbuf(sc, index, m0); 754 if (error != 0) { 755 /* XXX hole in RX ring */ 756 } 757 } else 758 ifp->if_ierrors++; 759 760 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 761 index, index + 1, 762 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 763 } 764 765 sc->rx.cur = index; 766 767 return npkt; 768 } 769 770 static void 771 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 772 { 773 struct ifnet *ifp = &sc->ec.ec_if; 774 struct sunxi_emac_bufmap *bmap; 775 struct sunxi_emac_desc *desc; 776 uint32_t status; 777 int i; 778 779 EMAC_ASSERT_LOCKED(sc); 780 781 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 782 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 783 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 784 i, i + 1, TX_DESC_COUNT, 785 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 786 desc = &sc->tx.desc_ring[i]; 787 status = le32toh(desc->status); 788 if ((status & TX_DESC_CTL) != 0) 789 break; 790 bmap = &sc->tx.buf_map[i]; 791 if (bmap->mbuf != NULL) { 792 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 793 0, bmap->map->dm_mapsize, 794 BUS_DMASYNC_POSTWRITE); 795 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 796 m_freem(bmap->mbuf); 797 bmap->mbuf = NULL; 798 } 799 800 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 801 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 802 i, i + 1, TX_DESC_COUNT, 803 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 804 805 ifp->if_flags &= ~IFF_OACTIVE; 806 ifp->if_opackets++; 807 } 808 809 sc->tx.next = i; 810 } 811 812 static int 813 sunxi_emac_intr(void *arg) 814 { 815 struct sunxi_emac_softc *sc = arg; 816 struct ifnet *ifp = &sc->ec.ec_if; 817 uint32_t val; 818 819 EMAC_LOCK(sc); 820 821 val = RD4(sc, EMAC_INT_STA); 822 WR4(sc, EMAC_INT_STA, val); 823 824 if (val & RX_INT) 825 sunxi_emac_rxintr(sc); 826 827 if (val & (TX_INT|TX_BUF_UA_INT)) { 828 sunxi_emac_txintr(sc); 829 if_schedule_deferred_start(ifp); 830 } 831 832 EMAC_UNLOCK(sc); 833 834 return 1; 835 } 836 837 static int 838 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 839 { 840 struct sunxi_emac_softc *sc = ifp->if_softc; 841 struct mii_data *mii = &sc->mii; 842 struct ifreq *ifr = data; 843 int error, s; 844 845 #ifndef EMAC_MPSAFE 846 s = splnet(); 847 #endif 848 849 switch (cmd) { 850 case SIOCSIFMEDIA: 851 case SIOCGIFMEDIA: 852 #ifdef EMAC_MPSAFE 853 s = splnet(); 854 #endif 855 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 856 #ifdef EMAC_MPSAFE 857 splx(s); 858 #endif 859 break; 860 default: 861 #ifdef EMAC_MPSAFE 862 s = splnet(); 863 #endif 864 error = ether_ioctl(ifp, cmd, data); 865 #ifdef EMAC_MPSAFE 866 splx(s); 867 #endif 868 if (error != ENETRESET) 869 break; 870 871 error = 0; 872 873 if (cmd == SIOCSIFCAP) 874 error = (*ifp->if_init)(ifp); 875 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 876 ; 877 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 878 EMAC_LOCK(sc); 879 sunxi_emac_setup_rxfilter(sc); 880 EMAC_UNLOCK(sc); 881 } 882 break; 883 } 884 885 #ifndef EMAC_MPSAFE 886 splx(s); 887 #endif 888 889 return error; 890 } 891 892 static int 893 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 894 { 895 uint32_t reg, tx_delay, rx_delay; 896 const char *phy_type; 897 898 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 899 if (phy_type == NULL) 900 return 0; 901 902 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 903 904 reg = SYSCONRD4(sc, 0); 905 906 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 907 if (strcmp(phy_type, "rgmii") == 0) 908 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 909 else if (strcmp(phy_type, "rmii") == 0) 910 reg |= EMAC_CLK_RMII_EN; 911 else 912 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 913 914 if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 915 reg &= ~EMAC_CLK_ETXDC; 916 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 917 } 918 if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 919 reg &= ~EMAC_CLK_ERXDC; 920 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 921 } 922 923 if (sc->type == EMAC_H3) { 924 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) { 925 reg |= EMAC_CLK_EPHY_SELECT; 926 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 927 if (of_hasprop(sc->phandle, 928 "allwinner,leds-active-low")) 929 reg |= EMAC_CLK_EPHY_LED_POL; 930 else 931 reg &= ~EMAC_CLK_EPHY_LED_POL; 932 933 /* Set internal PHY addr to 1 */ 934 reg &= ~EMAC_CLK_EPHY_ADDR; 935 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 936 } else { 937 reg &= ~EMAC_CLK_EPHY_SELECT; 938 } 939 } 940 941 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 942 943 SYSCONWR4(sc, 0, reg); 944 945 return 0; 946 } 947 948 static int 949 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 950 { 951 u_int freq; 952 int error, div; 953 954 /* Configure PHY for MII or RGMII mode */ 955 if (sunxi_emac_setup_phy(sc) != 0) 956 return ENXIO; 957 958 /* Enable clocks */ 959 error = clk_enable(sc->clk_ahb); 960 if (error != 0) { 961 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 962 return error; 963 } 964 965 if (sc->clk_ephy != NULL) { 966 error = clk_enable(sc->clk_ephy); 967 if (error != 0) { 968 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 969 return error; 970 } 971 } 972 973 /* De-assert reset */ 974 error = fdtbus_reset_deassert(sc->rst_ahb); 975 if (error != 0) { 976 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 977 return error; 978 } 979 if (sc->rst_ephy != NULL) { 980 error = fdtbus_reset_deassert(sc->rst_ephy); 981 if (error != 0) { 982 aprint_error_dev(sc->dev, 983 "cannot de-assert ephy reset\n"); 984 return error; 985 } 986 } 987 988 /* Enable PHY regulator if applicable */ 989 if (sc->reg_phy != NULL) { 990 error = fdtbus_regulator_enable(sc->reg_phy); 991 if (error != 0) { 992 aprint_error_dev(sc->dev, 993 "cannot enable PHY regulator\n"); 994 return error; 995 } 996 } 997 998 /* Determine MDC clock divide ratio based on AHB clock */ 999 freq = clk_get_rate(sc->clk_ahb); 1000 if (freq == 0) { 1001 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1002 return ENXIO; 1003 } 1004 div = freq / MDIO_FREQ; 1005 if (div <= 16) 1006 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1007 else if (div <= 32) 1008 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1009 else if (div <= 64) 1010 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1011 else if (div <= 128) 1012 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1013 else { 1014 aprint_error_dev(sc->dev, 1015 "cannot determine MDC clock divide ratio\n"); 1016 return ENXIO; 1017 } 1018 1019 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1020 freq, sc->mdc_div_ratio_m); 1021 1022 return 0; 1023 } 1024 1025 static void 1026 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1027 { 1028 uint32_t maclo, machi; 1029 #if notyet 1030 u_char rootkey[16]; 1031 #endif 1032 1033 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1034 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1035 1036 if (maclo == 0xffffffff && machi == 0xffff) { 1037 #if notyet 1038 /* MAC address in hardware is invalid, create one */ 1039 if (aw_sid_get_rootkey(rootkey) == 0 && 1040 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1041 rootkey[15]) != 0) { 1042 /* MAC address is derived from the root key in SID */ 1043 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1044 (rootkey[3] << 8) | 0x02; 1045 machi = (rootkey[15] << 8) | rootkey[14]; 1046 } else { 1047 #endif 1048 /* Create one */ 1049 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1050 machi = cprng_strong32() & 0xffff; 1051 #if notyet 1052 } 1053 #endif 1054 } 1055 1056 eaddr[0] = maclo & 0xff; 1057 eaddr[1] = (maclo >> 8) & 0xff; 1058 eaddr[2] = (maclo >> 16) & 0xff; 1059 eaddr[3] = (maclo >> 24) & 0xff; 1060 eaddr[4] = machi & 0xff; 1061 eaddr[5] = (machi >> 8) & 0xff; 1062 } 1063 1064 #ifdef SUNXI_EMAC_DEBUG 1065 static void 1066 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 1067 { 1068 static const struct { 1069 const char *name; 1070 u_int reg; 1071 } regs[] = { 1072 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1073 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1074 { "INT_STA", EMAC_INT_STA }, 1075 { "INT_EN", EMAC_INT_EN }, 1076 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1077 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1078 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1079 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1080 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1081 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1082 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1083 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1084 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1085 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1086 { "MII_CMD", EMAC_MII_CMD }, 1087 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1088 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1089 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1090 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1091 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1092 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1093 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1094 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1095 { "RGMII_STA", EMAC_RGMII_STA }, 1096 }; 1097 u_int n; 1098 1099 for (n = 0; n < __arraycount(regs); n++) 1100 device_printf(dev, " %-20s %08x\n", regs[n].name, 1101 RD4(sc, regs[n].reg)); 1102 } 1103 #endif 1104 1105 static int 1106 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1107 { 1108 uint32_t delay_prop[3]; 1109 int pin_value; 1110 1111 if (sc->pin_reset == NULL) 1112 return 0; 1113 1114 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1115 sizeof(delay_prop)) <= 0) 1116 return ENXIO; 1117 1118 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1119 1120 fdtbus_gpio_write(sc->pin_reset, pin_value); 1121 delay(htole32(delay_prop[0])); 1122 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1123 delay(htole32(delay_prop[1])); 1124 fdtbus_gpio_write(sc->pin_reset, pin_value); 1125 delay(htole32(delay_prop[2])); 1126 1127 return 0; 1128 } 1129 1130 static int 1131 sunxi_emac_reset(struct sunxi_emac_softc *sc) 1132 { 1133 int retry; 1134 1135 /* Reset PHY if necessary */ 1136 if (sunxi_emac_phy_reset(sc) != 0) { 1137 aprint_error_dev(sc->dev, "failed to reset PHY\n"); 1138 return ENXIO; 1139 } 1140 1141 /* Soft reset all registers and logic */ 1142 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1143 1144 /* Wait for soft reset bit to self-clear */ 1145 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1146 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1147 break; 1148 delay(10); 1149 } 1150 if (retry == 0) { 1151 aprint_error_dev(sc->dev, "soft reset timed out\n"); 1152 #ifdef SUNXI_EMAC_DEBUG 1153 sunxi_emac_dump_regs(sc); 1154 #endif 1155 return ETIMEDOUT; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int 1162 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1163 { 1164 struct mbuf *m; 1165 int error, nsegs, i; 1166 1167 /* Setup TX ring */ 1168 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1169 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1170 BUS_DMA_WAITOK, &sc->tx.desc_map); 1171 if (error) 1172 return error; 1173 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1174 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1175 if (error) 1176 return error; 1177 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1178 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1179 BUS_DMA_WAITOK); 1180 if (error) 1181 return error; 1182 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1183 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1184 if (error) 1185 return error; 1186 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1187 1188 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1189 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1190 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1191 1192 for (i = 0; i < TX_DESC_COUNT; i++) 1193 sc->tx.desc_ring[i].next = 1194 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1195 1196 sc->tx.queued = TX_DESC_COUNT; 1197 for (i = 0; i < TX_DESC_COUNT; i++) { 1198 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1199 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1200 &sc->tx.buf_map[i].map); 1201 if (error != 0) { 1202 device_printf(sc->dev, "cannot create TX buffer map\n"); 1203 return error; 1204 } 1205 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1206 } 1207 1208 /* Setup RX ring */ 1209 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1210 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1211 BUS_DMA_WAITOK, &sc->rx.desc_map); 1212 if (error) 1213 return error; 1214 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1215 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1216 if (error) 1217 return error; 1218 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1219 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1220 BUS_DMA_WAITOK); 1221 if (error) 1222 return error; 1223 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1224 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1225 if (error) 1226 return error; 1227 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1228 1229 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1230 1231 for (i = 0; i < RX_DESC_COUNT; i++) { 1232 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1233 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1234 &sc->rx.buf_map[i].map); 1235 if (error != 0) { 1236 device_printf(sc->dev, "cannot create RX buffer map\n"); 1237 return error; 1238 } 1239 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1240 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1241 return ENOMEM; 1242 } 1243 error = sunxi_emac_setup_rxbuf(sc, i, m); 1244 if (error != 0) { 1245 device_printf(sc->dev, "cannot create RX buffer\n"); 1246 return error; 1247 } 1248 } 1249 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1250 0, sc->rx.desc_map->dm_mapsize, 1251 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1252 1253 /* Write transmit and receive descriptor base address registers */ 1254 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1255 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1256 1257 return 0; 1258 } 1259 1260 static int 1261 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1262 { 1263 const int phandle = sc->phandle; 1264 bus_addr_t addr, size; 1265 u_int n; 1266 1267 /* Map registers */ 1268 for (n = 0; n < _RES_NITEMS; n++) { 1269 if (fdtbus_get_reg(phandle, n, &addr, &size) != 0) 1270 return ENXIO; 1271 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[n]) != 0) 1272 return ENXIO; 1273 } 1274 1275 /* Get clocks and resets. "ahb" is required, "ephy" is optional. */ 1276 1277 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL) 1278 return ENXIO; 1279 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1280 1281 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL) 1282 return ENXIO; 1283 sc->rst_ephy = fdtbus_reset_get(phandle, "ephy"); 1284 1285 /* Regulator is optional */ 1286 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1287 1288 /* Reset GPIO is optional */ 1289 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1290 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1291 1292 return 0; 1293 } 1294 1295 static int 1296 sunxi_emac_get_phyid(struct sunxi_emac_softc *sc) 1297 { 1298 bus_addr_t addr; 1299 1300 const int phy_phandle = fdtbus_get_phandle(sc->phandle, "phy"); 1301 if (phy_phandle == -1) 1302 return MII_PHY_ANY; 1303 1304 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 1305 return MII_PHY_ANY; 1306 1307 return (int)addr; 1308 } 1309 1310 static int 1311 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1312 { 1313 struct fdt_attach_args * const faa = aux; 1314 1315 return of_match_compat_data(faa->faa_phandle, compat_data); 1316 } 1317 1318 static void 1319 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1320 { 1321 struct fdt_attach_args * const faa = aux; 1322 struct sunxi_emac_softc * const sc = device_private(self); 1323 const int phandle = faa->faa_phandle; 1324 struct mii_data *mii = &sc->mii; 1325 struct ifnet *ifp = &sc->ec.ec_if; 1326 uint8_t eaddr[ETHER_ADDR_LEN]; 1327 char intrstr[128]; 1328 1329 sc->dev = self; 1330 sc->phandle = phandle; 1331 sc->bst = faa->faa_bst; 1332 sc->dmat = faa->faa_dmat; 1333 sc->type = of_search_compatible(phandle, compat_data)->data; 1334 sc->phy_id = sunxi_emac_get_phyid(sc); 1335 1336 if (sunxi_emac_get_resources(sc) != 0) { 1337 aprint_error(": cannot allocate resources for device\n"); 1338 return; 1339 } 1340 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1341 aprint_error(": cannot decode interrupt\n"); 1342 return; 1343 } 1344 1345 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1346 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1347 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1348 1349 aprint_naive("\n"); 1350 aprint_normal(": EMAC\n"); 1351 1352 /* Setup clocks and regulators */ 1353 if (sunxi_emac_setup_resources(sc) != 0) 1354 return; 1355 1356 /* Read MAC address before resetting the chip */ 1357 sunxi_emac_get_eaddr(sc, eaddr); 1358 1359 /* Soft reset EMAC core */ 1360 if (sunxi_emac_reset(sc) != 0) 1361 return; 1362 1363 /* Setup DMA descriptors */ 1364 if (sunxi_emac_setup_dma(sc) != 0) { 1365 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1366 return; 1367 } 1368 1369 /* Install interrupt handler */ 1370 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1371 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1372 if (sc->ih == NULL) { 1373 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1374 intrstr); 1375 return; 1376 } 1377 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1378 1379 /* Setup ethernet interface */ 1380 ifp->if_softc = sc; 1381 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1383 #ifdef EMAC_MPSAFE 1384 ifp->if_extflags = IFEF_MPSAFE; 1385 #endif 1386 ifp->if_start = sunxi_emac_start; 1387 ifp->if_ioctl = sunxi_emac_ioctl; 1388 ifp->if_init = sunxi_emac_init; 1389 ifp->if_stop = sunxi_emac_stop; 1390 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1391 IFCAP_CSUM_IPv4_Tx | 1392 IFCAP_CSUM_TCPv4_Rx | 1393 IFCAP_CSUM_TCPv4_Tx | 1394 IFCAP_CSUM_UDPv4_Rx | 1395 IFCAP_CSUM_UDPv4_Tx; 1396 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1397 IFQ_SET_READY(&ifp->if_snd); 1398 1399 /* 802.1Q VLAN-sized frames are supported */ 1400 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1401 1402 /* Attach MII driver */ 1403 sc->ec.ec_mii = mii; 1404 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1405 mii->mii_ifp = ifp; 1406 mii->mii_readreg = sunxi_emac_mii_readreg; 1407 mii->mii_writereg = sunxi_emac_mii_writereg; 1408 mii->mii_statchg = sunxi_emac_mii_statchg; 1409 mii_attach(self, mii, 0xffffffff, sc->phy_id, MII_OFFSET_ANY, 1410 MIIF_DOPAUSE); 1411 1412 if (LIST_EMPTY(&mii->mii_phys)) { 1413 aprint_error_dev(self, "no PHY found!\n"); 1414 return; 1415 } 1416 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 1417 1418 /* Attach interface */ 1419 if_attach(ifp); 1420 if_deferred_start_init(ifp, NULL); 1421 1422 /* Attach ethernet interface */ 1423 ether_ifattach(ifp, eaddr); 1424 } 1425 1426 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1427 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1428