1 /* $NetBSD: sunxi_codec.c,v 1.7 2019/06/08 08:02:37 isaki Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.7 2019/06/08 08:02:37 isaki Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio/audio_if.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_codec.h> 47 48 #define TX_TRIG_LEVEL 0xf 49 #define RX_TRIG_LEVEL 0x7 50 #define DRQ_CLR_CNT 0x3 51 52 #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 53 #define DAC_DPC_EN_DA 0x80000000 54 #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 55 #define DAC_FIFOC_FS __BITS(31,29) 56 #define DAC_FS_48KHZ 0 57 #define DAC_FS_32KHZ 1 58 #define DAC_FS_24KHZ 2 59 #define DAC_FS_16KHZ 3 60 #define DAC_FS_12KHZ 4 61 #define DAC_FS_8KHZ 5 62 #define DAC_FS_192KHZ 6 63 #define DAC_FS_96KHZ 7 64 #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 65 #define FIFO_MODE_24_31_8 0 66 #define FIFO_MODE_16_31_16 0 67 #define FIFO_MODE_16_15_0 1 68 #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 69 #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 70 #define DAC_FIFOC_MONO_EN __BIT(6) 71 #define DAC_FIFOC_TX_BITS __BIT(5) 72 #define DAC_FIFOC_DRQ_EN __BIT(4) 73 #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 74 #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 75 #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 76 #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 77 #define ADC_FIFOC_FS __BITS(31,29) 78 #define ADC_FS_48KHZ 0 79 #define ADC_FIFOC_EN_AD __BIT(28) 80 #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 81 #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 82 #define ADC_FIFOC_MONO_EN __BIT(7) 83 #define ADC_FIFOC_RX_BITS __BIT(6) 84 #define ADC_FIFOC_DRQ_EN __BIT(4) 85 #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 86 #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 87 #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 88 #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 89 #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 90 91 static const struct of_compat_data compat_data[] = { 92 A10_CODEC_COMPATDATA, 93 A31_CODEC_COMPATDATA, 94 H3_CODEC_COMPATDATA, 95 { NULL } 96 }; 97 98 #define CODEC_READ(sc, reg) \ 99 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 100 #define CODEC_WRITE(sc, reg, val) \ 101 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 102 103 static int 104 sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 105 size_t align, struct sunxi_codec_dma *dma) 106 { 107 int error; 108 109 dma->dma_size = size; 110 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 111 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 112 if (error) 113 return error; 114 115 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 116 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 117 if (error) 118 goto free; 119 120 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 121 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 122 if (error) 123 goto unmap; 124 125 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 126 dma->dma_size, NULL, BUS_DMA_WAITOK); 127 if (error) 128 goto destroy; 129 130 return 0; 131 132 destroy: 133 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 134 unmap: 135 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 136 free: 137 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 138 139 return error; 140 } 141 142 static void 143 sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 144 { 145 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 146 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 147 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 148 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 149 } 150 151 static int 152 sunxi_codec_transfer(struct sunxi_codec_chan *ch) 153 { 154 bus_dma_segment_t seg; 155 156 seg.ds_addr = ch->ch_cur_phys; 157 seg.ds_len = ch->ch_blksize; 158 ch->ch_req.dreq_segs = &seg; 159 ch->ch_req.dreq_nsegs = 1; 160 161 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 162 } 163 164 static int 165 sunxi_codec_query_format(void *priv, audio_format_query_t *afp) 166 { 167 struct sunxi_codec_softc * const sc = priv; 168 169 return audio_query_format(&sc->sc_format, 1, afp); 170 } 171 172 static int 173 sunxi_codec_set_format(void *priv, int setmode, 174 const audio_params_t *play, const audio_params_t *rec, 175 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 176 { 177 178 return 0; 179 } 180 181 static int 182 sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 183 { 184 struct sunxi_codec_softc * const sc = priv; 185 186 return sc->sc_cfg->set_port(sc, mc); 187 } 188 189 static int 190 sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 191 { 192 struct sunxi_codec_softc * const sc = priv; 193 194 return sc->sc_cfg->get_port(sc, mc); 195 } 196 197 static int 198 sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 199 { 200 struct sunxi_codec_softc * const sc = priv; 201 202 return sc->sc_cfg->query_devinfo(sc, di); 203 } 204 205 static void * 206 sunxi_codec_allocm(void *priv, int dir, size_t size) 207 { 208 struct sunxi_codec_softc * const sc = priv; 209 struct sunxi_codec_dma *dma; 210 int error; 211 212 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 213 214 error = sunxi_codec_allocdma(sc, size, 16, dma); 215 if (error) { 216 kmem_free(dma, sizeof(*dma)); 217 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 218 error); 219 return NULL; 220 } 221 222 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 223 224 return dma->dma_addr; 225 } 226 227 static void 228 sunxi_codec_freem(void *priv, void *addr, size_t size) 229 { 230 struct sunxi_codec_softc * const sc = priv; 231 struct sunxi_codec_dma *dma; 232 233 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 234 if (dma->dma_addr == addr) { 235 sunxi_codec_freedma(sc, dma); 236 LIST_REMOVE(dma, dma_list); 237 kmem_free(dma, sizeof(*dma)); 238 break; 239 } 240 } 241 242 static int 243 sunxi_codec_getdev(void *priv, struct audio_device *adev) 244 { 245 struct sunxi_codec_softc * const sc = priv; 246 247 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 248 snprintf(adev->version, sizeof(adev->version), "%s", 249 sc->sc_cfg->name); 250 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 251 252 return 0; 253 } 254 255 static int 256 sunxi_codec_get_props(void *priv) 257 { 258 259 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE| 260 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 261 } 262 263 static int 264 sunxi_codec_round_blocksize(void *priv, int bs, int mode, 265 const audio_params_t *params) 266 { 267 bs &= ~3; 268 if (bs == 0) 269 bs = 4; 270 return bs; 271 } 272 273 static int 274 sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 275 void (*intr)(void *), void *intrarg, const audio_params_t *params) 276 { 277 struct sunxi_codec_softc * const sc = priv; 278 struct sunxi_codec_chan *ch = &sc->sc_pchan; 279 struct sunxi_codec_dma *dma; 280 bus_addr_t pstart; 281 bus_size_t psize; 282 uint32_t val; 283 int error; 284 285 pstart = 0; 286 psize = (uintptr_t)end - (uintptr_t)start; 287 288 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 289 if (dma->dma_addr == start) { 290 pstart = dma->dma_map->dm_segs[0].ds_addr; 291 break; 292 } 293 if (pstart == 0) { 294 device_printf(sc->sc_dev, "bad addr %p\n", start); 295 return EINVAL; 296 } 297 298 ch->ch_intr = intr; 299 ch->ch_intrarg = intrarg; 300 ch->ch_start_phys = ch->ch_cur_phys = pstart; 301 ch->ch_end_phys = pstart + psize; 302 ch->ch_blksize = blksize; 303 304 /* Flush DAC FIFO */ 305 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 306 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 307 308 /* Clear DAC FIFO status */ 309 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 310 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 311 312 /* Unmute output */ 313 if (sc->sc_cfg->mute) 314 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 315 316 /* Configure DAC FIFO */ 317 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 318 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 319 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 320 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 321 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 322 323 /* Enable DAC DRQ */ 324 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 325 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 326 327 /* Start DMA transfer */ 328 error = sunxi_codec_transfer(ch); 329 if (error != 0) { 330 aprint_error_dev(sc->sc_dev, 331 "failed to start DMA transfer: %d\n", error); 332 return error; 333 } 334 335 return 0; 336 } 337 338 static int 339 sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 340 void (*intr)(void *), void *intrarg, const audio_params_t *params) 341 { 342 struct sunxi_codec_softc * const sc = priv; 343 struct sunxi_codec_chan *ch = &sc->sc_rchan; 344 struct sunxi_codec_dma *dma; 345 bus_addr_t pstart; 346 bus_size_t psize; 347 uint32_t val; 348 int error; 349 350 pstart = 0; 351 psize = (uintptr_t)end - (uintptr_t)start; 352 353 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 354 if (dma->dma_addr == start) { 355 pstart = dma->dma_map->dm_segs[0].ds_addr; 356 break; 357 } 358 if (pstart == 0) { 359 device_printf(sc->sc_dev, "bad addr %p\n", start); 360 return EINVAL; 361 } 362 363 ch->ch_intr = intr; 364 ch->ch_intrarg = intrarg; 365 ch->ch_start_phys = ch->ch_cur_phys = pstart; 366 ch->ch_end_phys = pstart + psize; 367 ch->ch_blksize = blksize; 368 369 /* Flush ADC FIFO */ 370 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 371 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 372 373 /* Clear ADC FIFO status */ 374 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 375 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 376 377 /* Unmute input */ 378 if (sc->sc_cfg->mute) 379 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 380 381 /* Configure ADC FIFO */ 382 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 383 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 384 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 385 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 386 387 /* Enable ADC DRQ */ 388 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 389 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 390 391 /* Start DMA transfer */ 392 error = sunxi_codec_transfer(ch); 393 if (error != 0) { 394 aprint_error_dev(sc->sc_dev, 395 "failed to start DMA transfer: %d\n", error); 396 return error; 397 } 398 399 return 0; 400 } 401 402 static int 403 sunxi_codec_halt_output(void *priv) 404 { 405 struct sunxi_codec_softc * const sc = priv; 406 struct sunxi_codec_chan *ch = &sc->sc_pchan; 407 uint32_t val; 408 409 /* Disable DMA channel */ 410 fdtbus_dma_halt(ch->ch_dma); 411 412 /* flush fifo */ 413 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 414 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 415 while (val & DAC_FIFOC_FIFO_FLUSH) 416 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 417 418 /* Mute output */ 419 if (sc->sc_cfg->mute) 420 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 421 422 /* Disable DAC DRQ */ 423 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 424 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 425 426 ch->ch_intr = NULL; 427 ch->ch_intrarg = NULL; 428 429 return 0; 430 } 431 432 static int 433 sunxi_codec_halt_input(void *priv) 434 { 435 struct sunxi_codec_softc * const sc = priv; 436 struct sunxi_codec_chan *ch = &sc->sc_rchan; 437 uint32_t val; 438 439 /* Mute output */ 440 if (sc->sc_cfg->mute) 441 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 442 443 /* flush fifo */ 444 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 445 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 446 while (val & ADC_FIFOC_FIFO_FLUSH) 447 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 448 449 /* Disable DMA channel */ 450 fdtbus_dma_halt(ch->ch_dma); 451 452 /* Disable ADC DRQ */ 453 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 454 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 455 456 return 0; 457 } 458 459 static void 460 sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 461 { 462 struct sunxi_codec_softc * const sc = priv; 463 464 *intr = &sc->sc_intr_lock; 465 *thread = &sc->sc_lock; 466 } 467 468 static const struct audio_hw_if sunxi_codec_hw_if = { 469 .query_format = sunxi_codec_query_format, 470 .set_format = sunxi_codec_set_format, 471 .allocm = sunxi_codec_allocm, 472 .freem = sunxi_codec_freem, 473 .getdev = sunxi_codec_getdev, 474 .set_port = sunxi_codec_set_port, 475 .get_port = sunxi_codec_get_port, 476 .query_devinfo = sunxi_codec_query_devinfo, 477 .get_props = sunxi_codec_get_props, 478 .round_blocksize = sunxi_codec_round_blocksize, 479 .trigger_output = sunxi_codec_trigger_output, 480 .trigger_input = sunxi_codec_trigger_input, 481 .halt_output = sunxi_codec_halt_output, 482 .halt_input = sunxi_codec_halt_input, 483 .get_locks = sunxi_codec_get_locks, 484 }; 485 486 static void 487 sunxi_codec_dmaintr(void *priv) 488 { 489 struct sunxi_codec_chan * const ch = priv; 490 struct sunxi_codec_softc * const sc = ch->ch_sc; 491 492 mutex_enter(&sc->sc_intr_lock); 493 ch->ch_cur_phys += ch->ch_blksize; 494 if (ch->ch_cur_phys >= ch->ch_end_phys) 495 ch->ch_cur_phys = ch->ch_start_phys; 496 497 if (ch->ch_intr) { 498 ch->ch_intr(ch->ch_intrarg); 499 sunxi_codec_transfer(ch); 500 } 501 mutex_exit(&sc->sc_intr_lock); 502 } 503 504 static int 505 sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 506 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 507 { 508 ch->ch_sc = sc; 509 ch->ch_mode = mode; 510 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 511 if (ch->ch_dma == NULL) { 512 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 513 return ENXIO; 514 } 515 516 if (mode == AUMODE_PLAY) { 517 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 518 ch->ch_req.dreq_dev_phys = 519 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 520 } else { 521 ch->ch_req.dreq_dir = FDT_DMA_READ; 522 ch->ch_req.dreq_dev_phys = 523 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 524 } 525 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 526 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 527 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 528 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 529 530 return 0; 531 } 532 533 static int 534 sunxi_codec_clock_init(int phandle) 535 { 536 struct fdtbus_reset *rst; 537 struct clk *clk; 538 int error; 539 540 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 541 clk = fdtbus_clock_get(phandle, "codec"); 542 if (clk == NULL) { 543 aprint_error(": couldn't find codec clock\n"); 544 return ENXIO; 545 } 546 error = clk_set_rate(clk, 24576000); 547 if (error != 0) { 548 aprint_error(": couldn't set codec clock rate: %d\n", error); 549 return error; 550 } 551 error = clk_enable(clk); 552 if (error != 0) { 553 aprint_error(": couldn't enable codec clock: %d\n", error); 554 return error; 555 } 556 557 /* Enable APB clock */ 558 clk = fdtbus_clock_get(phandle, "apb"); 559 if (clk == NULL) { 560 aprint_error(": couldn't find apb clock\n"); 561 return ENXIO; 562 } 563 error = clk_enable(clk); 564 if (error != 0) { 565 aprint_error(": couldn't enable apb clock: %d\n", error); 566 return error; 567 } 568 569 /* De-assert reset */ 570 rst = fdtbus_reset_get_index(phandle, 0); 571 if (rst != NULL) { 572 error = fdtbus_reset_deassert(rst); 573 if (error != 0) { 574 aprint_error(": couldn't de-assert reset: %d\n", error); 575 return error; 576 } 577 } 578 579 return 0; 580 } 581 582 static int 583 sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 584 { 585 struct fdt_attach_args * const faa = aux; 586 587 return of_match_compat_data(faa->faa_phandle, compat_data); 588 } 589 590 static void 591 sunxi_codec_attach(device_t parent, device_t self, void *aux) 592 { 593 struct sunxi_codec_softc * const sc = device_private(self); 594 struct fdt_attach_args * const faa = aux; 595 const int phandle = faa->faa_phandle; 596 bus_addr_t addr; 597 bus_size_t size; 598 uint32_t val; 599 600 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 601 aprint_error(": couldn't get registers\n"); 602 return; 603 } 604 605 if (sunxi_codec_clock_init(phandle) != 0) 606 return; 607 608 sc->sc_dev = self; 609 sc->sc_phandle = phandle; 610 sc->sc_baseaddr = addr; 611 sc->sc_bst = faa->faa_bst; 612 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 613 aprint_error(": couldn't map registers\n"); 614 return; 615 } 616 sc->sc_dmat = faa->faa_dmat; 617 LIST_INIT(&sc->sc_dmalist); 618 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 619 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 620 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 621 622 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 623 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 624 aprint_error(": couldn't setup channels\n"); 625 return; 626 } 627 628 /* Optional PA mute GPIO */ 629 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 630 631 aprint_naive("\n"); 632 aprint_normal(": %s\n", sc->sc_cfg->name); 633 634 /* Enable DAC */ 635 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 636 val |= DAC_DPC_EN_DA; 637 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 638 639 /* Initialize codec */ 640 if (sc->sc_cfg->init(sc) != 0) { 641 aprint_error_dev(self, "couldn't initialize codec\n"); 642 return; 643 } 644 645 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 646 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 647 sc->sc_format.validbits = 16; 648 sc->sc_format.precision = 16; 649 sc->sc_format.channels = 2; 650 sc->sc_format.channel_mask = AUFMT_STEREO; 651 sc->sc_format.frequency_type = 1; 652 sc->sc_format.frequency[0] = 48000; 653 654 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 655 } 656 657 CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 658 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 659 660 #ifdef DDB 661 void sunxicodec_dump(void); 662 663 void 664 sunxicodec_dump(void) 665 { 666 struct sunxi_codec_softc *sc; 667 device_t dev; 668 669 dev = device_find_by_driver_unit("sunxicodec", 0); 670 if (dev == NULL) 671 return; 672 sc = device_private(dev); 673 674 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 675 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 676 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 677 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 678 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 679 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 680 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 681 } 682 #endif 683