1 /* $NetBSD: sun9i_a80_ccu.c,v 1.4 2021/01/27 03:10:20 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: sun9i_a80_ccu.c,v 1.4 2021/01/27 03:10:20 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <dev/fdt/fdtvar.h>
39
40 #include <arm/sunxi/sunxi_ccu.h>
41 #include <arm/sunxi/sun9i_a80_ccu.h>
42
43 /* CCU */
44 #define PLL_C0CPUX_CTRL_REG 0x000
45 #define PLL_C1CPUX_CTRL_REG 0x004
46 #define PLL_PERIPH0_CTRL_REG 0x00c
47 #define PLL_PERIPH1_CTRL_REG 0x02c
48 #define CPU_CLK_SRC_REG 0x050
49 #define CPU_CLK_SRC_SELECT(cluster) __BIT((cluster) * 8)
50 #define GTBUS_CLK_CFG_REG 0x05c
51 #define AHB0_CLK_CFG_REG 0x060
52 #define AHB1_CLK_CFG_REG 0x064
53 #define AHB2_CLK_CFG_REG 0x068
54 #define APB0_CLK_CFG_REG 0x070
55 #define APB1_CLK_CFG_REG 0x074
56 #define PLL_STABLE_STATUS_REG 0x09c
57
58 /* CCU_SCLK */
59 #define SDMMC0_CLK_REG 0x410
60 #define SDMMC1_CLK_REG 0x414
61 #define SDMMC2_CLK_REG 0x418
62 #define BUS_CLK_GATING_REG0 0x580
63 #define BUS_CLK_GATING_REG1 0x584
64 #define BUS_CLK_GATING_REG2 0x588
65 #define BUS_CLK_GATING_REG3 0x590
66 #define BUS_CLK_GATING_REG4 0x594
67 #define BUS_SOFT_RST_REG0 0x5a0
68 #define BUS_SOFT_RST_REG1 0x5a4
69 #define BUS_SOFT_RST_REG2 0x5a8
70 #define BUS_SOFT_RST_REG3 0x5b0
71 #define BUS_SOFT_RST_REG4 0x5b4
72
73 static int sun9i_a80_ccu_match(device_t, cfdata_t, void *);
74 static void sun9i_a80_ccu_attach(device_t, device_t, void *);
75
76 static const struct device_compatible_entry compat_data[] = {
77 { .compat = "allwinner,sun9i-a80-ccu" },
78 DEVICE_COMPAT_EOL
79 };
80
81 CFATTACH_DECL_NEW(sunxi_a80_ccu, sizeof(struct sunxi_ccu_softc),
82 sun9i_a80_ccu_match, sun9i_a80_ccu_attach, NULL, NULL);
83
84 static struct sunxi_ccu_reset sun9i_a80_ccu_resets[] = {
85 SUNXI_CCU_RESET(A80_RST_BUS_FD, BUS_SOFT_RST_REG0, 0),
86 SUNXI_CCU_RESET(A80_RST_BUS_GPU_CTRL, BUS_SOFT_RST_REG0, 3),
87 SUNXI_CCU_RESET(A80_RST_BUS_SS, BUS_SOFT_RST_REG0, 5),
88 SUNXI_CCU_RESET(A80_RST_BUS_MMC, BUS_SOFT_RST_REG0, 8),
89 SUNXI_CCU_RESET(A80_RST_BUS_NAND1, BUS_SOFT_RST_REG0, 12),
90 SUNXI_CCU_RESET(A80_RST_BUS_NAND0, BUS_SOFT_RST_REG0, 13),
91 SUNXI_CCU_RESET(A80_RST_BUS_TS, BUS_SOFT_RST_REG0, 18),
92 SUNXI_CCU_RESET(A80_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20),
93 SUNXI_CCU_RESET(A80_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21),
94 SUNXI_CCU_RESET(A80_RST_BUS_SPI2, BUS_SOFT_RST_REG0, 22),
95 SUNXI_CCU_RESET(A80_RST_BUS_SPI3, BUS_SOFT_RST_REG0, 23),
96
97 SUNXI_CCU_RESET(A80_RST_BUS_OTG_PHY, BUS_SOFT_RST_REG1, 1),
98 SUNXI_CCU_RESET(A80_RST_BUS_GMAC, BUS_SOFT_RST_REG1, 17),
99 SUNXI_CCU_RESET(A80_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21),
100 SUNXI_CCU_RESET(A80_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22),
101 SUNXI_CCU_RESET(A80_RST_BUS_HSTIMER, BUS_SOFT_RST_REG1, 23),
102 SUNXI_CCU_RESET(A80_RST_BUS_DMA, BUS_SOFT_RST_REG1, 24),
103
104 SUNXI_CCU_RESET(A80_RST_BUS_LCD0, BUS_SOFT_RST_REG2, 0),
105 SUNXI_CCU_RESET(A80_RST_BUS_LCD1, BUS_SOFT_RST_REG2, 1),
106 SUNXI_CCU_RESET(A80_RST_BUS_CSI, BUS_SOFT_RST_REG2, 4),
107 SUNXI_CCU_RESET(A80_RST_BUS_DE, BUS_SOFT_RST_REG2, 7),
108 SUNXI_CCU_RESET(A80_RST_BUS_MP, BUS_SOFT_RST_REG2, 8),
109 SUNXI_CCU_RESET(A80_RST_BUS_GPU, BUS_SOFT_RST_REG2, 9),
110
111 SUNXI_CCU_RESET(A80_RST_BUS_LRADC, BUS_SOFT_RST_REG3, 15),
112 SUNXI_CCU_RESET(A80_RST_BUS_GPADC, BUS_SOFT_RST_REG3, 17),
113
114 SUNXI_CCU_RESET(A80_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
115 SUNXI_CCU_RESET(A80_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
116 SUNXI_CCU_RESET(A80_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2),
117 SUNXI_CCU_RESET(A80_RST_BUS_I2C3, BUS_SOFT_RST_REG4, 3),
118 SUNXI_CCU_RESET(A80_RST_BUS_I2C4, BUS_SOFT_RST_REG4, 4),
119 SUNXI_CCU_RESET(A80_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
120 SUNXI_CCU_RESET(A80_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
121 SUNXI_CCU_RESET(A80_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
122 SUNXI_CCU_RESET(A80_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
123 SUNXI_CCU_RESET(A80_RST_BUS_UART4, BUS_SOFT_RST_REG4, 20),
124 SUNXI_CCU_RESET(A80_RST_BUS_UART5, BUS_SOFT_RST_REG4, 21),
125 };
126
127 static const char *gtbus_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
128 static const char *ahb0_parents[] = { "gtbus", "pll_periph0", "pll_periph1" };
129 static const char *ahb1_parents[] = { "gtbus", "pll_periph0", "pll_periph1" };
130 static const char *ahb2_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
131 static const char *apb_parents[] = { "hosc", "pll_periph0" };
132 static const char *mmc_parents[] = { "hosc", "pll_periph0" };
133
134 static kmutex_t cpux_axi_cfg_lock;
135
136 static int
sun9i_a80_ccu_cpux_set_rate(struct sunxi_ccu_softc * sc,struct sunxi_ccu_clk * clk,u_int rate)137 sun9i_a80_ccu_cpux_set_rate(struct sunxi_ccu_softc *sc,
138 struct sunxi_ccu_clk *clk, u_int rate)
139 {
140 const int cluster = clk->u.nkmp.reg == PLL_C0CPUX_CTRL_REG ? 0 : 1;
141 struct sunxi_ccu_nkmp *nkmp = &clk->u.nkmp;
142 uint32_t val;
143 u_int n;
144
145 n = rate / 24000000;
146 if (n < 0x11 || n > 0xff)
147 return EINVAL;
148
149 /* Switch cluster to OSC24M clock */
150 mutex_enter(&cpux_axi_cfg_lock);
151 val = CCU_READ(sc, CPU_CLK_SRC_REG);
152 val &= ~CPU_CLK_SRC_SELECT(cluster);
153 CCU_WRITE(sc, CPU_CLK_SRC_REG, val);
154 mutex_exit(&cpux_axi_cfg_lock);
155
156 /* Set new PLL rate */
157 val = CCU_READ(sc, nkmp->reg);
158 val &= ~nkmp->n;
159 val |= __SHIFTIN(n, nkmp->n);
160 CCU_WRITE(sc, nkmp->reg, val);
161
162 /* Wait for PLL lock */
163 while ((CCU_READ(sc, PLL_STABLE_STATUS_REG) & nkmp->lock) == 0)
164 ;
165
166 /* Switch cluster back to CPUX PLL */
167 mutex_enter(&cpux_axi_cfg_lock);
168 val = CCU_READ(sc, CPU_CLK_SRC_REG);
169 val |= CPU_CLK_SRC_SELECT(cluster);
170 CCU_WRITE(sc, CPU_CLK_SRC_SELECT(cluster), val);
171 mutex_exit(&cpux_axi_cfg_lock);
172
173 return 0;
174 }
175
176 static struct sunxi_ccu_clk sun9i_a80_ccu_clks[] = {
177 [A80_CLK_C0CPUX] = {
178 .type = SUNXI_CCU_NKMP,
179 .base.name = "pll_c0cpux",
180 .u.nkmp.reg = PLL_C0CPUX_CTRL_REG,
181 .u.nkmp.parent = "hosc",
182 .u.nkmp.n = __BITS(15,8),
183 .u.nkmp.k = 0,
184 .u.nkmp.m = __BITS(1,0),
185 .u.nkmp.p = __BIT(16),
186 .u.nkmp.enable = __BIT(31),
187 .u.nkmp.flags = SUNXI_CCU_NKMP_SCALE_CLOCK |
188 SUNXI_CCU_NKMP_FACTOR_N_EXACT |
189 SUNXI_CCU_NKMP_FACTOR_P_X4,
190 .u.nkmp.lock = __BIT(1), /* PLL_STABLE_STATUS_REG */
191 .u.nkmp.table = NULL,
192 .enable = sunxi_ccu_nkmp_enable,
193 .get_rate = sunxi_ccu_nkmp_get_rate,
194 .set_rate = sun9i_a80_ccu_cpux_set_rate,
195 .get_parent = sunxi_ccu_nkmp_get_parent,
196 },
197
198 [A80_CLK_C1CPUX] = {
199 .type = SUNXI_CCU_NKMP,
200 .base.name = "pll_c1cpux",
201 .u.nkmp.reg = PLL_C1CPUX_CTRL_REG,
202 .u.nkmp.parent = "hosc",
203 .u.nkmp.n = __BITS(15,8),
204 .u.nkmp.k = 0,
205 .u.nkmp.m = __BITS(1,0),
206 .u.nkmp.p = __BIT(16),
207 .u.nkmp.enable = __BIT(31),
208 .u.nkmp.flags = SUNXI_CCU_NKMP_SCALE_CLOCK |
209 SUNXI_CCU_NKMP_FACTOR_N_EXACT |
210 SUNXI_CCU_NKMP_FACTOR_P_X4,
211 .u.nkmp.lock = __BIT(1), /* PLL_STABLE_STATUS_REG */
212 .u.nkmp.table = NULL,
213 .enable = sunxi_ccu_nkmp_enable,
214 .get_rate = sunxi_ccu_nkmp_get_rate,
215 .set_rate = sun9i_a80_ccu_cpux_set_rate,
216 .get_parent = sunxi_ccu_nkmp_get_parent,
217 },
218
219 SUNXI_CCU_NKMP(A80_CLK_PLL_PERIPH0, "pll_periph0", "hosc",
220 PLL_PERIPH0_CTRL_REG, /* reg */
221 __BITS(15,8), /* n */
222 __BIT(16), /* k */
223 0, /* m */
224 __BIT(18), /* p */
225 __BIT(31), /* enable */
226 SUNXI_CCU_NKMP_FACTOR_N_EXACT),
227 SUNXI_CCU_NKMP(A80_CLK_PLL_PERIPH1, "pll_periph1", "hosc",
228 PLL_PERIPH1_CTRL_REG, /* reg */
229 __BITS(15,8), /* n */
230 __BIT(16), /* k */
231 0, /* m */
232 __BIT(18), /* p */
233 __BIT(31), /* enable */
234 SUNXI_CCU_NKMP_FACTOR_N_EXACT),
235
236 SUNXI_CCU_DIV(A80_CLK_GTBUS, "gtbus", gtbus_parents,
237 GTBUS_CLK_CFG_REG, /* reg */
238 __BITS(1,0), /* div */
239 __BITS(25,24), /* sel */
240 0),
241
242 SUNXI_CCU_DIV(A80_CLK_AHB0, "ahb0", ahb0_parents,
243 AHB0_CLK_CFG_REG, /* reg */
244 __BITS(1,0), /* div */
245 __BITS(25,24), /* sel */
246 SUNXI_CCU_DIV_POWER_OF_TWO),
247
248 SUNXI_CCU_DIV(A80_CLK_AHB1, "ahb1", ahb1_parents,
249 AHB1_CLK_CFG_REG, /* reg */
250 __BITS(1,0), /* div */
251 __BITS(25,24), /* sel */
252 SUNXI_CCU_DIV_POWER_OF_TWO),
253
254 SUNXI_CCU_DIV(A80_CLK_AHB2, "ahb2", ahb2_parents,
255 AHB2_CLK_CFG_REG, /* reg */
256 __BITS(1,0), /* div */
257 __BITS(25,24), /* sel */
258 SUNXI_CCU_DIV_POWER_OF_TWO),
259
260 SUNXI_CCU_DIV(A80_CLK_APB0, "apb0", apb_parents,
261 APB0_CLK_CFG_REG, /* reg */
262 __BITS(1,0), /* div */
263 __BIT(24), /* sel */
264 SUNXI_CCU_DIV_POWER_OF_TWO),
265
266 SUNXI_CCU_NM(A80_CLK_APB1, "apb1", apb_parents,
267 APB1_CLK_CFG_REG, /* reg */
268 __BITS(17,16), /* n */
269 __BITS(4,0), /* m */
270 __BIT(24), /* sel */
271 0, /* enable */
272 SUNXI_CCU_NM_POWER_OF_TWO),
273
274 SUNXI_CCU_NM(A80_CLK_MMC0, "mmc0", mmc_parents,
275 SDMMC0_CLK_REG, /* reg */
276 __BITS(17,16), /* n */
277 __BITS(3,0), /* m */
278 __BITS(27,24), /* sel */
279 __BIT(31), /* enable */
280 SUNXI_CCU_NM_POWER_OF_TWO),
281 SUNXI_CCU_PHASE(A80_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0",
282 SDMMC0_CLK_REG, __BITS(22,20)),
283 SUNXI_CCU_PHASE(A80_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0",
284 SDMMC0_CLK_REG, __BITS(10,8)),
285 SUNXI_CCU_NM(A80_CLK_MMC1, "mmc1", mmc_parents,
286 SDMMC1_CLK_REG, /* reg */
287 __BITS(17,16), /* n */
288 __BITS(3,0), /* m */
289 __BITS(27,24), /* sel */
290 __BIT(31), /* enable */
291 SUNXI_CCU_NM_POWER_OF_TWO),
292 SUNXI_CCU_PHASE(A80_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1",
293 SDMMC1_CLK_REG, __BITS(22,20)),
294 SUNXI_CCU_PHASE(A80_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1",
295 SDMMC1_CLK_REG, __BITS(10,8)),
296 SUNXI_CCU_NM(A80_CLK_MMC2, "mmc2", mmc_parents,
297 SDMMC2_CLK_REG, /* reg */
298 __BITS(17,16), /* n */
299 __BITS(3,0), /* m */
300 __BITS(27,24), /* sel */
301 __BIT(31), /* enable */
302 SUNXI_CCU_NM_POWER_OF_TWO),
303 SUNXI_CCU_PHASE(A80_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2",
304 SDMMC2_CLK_REG, __BITS(22,20)),
305 SUNXI_CCU_PHASE(A80_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2",
306 SDMMC2_CLK_REG, __BITS(10,8)),
307
308 SUNXI_CCU_GATE(A80_CLK_BUS_FD, "ahb0-fd", "ahb0",
309 BUS_CLK_GATING_REG0, 0),
310 SUNXI_CCU_GATE(A80_CLK_BUS_GPU_CTRL, "ahb0-gpu-ctrl", "ahb0",
311 BUS_CLK_GATING_REG0, 3),
312 SUNXI_CCU_GATE(A80_CLK_BUS_SS, "ahb0-ss", "ahb0",
313 BUS_CLK_GATING_REG0, 5),
314 SUNXI_CCU_GATE(A80_CLK_BUS_MMC, "ahb0-mmc", "ahb0",
315 BUS_CLK_GATING_REG0, 8),
316 SUNXI_CCU_GATE(A80_CLK_BUS_NAND1, "ahb0-nand1", "ahb0",
317 BUS_CLK_GATING_REG0, 12),
318 SUNXI_CCU_GATE(A80_CLK_BUS_NAND0, "ahb0-nand0", "ahb0",
319 BUS_CLK_GATING_REG0, 13),
320 SUNXI_CCU_GATE(A80_CLK_BUS_TS, "ahb0-ts", "ahb0",
321 BUS_CLK_GATING_REG0, 18),
322 SUNXI_CCU_GATE(A80_CLK_BUS_SPI0, "ahb0-spi0", "ahb0",
323 BUS_CLK_GATING_REG0, 20),
324 SUNXI_CCU_GATE(A80_CLK_BUS_SPI1, "ahb0-spi1", "ahb0",
325 BUS_CLK_GATING_REG0, 21),
326 SUNXI_CCU_GATE(A80_CLK_BUS_SPI2, "ahb0-spi2", "ahb0",
327 BUS_CLK_GATING_REG0, 22),
328 SUNXI_CCU_GATE(A80_CLK_BUS_SPI3, "ahb0-spi3", "ahb0",
329 BUS_CLK_GATING_REG0, 23),
330
331 SUNXI_CCU_GATE(A80_CLK_BUS_USB, "ahb1-usb", "ahb1",
332 BUS_CLK_GATING_REG1, 1),
333 SUNXI_CCU_GATE(A80_CLK_BUS_GMAC, "ahb1-gmac", "ahb1",
334 BUS_CLK_GATING_REG1, 17),
335 SUNXI_CCU_GATE(A80_CLK_BUS_MSGBOX, "ahb1-msgbox", "ahb1",
336 BUS_CLK_GATING_REG1, 21),
337 SUNXI_CCU_GATE(A80_CLK_BUS_SPINLOCK, "ahb1-spinlock", "ahb1",
338 BUS_CLK_GATING_REG1, 22),
339 SUNXI_CCU_GATE(A80_CLK_BUS_HSTIMER, "ahb1-hstimer", "ahb1",
340 BUS_CLK_GATING_REG1, 23),
341 SUNXI_CCU_GATE(A80_CLK_BUS_DMA, "ahb1-dma", "ahb1",
342 BUS_CLK_GATING_REG1, 24),
343
344 SUNXI_CCU_GATE(A80_CLK_BUS_LCD0, "ahb2-lcd0", "ahb2",
345 BUS_CLK_GATING_REG2, 0),
346 SUNXI_CCU_GATE(A80_CLK_BUS_LCD1, "ahb2-lcd1", "ahb2",
347 BUS_CLK_GATING_REG2, 1),
348 SUNXI_CCU_GATE(A80_CLK_BUS_CSI, "ahb2-csi", "ahb2",
349 BUS_CLK_GATING_REG2, 4),
350 SUNXI_CCU_GATE(A80_CLK_BUS_DE, "ahb2-de", "ahb2",
351 BUS_CLK_GATING_REG2, 7),
352 SUNXI_CCU_GATE(A80_CLK_BUS_MP, "ahb2-mp", "ahb2",
353 BUS_CLK_GATING_REG2, 8),
354
355 SUNXI_CCU_GATE(A80_CLK_BUS_PIO, "apb0-pio", "apb0",
356 BUS_CLK_GATING_REG3, 5),
357 SUNXI_CCU_GATE(A80_CLK_BUS_LRADC, "apb0-lradc", "apb0",
358 BUS_CLK_GATING_REG3, 15),
359 SUNXI_CCU_GATE(A80_CLK_BUS_GPADC, "apb0-gpadc", "apb0",
360 BUS_CLK_GATING_REG3, 17),
361
362 SUNXI_CCU_GATE(A80_CLK_BUS_I2C0, "apb1-i2c0", "apb1",
363 BUS_CLK_GATING_REG4, 0),
364 SUNXI_CCU_GATE(A80_CLK_BUS_I2C1, "apb1-i2c1", "apb1",
365 BUS_CLK_GATING_REG4, 1),
366 SUNXI_CCU_GATE(A80_CLK_BUS_I2C2, "apb1-i2c2", "apb1",
367 BUS_CLK_GATING_REG4, 2),
368 SUNXI_CCU_GATE(A80_CLK_BUS_I2C3, "apb1-i2c3", "apb1",
369 BUS_CLK_GATING_REG4, 3),
370 SUNXI_CCU_GATE(A80_CLK_BUS_I2C4, "apb1-i2c4", "apb1",
371 BUS_CLK_GATING_REG4, 4),
372 SUNXI_CCU_GATE(A80_CLK_BUS_UART0, "apb1-uart0", "apb1",
373 BUS_CLK_GATING_REG4, 16),
374 SUNXI_CCU_GATE(A80_CLK_BUS_UART1, "apb1-uart1", "apb1",
375 BUS_CLK_GATING_REG4, 17),
376 SUNXI_CCU_GATE(A80_CLK_BUS_UART2, "apb1-uart2", "apb1",
377 BUS_CLK_GATING_REG4, 18),
378 SUNXI_CCU_GATE(A80_CLK_BUS_UART3, "apb1-uart3", "apb1",
379 BUS_CLK_GATING_REG4, 19),
380 SUNXI_CCU_GATE(A80_CLK_BUS_UART4, "apb1-uart4", "apb1",
381 BUS_CLK_GATING_REG4, 20),
382 SUNXI_CCU_GATE(A80_CLK_BUS_UART5, "apb1-uart5", "apb1",
383 BUS_CLK_GATING_REG4, 21),
384 };
385
386 static int
sun9i_a80_ccu_match(device_t parent,cfdata_t cf,void * aux)387 sun9i_a80_ccu_match(device_t parent, cfdata_t cf, void *aux)
388 {
389 struct fdt_attach_args * const faa = aux;
390
391 return of_compatible_match(faa->faa_phandle, compat_data);
392 }
393
394 static void
sun9i_a80_ccu_attach(device_t parent,device_t self,void * aux)395 sun9i_a80_ccu_attach(device_t parent, device_t self, void *aux)
396 {
397 struct sunxi_ccu_softc * const sc = device_private(self);
398 struct fdt_attach_args * const faa = aux;
399
400 sc->sc_dev = self;
401 sc->sc_phandle = faa->faa_phandle;
402 sc->sc_bst = faa->faa_bst;
403
404 sc->sc_resets = sun9i_a80_ccu_resets;
405 sc->sc_nresets = __arraycount(sun9i_a80_ccu_resets);
406
407 sc->sc_clks = sun9i_a80_ccu_clks;
408 sc->sc_nclks = __arraycount(sun9i_a80_ccu_clks);
409
410 mutex_init(&cpux_axi_cfg_lock, MUTEX_DEFAULT, IPL_HIGH);
411
412 if (sunxi_ccu_attach(sc) != 0)
413 return;
414
415 aprint_naive("\n");
416 aprint_normal(": A80 CCU\n");
417
418 sunxi_ccu_print(sc);
419 }
420