1 /* $NetBSD: sun50i_a64_ccu.c,v 1.24 2021/11/07 17:13:26 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.24 2021/11/07 17:13:26 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_a64_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_VIDEO0_CTRL_REG 0x010 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define PLL_PERIPH1_CTRL_REG 0x02c 48 #define PLL_VIDEO1_CTRL_REG 0x030 49 #define PLL_GPU_CTRL_REG 0x038 50 #define PLL_DE_CTRL_REG 0x048 51 #define CPUX_AXI_CFG_REG 0x050 52 #define AHB1_APB1_CFG_REG 0x054 53 #define APB2_CFG_REG 0x058 54 #define AHB2_CFG_REG 0x05c 55 #define BUS_CLK_GATING_REG0 0x060 56 #define BUS_CLK_GATING_REG1 0x064 57 #define BUS_CLK_GATING_REG2 0x068 58 #define BUS_CLK_GATING_REG3 0x06c 59 #define BUS_CLK_GATING_REG4 0x070 60 #define THS_CLK_REG 0x074 61 #define SDMMC0_CLK_REG 0x088 62 #define SDMMC1_CLK_REG 0x08c 63 #define SDMMC2_CLK_REG 0x090 64 #define CE_CLK_REG 0x09c 65 #define SPI0_CLK_REG 0x0a0 66 #define SPI1_CLK_REG 0x0a4 67 #define I2SPCM0_CLK_REG 0x0b0 68 #define I2SPCM1_CLK_REG 0x0b4 69 #define I2SPCM2_CLK_REG 0x0b8 70 #define USBPHY_CFG_REG 0x0cc 71 #define DRAM_CFG_REG 0x0f4 72 #define MBUS_RST_REG 0x0fc 73 #define DE_CLK_REG 0x104 74 #define TCON0_CLK_REG 0x118 75 #define TCON1_CLK_REG 0x11c 76 #define AC_DIG_CLK_REG 0x140 77 #define HDMI_CLK_REG 0x150 78 #define HDMI_SLOW_CLK_REG 0x154 79 #define GPU_CLK_REG 0x1a0 80 #define BUS_SOFT_RST_REG0 0x2c0 81 #define BUS_SOFT_RST_REG1 0x2c4 82 #define BUS_SOFT_RST_REG2 0x2c8 83 #define BUS_SOFT_RST_REG3 0x2d0 84 #define BUS_SOFT_RST_REG4 0x2d8 85 86 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *); 87 static void sun50i_a64_ccu_attach(device_t, device_t, void *); 88 89 static const struct device_compatible_entry compat_data[] = { 90 { .compat = "allwinner,sun50i-a64-ccu" }, 91 DEVICE_COMPAT_EOL 92 }; 93 94 CFATTACH_DECL_NEW(sunxi_a64_ccu, sizeof(struct sunxi_ccu_softc), 95 sun50i_a64_ccu_match, sun50i_a64_ccu_attach, NULL, NULL); 96 97 static struct sunxi_ccu_reset sun50i_a64_ccu_resets[] = { 98 SUNXI_CCU_RESET(A64_RST_USB_PHY0, USBPHY_CFG_REG, 0), 99 SUNXI_CCU_RESET(A64_RST_USB_PHY1, USBPHY_CFG_REG, 1), 100 SUNXI_CCU_RESET(A64_RST_USB_HSIC, USBPHY_CFG_REG, 2), 101 102 SUNXI_CCU_RESET(A64_RST_DRAM, DRAM_CFG_REG, 31), 103 104 SUNXI_CCU_RESET(A64_RST_MBUS, MBUS_RST_REG, 31), 105 106 SUNXI_CCU_RESET(A64_RST_BUS_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 107 SUNXI_CCU_RESET(A64_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 108 SUNXI_CCU_RESET(A64_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 109 SUNXI_CCU_RESET(A64_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 110 SUNXI_CCU_RESET(A64_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 111 SUNXI_CCU_RESET(A64_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 112 SUNXI_CCU_RESET(A64_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 113 SUNXI_CCU_RESET(A64_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 114 SUNXI_CCU_RESET(A64_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 115 SUNXI_CCU_RESET(A64_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 116 SUNXI_CCU_RESET(A64_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 117 SUNXI_CCU_RESET(A64_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 118 SUNXI_CCU_RESET(A64_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 119 SUNXI_CCU_RESET(A64_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 120 SUNXI_CCU_RESET(A64_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 121 SUNXI_CCU_RESET(A64_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 122 SUNXI_CCU_RESET(A64_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 123 SUNXI_CCU_RESET(A64_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 124 125 SUNXI_CCU_RESET(A64_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 126 SUNXI_CCU_RESET(A64_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 127 SUNXI_CCU_RESET(A64_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 128 SUNXI_CCU_RESET(A64_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 129 SUNXI_CCU_RESET(A64_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 130 SUNXI_CCU_RESET(A64_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 131 SUNXI_CCU_RESET(A64_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 132 SUNXI_CCU_RESET(A64_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 133 SUNXI_CCU_RESET(A64_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 134 SUNXI_CCU_RESET(A64_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 135 SUNXI_CCU_RESET(A64_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 136 SUNXI_CCU_RESET(A64_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 137 138 SUNXI_CCU_RESET(A64_RST_BUS_LVDS, BUS_SOFT_RST_REG2, 0), 139 140 SUNXI_CCU_RESET(A64_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 141 SUNXI_CCU_RESET(A64_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 142 SUNXI_CCU_RESET(A64_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 143 SUNXI_CCU_RESET(A64_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 144 SUNXI_CCU_RESET(A64_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 145 SUNXI_CCU_RESET(A64_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 146 147 SUNXI_CCU_RESET(A64_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 148 SUNXI_CCU_RESET(A64_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 149 SUNXI_CCU_RESET(A64_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 150 SUNXI_CCU_RESET(A64_RST_BUS_SCR, BUS_SOFT_RST_REG4, 5), 151 SUNXI_CCU_RESET(A64_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 152 SUNXI_CCU_RESET(A64_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 153 SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 154 SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 155 }; 156 157 static const char *cpux_parents[] = { "losc", "hosc", "pll_cpux", "pll_cpux" }; 158 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 159 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 160 static const char *apb1_parents[] = { "ahb1" }; 161 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 162 static const char *ce_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 163 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 164 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL }; 165 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 166 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" }; 167 static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" }; 168 static const char *spi_parents[] = { "hosc", "pll_periph0", "pll_periph1", NULL }; 169 static const char *tcon0_parents[] = { "pll_mipi", NULL, "pll_video0_2x", NULL }; 170 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL }; 171 static const char *gpu_parents[] = { "pll_gpu" }; 172 173 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = { 174 { 60000000, 9, 0, 0, 2 }, 175 { 66000000, 10, 0, 0, 2 }, 176 { 72000000, 11, 0, 0, 2 }, 177 { 78000000, 12, 0, 0, 2 }, 178 { 84000000, 13, 0, 0, 2 }, 179 { 90000000, 14, 0, 0, 2 }, 180 { 96000000, 15, 0, 0, 2 }, 181 { 102000000, 16, 0, 0, 2 }, 182 { 108000000, 17, 0, 0, 2 }, 183 { 114000000, 18, 0, 0, 2 }, 184 { 120000000, 9, 0, 0, 1 }, 185 { 132000000, 10, 0, 0, 1 }, 186 { 144000000, 11, 0, 0, 1 }, 187 { 156000000, 12, 0, 0, 1 }, 188 { 168000000, 13, 0, 0, 1 }, 189 { 180000000, 14, 0, 0, 1 }, 190 { 192000000, 15, 0, 0, 1 }, 191 { 204000000, 16, 0, 0, 1 }, 192 { 216000000, 17, 0, 0, 1 }, 193 { 228000000, 18, 0, 0, 1 }, 194 { 240000000, 9, 0, 0, 0 }, 195 { 264000000, 10, 0, 0, 0 }, 196 { 288000000, 11, 0, 0, 0 }, 197 { 312000000, 12, 0, 0, 0 }, 198 { 336000000, 13, 0, 0, 0 }, 199 { 360000000, 14, 0, 0, 0 }, 200 { 384000000, 15, 0, 0, 0 }, 201 { 408000000, 16, 0, 0, 0 }, 202 { 432000000, 17, 0, 0, 0 }, 203 { 456000000, 18, 0, 0, 0 }, 204 { 480000000, 19, 0, 0, 0 }, 205 { 504000000, 20, 0, 0, 0 }, 206 { 528000000, 21, 0, 0, 0 }, 207 { 552000000, 22, 0, 0, 0 }, 208 { 576000000, 23, 0, 0, 0 }, 209 { 600000000, 24, 0, 0, 0 }, 210 { 624000000, 25, 0, 0, 0 }, 211 { 648000000, 26, 0, 0, 0 }, 212 { 672000000, 27, 0, 0, 0 }, 213 { 696000000, 28, 0, 0, 0 }, 214 { 720000000, 29, 0, 0, 0 }, 215 { 768000000, 15, 1, 0, 0 }, 216 { 792000000, 10, 2, 0, 0 }, 217 { 816000000, 16, 1, 0, 0 }, 218 { 864000000, 17, 1, 0, 0 }, 219 { 912000000, 18, 1, 0, 0 }, 220 { 936000000, 12, 2, 0, 0 }, 221 { 960000000, 19, 1, 0, 0 }, 222 { 1008000000, 20, 1, 0, 0 }, 223 { 1056000000, 21, 1, 0, 0 }, 224 { 1080000000, 14, 2, 0, 0 }, 225 { 1104000000, 22, 1, 0, 0 }, 226 { 1152000000, 23, 1, 0, 0 }, 227 { 1200000000, 24, 1, 0, 0 }, 228 { 1224000000, 16, 2, 0, 0 }, 229 { 1248000000, 25, 1, 0, 0 }, 230 { 1296000000, 26, 1, 0, 0 }, 231 { 1344000000, 27, 1, 0, 0 }, 232 { 1368000000, 18, 2, 0, 0 }, 233 { 1440000000, 19, 2, 0, 0 }, 234 { 1512000000, 20, 2, 0, 0 }, 235 { 1536000000, 15, 3, 0, 0 }, 236 { 1584000000, 21, 2, 0, 0 }, 237 { 1632000000, 16, 3, 0, 0 }, 238 { 1656000000, 22, 2, 0, 0 }, 239 { 1728000000, 23, 2, 0, 0 }, 240 { 1800000000, 24, 2, 0, 0 }, 241 { 1872000000, 25, 2, 0, 0 }, 242 { 0 } 243 }; 244 245 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_ac_dig_table[] = { 246 { 24576000, 0x55, 0, 0x14, 0x3 }, 247 { 0 } 248 }; 249 250 static struct sunxi_ccu_clk sun50i_a64_ccu_clks[] = { 251 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_CPUX, "pll_cpux", "hosc", 252 PLL_CPUX_CTRL_REG, /* reg */ 253 __BITS(12,8), /* n */ 254 __BITS(5,4), /* k */ 255 __BITS(1,0), /* m */ 256 __BITS(17,16), /* p */ 257 __BIT(31), /* enable */ 258 __BIT(28), /* lock */ 259 sun50i_a64_cpux_table, /* table */ 260 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 261 262 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 263 PLL_PERIPH0_CTRL_REG, /* reg */ 264 __BITS(12,8), /* n */ 265 __BITS(5,4), /* k */ 266 0, /* m */ 267 __BITS(17,16), /* p */ 268 __BIT(31), /* enable */ 269 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 270 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 271 272 SUNXI_CCU_NKMP(A64_CLK_PLL_PERIPH1, "pll_periph1", "hosc", 273 PLL_PERIPH1_CTRL_REG, /* reg */ 274 __BITS(12,8), /* n */ 275 __BITS(5,4), /* k */ 276 0, /* m */ 277 __BITS(17,16), /* p */ 278 __BIT(31), /* enable */ 279 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 280 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_PERIPH1_2X, "pll_periph1_2x", "pll_periph1", 1, 2), 281 282 SUNXI_CCU_NKMP_TABLE(A64_CLK_PLL_AUDIO_BASE, "pll_audio_base", "hosc", 283 PLL_AUDIO_CTRL_REG, /* reg */ 284 __BITS(14,8), /* n */ 285 0, /* k */ 286 __BITS(4,0), /* m */ 287 __BITS(19,16), /* p */ 288 __BIT(31), /* enable */ 289 __BIT(28), /* lock */ 290 sun50i_a64_ac_dig_table, /* table */ 291 0), 292 293 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO, "pll_audio", "pll_audio_base", 1, 1), 294 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_2X, "pll_audio_2x", "pll_audio_base", 1, 2), 295 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_4X, "pll_audio_4x", "pll_audio_base", 1, 4), 296 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_AUDIO_8X, "pll_audio_8x", "pll_audio_base", 1, 8), 297 298 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO0, "pll_video0", "hosc", 299 PLL_VIDEO0_CTRL_REG, /* reg */ 300 __BITS(14,8), /* m */ 301 16, /* m_min */ 302 50, /* m_max */ 303 __BIT(24), /* div_en */ 304 __BIT(25), /* frac_sel */ 305 270000000, 297000000, /* frac values */ 306 __BITS(3,0), /* prediv */ 307 4, /* prediv_val */ 308 __BIT(31), /* enable */ 309 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 310 311 SUNXI_CCU_FIXED_FACTOR(A64_CLK_PLL_VIDEO0_2X, "pll_video0_2x", "pll_video0", 1, 2), 312 313 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_VIDEO1, "pll_video1", "hosc", 314 PLL_VIDEO1_CTRL_REG, /* reg */ 315 __BITS(14,8), /* m */ 316 16, /* m_min */ 317 50, /* m_max */ 318 __BIT(24), /* div_en */ 319 __BIT(25), /* frac_sel */ 320 270000000, 297000000, /* frac values */ 321 __BITS(3,0), /* prediv */ 322 4, /* prediv_val */ 323 __BIT(31), /* enable */ 324 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 325 326 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc", 327 PLL_DE_CTRL_REG, /* reg */ 328 __BITS(14,8), /* m */ 329 16, /* m_min */ 330 50, /* m_max */ 331 __BIT(24), /* div_en */ 332 __BIT(25), /* frac_sel */ 333 270000000, 297000000, /* frac values */ 334 __BITS(3,0), /* prediv */ 335 2, /* prediv_val */ 336 __BIT(31), /* enable */ 337 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 338 339 SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc", 340 PLL_GPU_CTRL_REG, /* reg */ 341 __BITS(14,8), /* m */ 342 1, /* m_min */ 343 128, /* m_max */ 344 __BIT(24), /* div_en */ 345 __BIT(25), /* frac_sel */ 346 270000000, 297000000, /* frac values */ 347 __BITS(3,0), /* prediv */ 348 4, /* prediv_val */ 349 __BIT(31), /* enable */ 350 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 351 352 SUNXI_CCU_MUX(A64_CLK_CPUX, "cpux", cpux_parents, 353 CPUX_AXI_CFG_REG, /* reg */ 354 __BITS(17,16), /* sel */ 355 0), 356 357 SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents, 358 AHB1_APB1_CFG_REG, /* reg */ 359 __BITS(7,6), /* prediv */ 360 __BIT(3), /* prediv_sel */ 361 __BITS(5,4), /* div */ 362 __BITS(13,12), /* sel */ 363 SUNXI_CCU_PREDIV_POWER_OF_TWO), 364 365 SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents, 366 AHB2_CFG_REG, /* reg */ 367 0, /* prediv */ 368 __BIT(1), /* prediv_sel */ 369 0, /* div */ 370 __BITS(1,0), /* sel */ 371 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 372 373 SUNXI_CCU_DIV(A64_CLK_APB1, "apb1", apb1_parents, 374 AHB1_APB1_CFG_REG, /* reg */ 375 __BITS(9,8), /* div */ 376 0, /* sel */ 377 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 378 379 SUNXI_CCU_NM(A64_CLK_APB2, "apb2", apb2_parents, 380 APB2_CFG_REG, /* reg */ 381 __BITS(17,16), /* n */ 382 __BITS(4,0), /* m */ 383 __BITS(25,24), /* sel */ 384 0, /* enable */ 385 SUNXI_CCU_NM_POWER_OF_TWO), 386 387 SUNXI_CCU_NM(A64_CLK_MMC0, "mmc0", mmc_parents, 388 SDMMC0_CLK_REG, /* reg */ 389 __BITS(17,16), /* n */ 390 __BITS(3,0), /* m */ 391 __BITS(25,24), /* sel */ 392 __BIT(31), /* enable */ 393 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 394 SUNXI_CCU_NM(A64_CLK_MMC1, "mmc1", mmc_parents, 395 SDMMC1_CLK_REG, /* reg */ 396 __BITS(17,16), /* n */ 397 __BITS(3,0), /* m */ 398 __BITS(25,24), /* sel */ 399 __BIT(31), /* enable */ 400 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 401 SUNXI_CCU_NM(A64_CLK_MMC2, "mmc2", mmc_parents, 402 SDMMC2_CLK_REG, /* reg */ 403 __BITS(17,16), /* n */ 404 __BITS(3,0), /* m */ 405 __BITS(25,24), /* sel */ 406 __BIT(31), /* enable */ 407 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO), 408 409 SUNXI_CCU_NM(A64_CLK_CE, "ce", ce_parents, 410 CE_CLK_REG, /* reg */ 411 __BITS(17,16), /* n */ 412 __BITS(3,0), /* m */ 413 __BITS(25,24), /* sel */ 414 __BIT(31), /* enable */ 415 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 416 417 SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents, 418 THS_CLK_REG, /* reg */ 419 __BITS(1,0), /* div */ 420 __BITS(25,24), /* sel */ 421 __BIT(31), /* enable */ 422 SUNXI_CCU_DIV_TIMES_TWO), 423 424 SUNXI_CCU_DIV_GATE(A64_CLK_DE, "de", de_parents, 425 DE_CLK_REG, /* reg */ 426 __BITS(3,0), /* div */ 427 __BITS(26,24), /* sel */ 428 __BIT(31), /* enable */ 429 0), 430 431 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 432 AC_DIG_CLK_REG, 31), 433 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x", 434 AC_DIG_CLK_REG, 30), 435 436 SUNXI_CCU_DIV_GATE(A64_CLK_HDMI, "hdmi", hdmi_parents, 437 HDMI_CLK_REG, /* reg */ 438 __BITS(3,0), /* div */ 439 __BITS(25,24), /* sel */ 440 __BIT(31), /* enable */ 441 0), 442 443 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 444 HDMI_SLOW_CLK_REG, 31), 445 446 SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents, 447 I2SPCM0_CLK_REG, /* reg */ 448 0, /* div */ 449 __BITS(17,16), /* sel */ 450 __BIT(31), /* enable */ 451 0), 452 SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents, 453 I2SPCM1_CLK_REG, /* reg */ 454 0, /* div */ 455 __BITS(17,16), /* sel */ 456 __BIT(31), /* enable */ 457 0), 458 SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents, 459 I2SPCM2_CLK_REG, /* reg */ 460 0, /* div */ 461 __BITS(17,16), /* sel */ 462 __BIT(31), /* enable */ 463 0), 464 465 SUNXI_CCU_NM(A64_CLK_SPI0, "spi0", spi_parents, 466 SPI0_CLK_REG, /* reg */ 467 __BITS(17,16), /* n */ 468 __BITS(3,0), /* m */ 469 __BITS(25,24), /* sel */ 470 __BIT(31), /* enable */ 471 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 472 473 SUNXI_CCU_NM(A64_CLK_SPI1, "spi1", spi_parents, 474 SPI1_CLK_REG, /* reg */ 475 __BITS(17,16), /* n */ 476 __BITS(3,0), /* m */ 477 __BITS(25,24), /* sel */ 478 __BIT(31), /* enable */ 479 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 480 481 SUNXI_CCU_DIV_GATE(A64_CLK_TCON0, "tcon0", tcon0_parents, 482 TCON0_CLK_REG, /* reg */ 483 0, /* div */ 484 __BITS(26,24), /* sel */ 485 __BIT(31), /* enable */ 486 0), 487 488 SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents, 489 TCON1_CLK_REG, /* reg */ 490 __BITS(3,0), /* div */ 491 __BITS(25,24), /* sel */ 492 __BIT(31), /* enable */ 493 0), 494 495 SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents, 496 GPU_CLK_REG, /* reg */ 497 __BITS(2,0), /* div */ 498 0, /* sel */ 499 __BIT(31), /* enable */ 500 0), 501 502 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 503 BUS_CLK_GATING_REG0, 1), 504 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 505 BUS_CLK_GATING_REG0, 5), 506 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 507 BUS_CLK_GATING_REG0, 6), 508 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 509 BUS_CLK_GATING_REG0, 8), 510 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 511 BUS_CLK_GATING_REG0, 9), 512 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 513 BUS_CLK_GATING_REG0, 10), 514 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 515 BUS_CLK_GATING_REG0, 13), 516 SUNXI_CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 517 BUS_CLK_GATING_REG0, 14), 518 SUNXI_CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 519 BUS_CLK_GATING_REG0, 17), 520 SUNXI_CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 521 BUS_CLK_GATING_REG0, 18), 522 SUNXI_CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 523 BUS_CLK_GATING_REG0, 19), 524 SUNXI_CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 525 BUS_CLK_GATING_REG0, 20), 526 SUNXI_CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 527 BUS_CLK_GATING_REG0, 21), 528 SUNXI_CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 529 BUS_CLK_GATING_REG0, 23), 530 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 531 BUS_CLK_GATING_REG0, 24), 532 SUNXI_CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 533 BUS_CLK_GATING_REG0, 25), 534 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 535 BUS_CLK_GATING_REG0, 28), 536 SUNXI_CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 537 BUS_CLK_GATING_REG0, 29), 538 539 SUNXI_CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 540 BUS_CLK_GATING_REG1, 0), 541 SUNXI_CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 542 BUS_CLK_GATING_REG1, 3), 543 SUNXI_CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 544 BUS_CLK_GATING_REG1, 4), 545 SUNXI_CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 546 BUS_CLK_GATING_REG1, 5), 547 SUNXI_CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 548 BUS_CLK_GATING_REG1, 8), 549 SUNXI_CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 550 BUS_CLK_GATING_REG1, 11), 551 SUNXI_CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 552 BUS_CLK_GATING_REG1, 12), 553 SUNXI_CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 554 BUS_CLK_GATING_REG1, 20), 555 SUNXI_CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 556 BUS_CLK_GATING_REG1, 21), 557 SUNXI_CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 558 BUS_CLK_GATING_REG1, 22), 559 560 SUNXI_CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 561 BUS_CLK_GATING_REG2, 0), 562 SUNXI_CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 563 BUS_CLK_GATING_REG2, 1), 564 SUNXI_CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 565 BUS_CLK_GATING_REG2, 5), 566 SUNXI_CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 567 BUS_CLK_GATING_REG2, 8), 568 SUNXI_CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 569 BUS_CLK_GATING_REG2, 12), 570 SUNXI_CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 571 BUS_CLK_GATING_REG2, 13), 572 SUNXI_CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 573 BUS_CLK_GATING_REG2, 14), 574 575 SUNXI_CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 576 BUS_CLK_GATING_REG3, 0), 577 SUNXI_CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 578 BUS_CLK_GATING_REG3, 1), 579 SUNXI_CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 580 BUS_CLK_GATING_REG3, 2), 581 SUNXI_CCU_GATE(A64_CLK_BUS_SCR, "bus-scr", "apb2", 582 BUS_CLK_GATING_REG3, 5), 583 SUNXI_CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 584 BUS_CLK_GATING_REG3, 16), 585 SUNXI_CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 586 BUS_CLK_GATING_REG3, 17), 587 SUNXI_CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 588 BUS_CLK_GATING_REG3, 18), 589 SUNXI_CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 590 BUS_CLK_GATING_REG3, 19), 591 SUNXI_CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 592 BUS_CLK_GATING_REG3, 20), 593 594 SUNXI_CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "hosc", 595 USBPHY_CFG_REG, 8), 596 SUNXI_CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "hosc", 597 USBPHY_CFG_REG, 9), 598 SUNXI_CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "hosc", 599 USBPHY_CFG_REG, 10), 600 SUNXI_CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12m", "hosc", 601 USBPHY_CFG_REG, 11), 602 SUNXI_CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "hosc", 603 USBPHY_CFG_REG, 16), 604 SUNXI_CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 605 USBPHY_CFG_REG, 17), 606 }; 607 608 static int 609 sun50i_a64_ccu_match(device_t parent, cfdata_t cf, void *aux) 610 { 611 struct fdt_attach_args * const faa = aux; 612 613 return of_compatible_match(faa->faa_phandle, compat_data); 614 } 615 616 static void 617 sun50i_a64_ccu_attach(device_t parent, device_t self, void *aux) 618 { 619 struct sunxi_ccu_softc * const sc = device_private(self); 620 struct fdt_attach_args * const faa = aux; 621 prop_dictionary_t prop = device_properties(self); 622 bool nomodeset; 623 624 sc->sc_dev = self; 625 sc->sc_phandle = faa->faa_phandle; 626 sc->sc_bst = faa->faa_bst; 627 628 sc->sc_resets = sun50i_a64_ccu_resets; 629 sc->sc_nresets = __arraycount(sun50i_a64_ccu_resets); 630 631 sc->sc_clks = sun50i_a64_ccu_clks; 632 sc->sc_nclks = __arraycount(sun50i_a64_ccu_clks); 633 634 if (sunxi_ccu_attach(sc) != 0) 635 return; 636 637 aprint_naive("\n"); 638 aprint_normal(": A64 CCU\n"); 639 640 nomodeset = false; 641 prop_dictionary_get_bool(prop, "nomodeset", &nomodeset); 642 if (!nomodeset) { 643 /* Set DE parent to PLL_DE */ 644 clk_set_parent(&sc->sc_clks[A64_CLK_DE].base, &sc->sc_clks[A64_CLK_PLL_DE].base); 645 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_DE].base, 420000000); 646 647 /* Set video PLLs to 297 MHz */ 648 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO0].base, 297000000); 649 clk_set_rate(&sc->sc_clks[A64_CLK_PLL_VIDEO1].base, 297000000); 650 651 /* Set TCON1 parent to PLL_VIDEO1(1X) */ 652 clk_set_parent(&sc->sc_clks[A64_CLK_TCON1].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base); 653 654 /* Set HDMI parent to PLL_VIDEO1(1X) */ 655 clk_set_parent(&sc->sc_clks[A64_CLK_HDMI].base, &sc->sc_clks[A64_CLK_PLL_VIDEO1].base); 656 } 657 658 sunxi_ccu_print(sc); 659 } 660