1 /* $NetBSD: mct.c,v 1.12 2017/06/11 16:21:41 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Reinoud Zandijk. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: mct.c,v 1.12 2017/06/11 16:21:41 jmcneill Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/kernel.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 #include <sys/kmem.h> 45 46 #include <prop/proplib.h> 47 48 #include <arm/samsung/exynos_reg.h> 49 #include <arm/samsung/exynos_var.h> 50 #include <arm/samsung/mct_reg.h> 51 #include <arm/samsung/mct_var.h> 52 53 #include <arm/cortex/gtmr_intr.h> 54 #include <arm/cortex/mpcore_var.h> 55 #include <arm/cortex/gtmr_var.h> 56 57 #include <dev/fdt/fdtvar.h> 58 #include <arm/fdt/arm_fdtvar.h> 59 60 static int mct_match(device_t, cfdata_t, void *); 61 static void mct_attach(device_t, device_t, void *); 62 63 CFATTACH_DECL_NEW(exyo_mct, 0, mct_match, mct_attach, NULL, NULL); 64 65 static inline uint32_t 66 mct_read_global(struct mct_softc *sc, bus_size_t o) 67 { 68 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 69 } 70 71 static inline void 72 mct_write_global(struct mct_softc *sc, bus_size_t o, uint32_t v) 73 { 74 bus_size_t wreg; 75 uint32_t bit; 76 int i; 77 78 /* do the write */ 79 bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v); 80 // printf("%s: write %#x at %#x\n", 81 // __func__, ((uint32_t) sc->sc_bsh + (uint32_t) o), v); 82 83 /* dependent on the write address, do the ack dance */ 84 if (o == MCT_G_CNT_L || o == MCT_G_CNT_U) { 85 wreg = MCT_G_CNT_WSTAT; 86 bit = (o == MCT_G_CNT_L) ? G_CNT_WSTAT_L : G_CNT_WSTAT_U; 87 } else { 88 wreg = MCT_G_WSTAT; 89 switch (o) { 90 case MCT_G_COMP0_L: 91 bit = G_WSTAT_COMP0_L; 92 break; 93 case MCT_G_COMP0_U: 94 bit = G_WSTAT_COMP0_U; 95 break; 96 case MCT_G_COMP0_ADD_INCR: 97 bit = G_WSTAT_ADD_INCR; 98 break; 99 case MCT_G_TCON: 100 bit = G_WSTAT_TCON; 101 break; 102 default: 103 /* all other registers */ 104 return; 105 } 106 } 107 108 /* wait for ack */ 109 for (i = 0; i < 10000000; i++) { 110 /* value accepted by the hardware/hal ? */ 111 if (mct_read_global(sc, wreg) & bit) { 112 /* ack */ 113 bus_space_write_4(sc->sc_bst, sc->sc_bsh, wreg, bit); 114 return; 115 } 116 } 117 panic("MCT hangs after writing %#x at %#x", v, (uint32_t) o); 118 } 119 120 static void 121 mct_fdt_cpu_hatch(void *priv, struct cpu_info *ci) 122 { 123 gtmr_init_cpu_clock(ci); 124 } 125 126 static int 127 mct_match(device_t parent, cfdata_t cf, void *aux) 128 { 129 const char * const compatible[] = { "samsung,exynos4210-mct", 130 NULL }; 131 132 struct fdt_attach_args * const faa = aux; 133 return of_match_compatible(faa->faa_phandle, compatible); 134 } 135 136 static void 137 mct_attach(device_t parent, device_t self, void *aux) 138 { 139 struct mct_softc * const sc = &mct_sc; 140 struct fdt_attach_args * const faa = aux; 141 bus_addr_t addr; 142 bus_size_t size; 143 int error; 144 145 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 146 aprint_error(": couldn't get registers\n"); 147 return; 148 } 149 150 self->dv_private = sc; 151 sc->sc_dev = self; 152 sc->sc_bst = faa->faa_bst; 153 sc->sc_freq = EXYNOS_F_IN_FREQ; 154 155 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 156 if (error) { 157 aprint_error(": couldn't map %#llx: %d", 158 (uint64_t)addr, error); 159 return; 160 } 161 162 aprint_naive("\n"); 163 aprint_normal(": Exynos SoC multi core timer (64 bits)\n"); 164 165 /* Start the timer */ 166 uint32_t tcon = mct_read_global(sc, MCT_G_TCON); 167 tcon |= G_TCON_START; 168 mct_write_global(sc, MCT_G_TCON, tcon); 169 170 /* Attach ARMv7 generic timer */ 171 struct mpcore_attach_args mpcaa = { 172 .mpcaa_name = "armgtmr", 173 .mpcaa_irq = IRQ_GTMR_PPI_VTIMER 174 }; 175 176 config_found(self, &mpcaa, NULL); 177 178 arm_fdt_cpu_hatch_register(self, mct_fdt_cpu_hatch); 179 } 180