1 /* $NetBSD: exynos_platform.c,v 1.40 2023/04/07 08:55:30 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_arm_debug.h" 30 #include "opt_console.h" 31 #include "opt_exynos.h" 32 #include "opt_multiprocessor.h" 33 #include "opt_console.h" 34 35 #include "ukbd.h" 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: exynos_platform.c,v 1.40 2023/04/07 08:55:30 skrll Exp $"); 39 40 #define EXYNOS_CORE_VBASE KERNEL_IO_VBASE 41 42 /* 43 * Booting a CA7 core on Exynos5422 is currently broken, disable starting CA7 secondaries. 44 */ 45 #define EXYNOS5422_DISABLE_CA7_CLUSTER 46 47 #include <sys/param.h> 48 #include <sys/bus.h> 49 #include <sys/cpu.h> 50 #include <sys/device.h> 51 #include <sys/termios.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <machine/bootconfig.h> 58 #include <arm/cpufunc.h> 59 60 #include <arm/samsung/exynos_reg.h> 61 #include <arm/samsung/exynos_var.h> 62 #include <arm/samsung/mct_var.h> 63 #include <arm/samsung/sscom_reg.h> 64 65 #include <evbarm/fdt/platform.h> 66 #include <evbarm/fdt/machdep.h> 67 68 #include <arm/fdt/arm_fdtvar.h> 69 70 #include <libfdt.h> 71 72 void exynos_platform_early_putchar(char); 73 74 #define EXYNOS5800_PMU_BASE 0x10040000 75 #define EXYNOS5800_PMU_SIZE 0x20000 76 #define EXYNOS5800_PMU_SWRESET 0x0400 77 #define EXYNOS5800_PMU_KFC_ETM_RESET(n) __BIT(20 + (n)) 78 #define EXYNOS5800_PMU_KFC_CORE_RESET(n) __BIT(8 + (n)) 79 #define EXYNOS5800_PMU_SPARE2 0x0908 80 #define EXYNOS5800_PMU_SPARE3 0x090c 81 #define EXYNOS5800_PMU_SWRESET_KFC_SEL 0x3 82 #define EXYNOS5800_PMU_CORE_CONFIG(n) (0x2000 + 0x80 * (n)) 83 #define EXYNOS5800_PMU_CORE_STATUS(n) (0x2004 + 0x80 * (n)) 84 #define EXYNOS5800_PMU_CORE_POWER_EN 0x3 85 #define EXYNOS5800_PMU_COMMON_CONFIG(n) (0x2500 + 0x80 * (n)) 86 #define EXYNOS5800_PMU_COMMON_POWER_EN 0x3 87 #define EXYNOS5800_PMU_COMMON_OPTION(n) (0x2508 + 0x80 * (n)) 88 #define EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE __BIT(30) 89 #define EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE __BIT(29) 90 #define EXYNOS5800_PMU_AUTO_CORE_DOWN __BIT(9) 91 92 #define EXYNOS5800_SYSRAM_BASE 0x02073000 93 #define EXYNOS5800_SYSRAM_SIZE 0x1000 94 #define EXYNOS5800_SYSRAM_HOTPLUG 0x001c 95 96 static int 97 exynos5800_mpstart(void) 98 { 99 int ret = 0; 100 #if defined(MULTIPROCESSOR) 101 bus_space_tag_t bst = &armv7_generic_bs_tag; 102 bus_space_handle_t pmu_bsh, sysram_bsh; 103 uint64_t mpidr, bp_mpidr; 104 uint32_t val, started = 0; 105 u_int cpuindex, n; 106 int child; 107 108 bus_space_map(bst, EXYNOS5800_PMU_BASE, EXYNOS5800_PMU_SIZE, 0, &pmu_bsh); 109 bus_space_map(bst, EXYNOS5800_SYSRAM_BASE, EXYNOS5800_SYSRAM_SIZE, 0, &sysram_bsh); 110 111 const int cpus = OF_finddevice("/cpus"); 112 if (cpus == -1) { 113 aprint_error("%s: no /cpus node found\n", __func__); 114 return ret; 115 } 116 117 /* MPIDR affinity levels of boot processor. */ 118 bp_mpidr = cpu_mpidr_aff_read(); 119 120 /* Setup KFC reset */ 121 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE3, EXYNOS5800_PMU_SWRESET_KFC_SEL); 122 123 const uint32_t option = EXYNOS5800_PMU_USE_L2_COMMON_UP_STATE | 124 EXYNOS5800_PMU_USE_ARM_CORE_DOWN_STATE | 125 EXYNOS5800_PMU_AUTO_CORE_DOWN; 126 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0)); 127 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(0), val | option); 128 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1)); 129 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_OPTION(1), val | option); 130 131 bus_space_write_4(bst, sysram_bsh, EXYNOS5800_SYSRAM_HOTPLUG, KERN_VTOPHYS((vaddr_t)cpu_mpstart)); 132 dsb(sy); 133 134 /* Power on clusters */ 135 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(0), 136 EXYNOS5800_PMU_COMMON_POWER_EN); 137 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_COMMON_CONFIG(1), 138 EXYNOS5800_PMU_COMMON_POWER_EN); 139 140 /* Boot APs */ 141 cpuindex = 1; 142 for (child = OF_child(cpus); child; child = OF_peer(child)) { 143 if (fdtbus_get_reg64(child, 0, &mpidr, NULL) != 0) 144 continue; 145 146 if (mpidr == bp_mpidr) 147 continue; /* BP already started */ 148 149 const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1); 150 const u_int aff0 = __SHIFTOUT(mpidr, MPIDR_AFF0); 151 const u_int cpu = cluster * 4 + aff0; 152 153 #if defined(EXYNOS5422_DISABLE_CA7_CLUSTER) 154 if (cluster == 1) 155 continue; 156 #endif 157 158 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu)); 159 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_CONFIG(cpu), 160 EXYNOS5800_PMU_CORE_POWER_EN); 161 162 for (n = 0x100000; n > 0; n--) { 163 val = bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_CORE_STATUS(cpu)); 164 if ((val & EXYNOS5800_PMU_CORE_POWER_EN) == EXYNOS5800_PMU_CORE_POWER_EN) { 165 started |= __BIT(cpuindex); 166 break; 167 } 168 } 169 if (n == 0) 170 aprint_error("cpu%d: WARNING: AP failed to power on\n", cpuindex); 171 172 if (cluster == 1 && __SHIFTOUT(bp_mpidr, MPIDR_AFF1) == 1) { 173 while (bus_space_read_4(bst, pmu_bsh, EXYNOS5800_PMU_SPARE2) == 0) 174 ; 175 bus_space_write_4(bst, pmu_bsh, EXYNOS5800_PMU_SWRESET, 176 EXYNOS5800_PMU_KFC_CORE_RESET(aff0) | 177 EXYNOS5800_PMU_KFC_ETM_RESET(aff0)); 178 } 179 180 /* Wait for AP to start */ 181 for (n = 0x100000; n > 0; n--) { 182 if (cpu_hatched_p(cpuindex)) 183 break; 184 } 185 if (n == 0) { 186 ret++; 187 aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex); 188 } 189 190 cpuindex++; 191 } 192 193 bus_space_unmap(bst, sysram_bsh, EXYNOS5800_SYSRAM_SIZE); 194 bus_space_unmap(bst, pmu_bsh, EXYNOS5800_PMU_SIZE); 195 #endif 196 return ret; 197 } 198 199 static struct device_compatible_entry mp_compat_data[] = { 200 { .compat = "samsung,exynos5800", .data = exynos5800_mpstart }, 201 DEVICE_COMPAT_EOL 202 }; 203 204 static int 205 exynos_platform_mpstart(void) 206 { 207 208 int (*mp_start)(void) = NULL; 209 210 const struct device_compatible_entry *cd = 211 of_compatible_lookup(OF_finddevice("/"), mp_compat_data); 212 if (cd) 213 mp_start = cd->data; 214 215 if (mp_start) 216 return mp_start(); 217 218 return 0; 219 } 220 221 static void 222 exynos_platform_init_attach_args(struct fdt_attach_args *faa) 223 { 224 extern struct bus_space armv7_generic_bs_tag; 225 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 226 227 faa->faa_bst = &armv7_generic_bs_tag; 228 faa->faa_dmat = &arm_generic_dma_tag; 229 } 230 231 void __noasan 232 exynos_platform_early_putchar(char c) 233 { 234 #ifdef CONSADDR 235 #define CONSADDR_VA (CONSADDR - EXYNOS_CORE_PBASE + EXYNOS_CORE_VBASE) 236 237 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 238 (volatile uint32_t *)CONSADDR_VA : 239 (volatile uint32_t *)CONSADDR; 240 241 while ((uartaddr[SSCOM_UFSTAT / 4] & UFSTAT_TXFULL) != 0) 242 ; 243 244 uartaddr[SSCOM_UTXH / 4] = c; 245 #endif 246 } 247 248 static void 249 exynos_platform_device_register(device_t self, void *aux) 250 { 251 exynos_device_register(self, aux); 252 } 253 254 static void 255 exynos5_platform_reset(void) 256 { 257 bus_space_tag_t bst = &armv7_generic_bs_tag; 258 bus_space_handle_t bsh; 259 260 bus_space_map(bst, EXYNOS5800_PMU_BASE + EXYNOS5800_PMU_SWRESET, 4, 0, &bsh); 261 bus_space_write_4(bst, bsh, 0, 1); 262 } 263 264 static u_int 265 exynos_platform_uart_freq(void) 266 { 267 return EXYNOS_UART_FREQ; 268 } 269 270 271 #if defined(SOC_EXYNOS4) 272 static const struct pmap_devmap * 273 exynos4_platform_devmap(void) 274 { 275 static const struct pmap_devmap devmap[] = { 276 DEVMAP_ENTRY(EXYNOS_CORE_VBASE, 277 EXYNOS_CORE_PBASE, 278 EXYNOS4_CORE_SIZE), 279 DEVMAP_ENTRY(EXYNOS4_AUDIOCORE_VBASE, 280 EXYNOS4_AUDIOCORE_PBASE, 281 EXYNOS4_AUDIOCORE_SIZE), 282 DEVMAP_ENTRY_END 283 }; 284 285 return devmap; 286 } 287 288 static void 289 exynos4_platform_bootstrap(void) 290 { 291 292 exynos_bootstrap(4); 293 294 #if defined(MULTIPROCESSOR) 295 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU); 296 #endif 297 } 298 299 static const struct fdt_platform exynos4_platform = { 300 .fp_devmap = exynos4_platform_devmap, 301 // .fp_mpstart = exynos4_mpstart, 302 .fp_bootstrap = exynos4_platform_bootstrap, 303 .fp_init_attach_args = exynos_platform_init_attach_args, 304 .fp_device_register = exynos_platform_device_register, 305 .fp_reset = exynos5_platform_reset, 306 .fp_delay = mct_delay, 307 .fp_uart_freq = exynos_platform_uart_freq, 308 }; 309 310 FDT_PLATFORM(exynos4, "samsung,exynos4", &exynos4_platform); 311 #endif 312 313 314 #if defined(SOC_EXYNOS5) 315 static const struct pmap_devmap * 316 exynos5_platform_devmap(void) 317 { 318 static const struct pmap_devmap devmap[] = { 319 DEVMAP_ENTRY(EXYNOS_CORE_VBASE, 320 EXYNOS_CORE_PBASE, 321 EXYNOS5_CORE_SIZE), 322 DEVMAP_ENTRY(EXYNOS5_AUDIOCORE_VBASE, 323 EXYNOS5_AUDIOCORE_PBASE, 324 EXYNOS5_AUDIOCORE_SIZE), 325 DEVMAP_ENTRY(EXYNOS5_SYSRAM_VBASE, 326 EXYNOS5_SYSRAM_PBASE, 327 EXYNOS5_SYSRAM_SIZE), 328 DEVMAP_ENTRY_END 329 }; 330 331 return devmap; 332 } 333 334 static void 335 exynos5_platform_bootstrap(void) 336 { 337 338 exynos_bootstrap(5); 339 340 #if defined(MULTIPROCESSOR) && defined(EXYNOS5422_DISABLE_CA7_CLUSTER) 341 const struct device_compatible_entry *cd = 342 of_compatible_lookup(OF_finddevice("/"), mp_compat_data); 343 if (cd && cd->data == exynos5800_mpstart) { 344 void *fdt_data = __UNCONST(fdtbus_get_data()); 345 int cpu_off, cpus_off, len; 346 347 cpus_off = fdt_path_offset(fdt_data, "/cpus"); 348 if (cpus_off < 0) 349 return; 350 351 fdt_for_each_subnode(cpu_off, fdt_data, cpus_off) { 352 const void *prop = fdt_getprop(fdt_data, cpu_off, "reg", &len); 353 if (len != 4) 354 continue; 355 const uint32_t mpidr = be32dec(prop); 356 if (mpidr != cpu_mpidr_aff_read() && __SHIFTOUT(mpidr, MPIDR_AFF1) == 1) 357 fdt_setprop_string(fdt_data, cpu_off, "status", "fail"); 358 } 359 } 360 #endif 361 362 arm_fdt_cpu_bootstrap(); 363 } 364 365 static const struct fdt_platform exynos5_platform = { 366 .fp_devmap = exynos5_platform_devmap, 367 .fp_bootstrap = exynos5_platform_bootstrap, 368 .fp_mpstart = exynos_platform_mpstart, 369 .fp_init_attach_args = exynos_platform_init_attach_args, 370 .fp_device_register = exynos_platform_device_register, 371 .fp_reset = exynos5_platform_reset, 372 .fp_delay = mct_delay, 373 .fp_uart_freq = exynos_platform_uart_freq, 374 }; 375 376 FDT_PLATFORM(exynos5, "samsung,exynos5", &exynos5_platform); 377 #endif 378