xref: /netbsd-src/sys/arch/arm/sa11x0/sa1111.c (revision 27527e67bbdf8d9ec84fd58803048ed6d181ece2)
1 /*      $NetBSD: sa1111.c,v 1.15 2006/01/03 23:14:23 peter Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by IWAMOTO Toshihiro.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *        This product includes software developed by the NetBSD
21  *        Foundation, Inc. and its contributors.
22  * 4. Neither the name of The NetBSD Foundation nor the names of its
23  *    contributors may be used to endorse or promote products derived
24  *    from this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 /*
40  * TODO:
41  *   - introduce bus abstraction to support SA1101
42  */
43 
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: sa1111.c,v 1.15 2006/01/03 23:14:23 peter Exp $");
46 
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/types.h>
50 #include <sys/conf.h>
51 #include <sys/device.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
54 #include <sys/uio.h>
55 
56 #include <machine/bus.h>
57 
58 #include <arm/sa11x0/sa11x0_reg.h>
59 #include <arm/sa11x0/sa11x0_var.h>
60 #include <arm/sa11x0/sa11x0_gpioreg.h>
61 #include <arm/sa11x0/sa1111_reg.h>
62 #include <arm/sa11x0/sa1111_var.h>
63 
64 #include "locators.h"
65 
66 static	int	sa1111_print(void *, const char *);
67 
68 static void	sacc_intr_calculatemasks(struct sacc_softc *);
69 static void	sacc_intr_setpolarity(sacc_chipset_tag_t *, int , int);
70 int		sacc_intr(void *);
71 
72 #if !defined(__HAVE_GENERIC_SOFT_INTERRUPTS)
73 void *softintr_establish(int, int (*)(void *), void *);
74 void softintr_schedule(void *);
75 #endif
76 
77 #ifdef INTR_DEBUG
78 #define DPRINTF(arg)	printf arg
79 #else
80 #define DPRINTF(arg)
81 #endif
82 
83 int
84 sacc_probe(parent, match, aux)
85 	struct device *parent;
86 	struct cfdata *match;
87 	void *aux;
88 {
89 	struct sa11x0_attach_args *sa = aux;
90 	bus_space_handle_t ioh;
91 	u_int32_t skid;
92 
93 	if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &ioh))
94 		return (0);
95 
96 	skid = bus_space_read_4(sa->sa_iot, ioh, SACCSBI_SKID);
97 	bus_space_unmap(sa->sa_iot, ioh, sa->sa_size);
98 
99 	if ((skid & 0xffffff00) != 0x690cc200)
100 		return (0);
101 
102 	return (1);
103 }
104 
105 
106 int
107 sa1111_search(parent, cf, ldesc, aux)
108 	struct device *parent;
109 	struct cfdata *cf;
110 	const int *ldesc;
111 	void *aux;
112 {
113 	struct sa1111_attach_args aa;
114 
115 	aa.sa_addr = cf->cf_loc[SACCCF_ADDR];
116 	aa.sa_size = cf->cf_loc[SACCCF_SIZE];
117 	aa.sa_intr = cf->cf_loc[SACCCF_INTR];
118 #if 0
119 	aa.sa_membase = cf->cf_loc[SACCCF_MEMBASE];
120 	aa.sa_memsize = cf->cf_loc[SACCCF_MEMSIZE];
121 #endif
122 
123         if (config_match(parent, cf, &aa) > 0)
124                 config_attach(parent, cf, &aa, sa1111_print);
125 
126         return 0;
127 }
128 
129 static int
130 sa1111_print(aux, name)
131 	void *aux;
132 	const char *name;
133 {
134 	return (UNCONF);
135 }
136 
137 
138 void *
139 sacc_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
140 	sacc_chipset_tag_t *ic;
141 	int irq, type, level;
142 	int (*ih_fun)(void *);
143 	void *ih_arg;
144 {
145 	int s;
146 	struct sacc_softc *sc = (struct sacc_softc *)ic;
147 	struct sacc_intrhand **p, *ih;
148 
149 	/* no point in sleeping unless someone can free memory. */
150 	ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
151 	if (ih == NULL)
152 		panic("sacc_intr_establish: can't malloc handler info");
153 
154 	if (irq < 0 || irq > SACCIC_LEN ||
155 	    ! (type == IST_EDGE_RAISE || type == IST_EDGE_FALL))
156 		panic("sacc_intr_establish: bogus irq or type");
157 
158 	if (sc->sc_intrhand[irq] == NULL) {
159 		sacc_intr_setpolarity(ic, irq, type);
160 		sc->sc_intrtype[irq] = type;
161 	} else if (sc->sc_intrtype[irq] != type)
162 		/* XXX we should be able to share raising and
163 		 * falling edge intrs */
164 		panic("sacc_intr_establish: type must be unique");
165 
166 	/* install intr handler */
167 #if defined(__GENERIC_SOFT_INTERRUPTS_ALL_LEVELS) || \
168 	!defined(__HAVE_GENERIC_SOFT_INTERRUPTS)
169 
170 	ih->ih_soft = softintr_establish(level, (void (*)(void *)) ih_fun,
171 					 ih_arg);
172 #else
173 	/* map interrupt level to appropriate softinterrupt level */
174 	if (level >= IPL_SOFTSERIAL)
175 		level = IPL_SOFTSERIAL;
176 	else if(level >= IPL_SOFTNET)
177 		level = IPL_SOFTNET;
178 	ih->ih_soft = softintr_establish(level, (void (*)(void *)) ih_fun,
179 					 ih_arg);
180 #endif
181 	ih->ih_irq = irq;
182 	ih->ih_next = NULL;
183 
184 	s = splhigh();
185 	for(p = &sc->sc_intrhand[irq]; *p; p = &(*p)->ih_next)
186 		;
187 
188 	*p = ih;
189 
190 	sacc_intr_calculatemasks(sc);
191 	splx(s);
192 
193 	return(ih);
194 }
195 
196 void
197 sacc_intr_disestablish(ic, arg)
198 	sacc_chipset_tag_t *ic;
199 	void *arg;
200 {
201 	int irq, s;
202 	struct sacc_softc *sc = (struct sacc_softc *)ic;
203 	struct sacc_intrhand *ih, **p;
204 
205 	ih = (struct sacc_intrhand *)arg;
206 	irq = ih->ih_irq;
207 
208 #ifdef DIAGNOSTIC
209 	if (irq < 0 || irq > SACCIC_LEN)
210 		panic("sacc_intr_disestablish: bogus irq");
211 #endif
212 
213 	s = splhigh();
214 
215 	for(p = &sc->sc_intrhand[irq];; p = &(*p)->ih_next) {
216 		if (*p == NULL)
217 			panic("sacc_intr_disestablish: handler not registered");
218 		if (*p == ih)
219 			break;
220 	}
221 	*p = (*p)->ih_next;
222 
223 	sacc_intr_calculatemasks(sc);
224 	splx(s);
225 
226 	free(ih, M_DEVBUF);
227 }
228 
229 void
230 sacc_intr_setpolarity(ic, irq, type)
231 	sacc_chipset_tag_t *ic;
232 	int irq;
233 	int type;
234 {
235 	struct sacc_softc *sc = (struct sacc_softc *)ic;
236 	int s;
237 	u_int32_t pol, mask;
238 	int addr;
239 
240 	if (irq >= 32) {
241 		addr = SACCIC_INTPOL1;
242 		irq -= 32;
243 	} else
244 		addr = SACCIC_INTPOL0;
245 
246 	mask = (1 << irq);
247 
248 	s = splhigh();
249 	pol = bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr);
250 	if (type == IST_EDGE_RAISE)
251 		pol &= ~mask;
252 	else
253 		pol |= mask;
254 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, pol);
255 	splx(s);
256 }
257 
258 void
259 sacc_intr_calculatemasks(sc)
260 	struct sacc_softc *sc;
261 {
262 	int irq;
263 
264 	sc->sc_imask.lo = 0;
265 	sc->sc_imask.hi = 0;
266 	for(irq = 0; irq < 32; irq++)
267 		if (sc->sc_intrhand[irq])
268 			sc->sc_imask.lo |= (1 << irq);
269 	for(irq = 0; irq < SACCIC_LEN - 32; irq++)
270 		if (sc->sc_intrhand[irq + 32])
271 			sc->sc_imask.hi |= (1 << irq);
272 
273 
274 	/* XXX this should not be done here */
275 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0,
276 			  sc->sc_imask.lo);
277 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1,
278 			  sc->sc_imask.hi);
279 	DPRINTF(("sacc_intr_calculatemasks: %x %x\n", sc->sc_imask.lo,
280 	    sc->sc_imask.hi));
281 }
282