1 /* $NetBSD: s3c2800_pci.c,v 1.23 2017/04/19 12:34:14 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * derived from evbarm/ifpga/ifpga_pci.c 35 */ 36 37 /* 38 * Copyright (c) 2001 ARM Ltd 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. The name of the company may not be used to endorse or promote 50 * products derived from this software without specific prior written 51 * permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * Copyright (c) 1997,1998 Mark Brinicombe. 66 * Copyright (c) 1997,1998 Causality Limited 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by Mark Brinicombe 80 * for the NetBSD Project. 81 * 4. The name of the company nor the name of the author may be used to 82 * endorse or promote products derived from this software without specific 83 * prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 86 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 87 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 88 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 */ 97 98 /* 99 * PCI configuration support for Samsung s3c2800. 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.23 2017/04/19 12:34:14 jmcneill Exp $"); 104 105 #include "opt_pci.h" 106 #include "pci.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/kernel.h> 111 #include <sys/device.h> 112 #include <sys/extent.h> 113 #include <sys/malloc.h> 114 115 #include <uvm/uvm_extern.h> 116 117 #include <sys/bus.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pciconf.h> 122 123 #include <arm/locore.h> 124 125 #include <arm/s3c2xx0/s3c2800reg.h> 126 #include <arm/s3c2xx0/s3c2800var.h> 127 128 /* 129 * pci tag encoding. 130 * also useful for configuration type 0 address 131 */ 132 #define BUSNO_SHIFT 16 133 #define BUSNO_MASK (0xff<<BUSNO_SHIFT) 134 #define DEVNO_SHIFT 11 135 #define DEVNO_MASK (0x1f<<DEVNO_SHIFT) 136 #define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT) 137 #define FUNNO_SHIFT 8 138 #define FUNNO_MASK (0x07<<FUNNO_SHIFT) 139 140 #define BUS0_DEV_MIN 1 141 #define BUS0_DEV_MAX 21 142 143 void s3c2800_pci_attach_hook(device_t, device_t, struct pcibus_attach_args *); 144 int s3c2800_pci_bus_maxdevs(void *, int); 145 pcitag_t s3c2800_pci_make_tag(void *, int, int, int); 146 void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *); 147 pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int); 148 void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t); 149 void s3c2800_pci_conf_interrupt(void *, int, int, int, int, int *); 150 int s3c2800_pci_intr_map(const struct pci_attach_args *, 151 pci_intr_handle_t *); 152 const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t, char *, size_t); 153 const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t); 154 void *s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int, 155 int (*) (void *), void *); 156 void s3c2800_pci_intr_disestablish(void *, void *); 157 158 #define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) 159 #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) 160 161 struct sspci_irq_handler { 162 int (*func) (void *); 163 void *arg; 164 int level; 165 SLIST_ENTRY(sspci_irq_handler) link; 166 }; 167 168 struct sspci_softc { 169 device_t sc_dev; 170 171 bus_space_tag_t sc_iot; 172 bus_space_handle_t sc_reg_ioh; 173 bus_space_handle_t sc_conf0_ioh; /* config type0 space */ 174 bus_space_handle_t sc_conf1_ioh; /* config type1 space */ 175 176 uint32_t sc_pciinten; /* copy of PCIINTEN register */ 177 178 /* list of interrupt handlers. SLIST is not good for removing 179 * element from it, but intr_disestablish is rarely called */ 180 SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers; 181 182 void *sc_softinterrupt; 183 }; 184 185 static int sspci_match(device_t, cfdata_t, void *aux); 186 static void sspci_attach(device_t, device_t, void *); 187 188 static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int, 189 bus_space_handle_t *); 190 static int sspci_init_controller(struct sspci_softc *); 191 static int sspci_intr(void *); 192 static void sspci_softintr(void *); 193 194 /* attach structures */ 195 CFATTACH_DECL_NEW(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach, 196 NULL, NULL); 197 198 199 struct arm32_pci_chipset sspci_chipset = { 200 NULL, /* conf_v */ 201 s3c2800_pci_attach_hook, 202 s3c2800_pci_bus_maxdevs, 203 s3c2800_pci_make_tag, 204 s3c2800_pci_decompose_tag, 205 s3c2800_pci_conf_read, 206 s3c2800_pci_conf_write, 207 NULL, /* intr_v */ 208 s3c2800_pci_intr_map, 209 s3c2800_pci_intr_string, 210 s3c2800_pci_intr_evcnt, 211 NULL, /* intr_setattr */ 212 s3c2800_pci_intr_establish, 213 s3c2800_pci_intr_disestablish, 214 #ifdef __HAVE_PCI_CONF_HOOK 215 NULL, 216 #endif 217 s3c2800_pci_conf_interrupt, 218 }; 219 220 221 /* 222 * bus space tag for PCI IO/Memory access space. 223 * filled in by sspci_attach() 224 */ 225 struct bus_space sspci_io_tag, sspci_mem_tag; 226 227 static int 228 sspci_match(device_t parent, cfdata_t match, void *aux) 229 { 230 return 1; 231 } 232 233 static void 234 sspci_attach(device_t parent, device_t self, void *aux) 235 { 236 struct sspci_softc *sc = device_private(self); 237 struct s3c2xx0_attach_args *aa = aux; 238 bus_space_tag_t iot; 239 bus_dma_tag_t pci_dma_tag; 240 const char *error_on; /* for panic message */ 241 #if defined(PCI_NETBSD_CONFIGURE) 242 struct extent *ioext, *memext; 243 struct pcibus_attach_args pci_pba; 244 #endif 245 246 #define FAIL(which) do { \ 247 error_on=(which); goto abort; }while(/*CONSTCOND*/0) 248 249 sc->sc_dev = self; 250 iot = sc->sc_iot = aa->sa_iot; 251 if (bus_space_map(iot, S3C2800_PCICTL_BASE, 252 S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh)) 253 FAIL("control regs"); 254 255 if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE, 256 S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh)) 257 FAIL("config type 0 area"); 258 259 #if 0 260 if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE, 261 S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh)) 262 FAIL("config type 1 area"); 263 #endif 264 printf("\n"); 265 266 SLIST_INIT(&sc->sc_irq_handlers); 267 if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL, 268 sspci_intr, sc)) 269 FAIL("intr_establish"); 270 271 sc->sc_softinterrupt = softint_establish(SOFTINT_SERIAL, 272 sspci_softintr, sc); 273 if (sc->sc_softinterrupt == NULL) 274 FAIL("softint_establish"); 275 276 #if defined(PCI_NETBSD_CONFIGURE) 277 if (sspci_init_controller(sc)) { 278 printf("%s: failed to initialize controller\n", device_xname(self)); 279 return; 280 } 281 #endif 282 283 sc->sc_pciinten = 284 PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 285 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD; 286 287 bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 288 sc->sc_pciinten); 289 290 { 291 pcireg_t id_reg, class_reg; 292 char buf[1000]; 293 294 id_reg = bus_space_read_4(iot, sc->sc_reg_ioh, 295 PCI_ID_REG); 296 class_reg = bus_space_read_4(iot, 297 sc->sc_reg_ioh, PCI_CLASS_REG); 298 299 pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf)); 300 printf("%s: %s\n", device_xname(self), buf); 301 } 302 303 #if defined(PCI_NETBSD_CONFIGURE) 304 ioext = extent_create("pciio", 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100, 305 NULL, 0, EX_NOWAIT); 306 307 memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE, 308 NULL, 0, EX_NOWAIT); 309 310 sspci_chipset.pc_conf_v = (void *) sc; 311 sspci_chipset.pc_intr_v = (void *) sc; 312 313 pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0, 314 arm_dcache_align); 315 316 extent_destroy(memext); 317 extent_destroy(ioext); 318 #endif /* PCI_NETBSD_CONFIGURE */ 319 320 /* initialize bus space tag */ 321 sspci_io_tag = *iot; 322 sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE; 323 sspci_io_tag.bs_map = sspci_bs_map; 324 sspci_mem_tag = *iot; 325 sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE; 326 sspci_mem_tag.bs_map = sspci_bs_map; 327 328 329 /* Platform provides PCI DMA tag */ 330 pci_dma_tag = s3c2800_pci_dma_init(); 331 332 pci_pba.pba_pc = &sspci_chipset; 333 pci_pba.pba_iot = &sspci_io_tag; 334 pci_pba.pba_memt = &sspci_mem_tag; 335 pci_pba.pba_dmat = pci_dma_tag; 336 pci_pba.pba_dmat64 = NULL; 337 pci_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 338 pci_pba.pba_bus = 0; 339 pci_pba.pba_bridgetag = NULL; 340 341 config_found_ia(self, "pcibus", &pci_pba, pcibusprint); 342 343 return; 344 345 #undef FAIL 346 abort: 347 panic("%s: map failed (%s)", 348 device_xname(self), error_on); 349 } 350 351 352 static int 353 sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 354 bus_space_handle_t * bshp) 355 { 356 bus_addr_t startpa, endpa; 357 vaddr_t va; 358 359 #ifdef PCI_DEBUG 360 printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n", 361 t, bpa, size, flag); 362 #endif 363 364 /* Round the allocation to page boundries */ 365 startpa = trunc_page(bpa); 366 endpa = round_page(bpa + size); 367 368 /* Get some VM. */ 369 va = uvm_km_alloc(kernel_map, endpa - startpa, 0, 370 UVM_KMF_VAONLY | UVM_KMF_NOWAIT); 371 if (va == 0) 372 return ENOMEM; 373 374 /* Store the bus space handle */ 375 *bshp = va + (bpa & PGOFSET); 376 377 /* Now map the pages */ 378 /* The cookie is the physical base address for PCI I/O or memory area */ 379 while (startpa < endpa) { 380 /* XXX pmap_kenter_pa maps pages cacheable -- not what we 381 * want. */ 382 pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa, 383 VM_PROT_READ | VM_PROT_WRITE, 0); 384 va += PAGE_SIZE; 385 startpa += PAGE_SIZE; 386 } 387 pmap_update(pmap_kernel()); 388 389 return 0; 390 } 391 392 393 394 void 395 s3c2800_pci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 396 { 397 #ifdef PCI_DEBUG 398 printf("pci_conf_interrupt(v(%p), bus(%d), dev(%d), ipin(%d), swiz(%d), *iline(%p)\n", v, bus, dev, ipin, swiz, iline); 399 #endif 400 if (bus == 0) { 401 *iline = dev; 402 } else { 403 panic("pci_conf_interrupt: bus=%d: not yet implemented", bus); 404 } 405 } 406 407 void 408 s3c2800_pci_attach_hook(device_t parent, device_t self, 409 struct pcibus_attach_args * pba) 410 { 411 412 /* Nothing to do. */ 413 #ifdef PCI_DEBUG 414 printf("s3c2800_pci_attach_hook()\n"); 415 #endif 416 } 417 418 int 419 s3c2800_pci_bus_maxdevs(void *v, int busno) 420 { 421 422 #ifdef PCI_DEBUG 423 printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno); 424 #endif 425 return (32); 426 } 427 pcitag_t 428 s3c2800_pci_make_tag(void *v, int bus, int device, int function) 429 { 430 431 return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) | 432 (function << FUNNO_SHIFT)); 433 } 434 435 void 436 s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 437 { 438 if (bp != NULL) 439 *bp = (tag >> BUSNO_SHIFT) & 0xff; 440 if (dp != NULL) 441 *dp = (tag >> DEVNO_SHIFT) & 0x1f; 442 if (fp != NULL) 443 *fp = (tag >> FUNNO_SHIFT) & 0x7; 444 } 445 446 static vaddr_t 447 make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset) 448 { 449 450 if ((unsigned int)offset >= PCI_CONF_SIZE) 451 return (vaddr_t) -1; 452 453 if ((tag & BUSNO_MASK) == 0) { 454 /* configuration type 0 */ 455 int devno = tag_to_devno(tag); 456 457 if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno) 458 return 0; 459 460 return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) + 461 (tag & (DEVNO_MASK | FUNNO_MASK)) + offset; 462 } else { 463 /* XXX */ 464 return (vaddr_t) - 1; /* cause fault */ 465 } 466 } 467 468 469 pcireg_t 470 s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset) 471 { 472 struct sspci_softc *sc = v; 473 vaddr_t va = make_pci_conf_va(sc, tag, offset); 474 int s; 475 pcireg_t rv; 476 477 #ifdef PCI_DEBUG 478 printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n", 479 sc->sc_conf0_ioh, tag, offset); 480 #endif 481 if (va == 0) 482 return -1; 483 484 PCI_CONF_LOCK(s); 485 486 if (badaddr_read((void *) va, sizeof(rv), &rv)) { 487 #if PCI_DEBUG 488 printf("conf_read: %lx bad address\n", va); 489 #endif 490 rv = (pcireg_t) - 1; 491 } 492 PCI_CONF_UNLOCK(s); 493 494 return rv; 495 } 496 497 void 498 s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 499 { 500 struct sspci_softc *sc = v; 501 vaddr_t va = make_pci_conf_va(sc, tag, offset); 502 u_int s; 503 504 #ifdef PCI_DEBUG 505 printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va); 506 #endif 507 508 PCI_CONF_LOCK(s); 509 510 *(pcireg_t *) va = val; 511 512 PCI_CONF_UNLOCK(s); 513 } 514 515 void * 516 s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level, 517 int (*func) (void *), void *arg) 518 { 519 struct sspci_softc *sc = pcv; 520 struct sspci_irq_handler *handler; 521 int s; 522 523 #ifdef PCI_DEBUG 524 printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, " 525 "func=%p, arg=%p)\n", pcv, ih, level, func, arg); 526 #endif 527 528 handler = malloc(sizeof *handler, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 529 if (handler == NULL) 530 panic("sspci_intr_establish: can't malloc handler info"); 531 532 handler->func = func; 533 handler->arg = arg; 534 handler->level = level; 535 536 s = splhigh(); 537 SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link); 538 splx(s); 539 540 return (handler); 541 } 542 543 void 544 s3c2800_pci_intr_disestablish(void *pcv, void *cookie) 545 { 546 struct sspci_softc *sc = pcv; 547 struct sspci_irq_handler *ih = cookie; 548 int s; 549 550 #ifdef PCI_DEBUG 551 printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n", 552 pcv, cookie); 553 #endif 554 555 s = splhigh(); 556 SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link); 557 splx(s); 558 } 559 560 int 561 s3c2800_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 562 { 563 #ifdef PCI_DEBUG 564 int pin = pa->pa_intrpin; 565 void *pcv = pa->pa_pc; 566 pcitag_t intrtag = pa->pa_intrtag; 567 int bus, device, function; 568 569 s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 570 printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n", 571 pcv, intrtag, pin, device); 572 #endif 573 574 575 /* S3C2800 has only one interrupt line for PCI */ 576 *ihp = 0; 577 return 0; 578 } 579 580 const char * 581 s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 582 { 583 /* We have only one interrupt source from PCI */ 584 strlcpy(buf, "pciint", len); 585 return buf; 586 } 587 588 const struct evcnt * 589 s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih) 590 { 591 592 /* XXX for now, no evcnt parent reported */ 593 return NULL; 594 } 595 /* 596 * Initialize PCI controller 597 */ 598 int 599 sspci_init_controller(struct sspci_softc * sc) 600 { 601 bus_space_tag_t iot = sc->sc_iot; 602 bus_space_handle_t ioh = sc->sc_reg_ioh; 603 604 /* disable PCI command */ 605 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 606 0xffff0000); 607 608 /* latency=0x10, cacheline=8 */ 609 bus_space_write_4(iot, ioh, PCI_BHLC_REG, 610 PCI_BHLC_CODE(0, 0, 0, 0x10, 8)); 611 612 bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG, 613 PCI_INTERRUPT_CODE(0, 0, 0, 0)); 614 615 616 617 #if 1 618 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 619 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 620 /* Cover all DBANKs with BAR0 */ 621 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000); 622 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START); 623 #else 624 bus_space_write_4(iot, ioh, PCI_MAPREG_START, 625 PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000); 626 bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4, 627 PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000); 628 629 bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000); 630 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000); 631 bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000); 632 bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START); 633 #endif 634 635 bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG, 636 PCI_STATUS_PARITY_DETECT | 637 PCI_STATUS_SPECIAL_ERROR | 638 PCI_STATUS_MASTER_ABORT | 639 PCI_STATUS_MASTER_TARGET_ABORT | 640 PCI_STATUS_TARGET_TARGET_ABORT | 641 PCI_STATUS_DEVSEL_MEDIUM | 642 PCI_STATUS_PARITY_ERROR | 643 PCI_STATUS_BACKTOBACK_SUPPORT | 644 PCI_STATUS_CAPLIST_SUPPORT | 645 PCI_COMMAND_MASTER_ENABLE | 646 PCI_COMMAND_MEM_ENABLE | 647 PCI_COMMAND_IO_ENABLE); 648 649 bus_space_write_4(iot, ioh, PCICTL_PCICON, 650 PCICON_ARB | PCICON_HST); 651 652 bus_space_write_4(iot, ioh, PCICTL_PCISET, 0); 653 /* clear all interrupts */ 654 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff); 655 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0); 656 657 bus_space_write_4(iot, ioh, PCICTL_PCICON, 658 PCICON_RDY | PCICON_CFD | PCICON_ATS | 659 PCICON_ARB | PCICON_HST); 660 661 662 #ifdef PCI_DEBUG 663 { 664 pcireg_t reg; 665 int i; 666 667 for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) { 668 reg = bus_space_read_4(iot, ioh, i); 669 printf("%03x: %08x\n", i, reg); 670 } 671 for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) { 672 reg = bus_space_read_4(iot, ioh, i); 673 printf("%03x: %08x\n", i, reg); 674 } 675 } 676 #endif 677 return 0; 678 } 679 680 681 static const char *pci_abnormal_error_name[] = { 682 "PCI reset deasserted", 683 "PCI reset asserted", 684 "PCI master detected fatal error", 685 "PCI master detected parity error", 686 "PCI target detected parity error", 687 "PCI SERR# asserted", 688 }; 689 690 static int 691 sspci_intr(void *arg) 692 { 693 struct sspci_softc *sc = arg; 694 int s; 695 bus_space_tag_t iot = sc->sc_iot; 696 bus_space_handle_t ioh = sc->sc_reg_ioh; 697 uint32_t interrupts, errors; 698 699 interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST); 700 701 if (interrupts & PCIINT_INA) { 702 s = splhigh(); 703 softint_schedule(sc->sc_softinterrupt); 704 705 /* mask INTA itnerrupt until softinterrupt is handled */ 706 sc->sc_pciinten &= ~PCIINT_INA; 707 bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 708 sc->sc_pciinten); 709 710 /* acknowledge INTA interrupt */ 711 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA); 712 713 splx(s); 714 715 interrupts &= ~PCIINT_INA; 716 717 } 718 errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE | 719 PCIINT_MFE | PCIINT_PRA | PCIINT_PRD); 720 if (errors) { 721 int i; 722 723 for (i = 0; errors; ++i) { 724 if ((errors & (1 << i)) == 0) 725 continue; 726 727 printf("%s: %s\n", device_xname(sc->sc_dev), 728 pci_abnormal_error_name[i > 4 ? 5 : i]); 729 730 errors &= ~(1 << i); 731 } 732 /* acknowledge interrupts */ 733 bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts); 734 } 735 return 0; 736 } 737 738 static void 739 sspci_softintr(void *arg) 740 { 741 struct sspci_softc *sc = arg; 742 struct sspci_irq_handler *ih; 743 int s; 744 745 746 SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) { 747 s = _splraise(ih->level); 748 ih->func(ih->arg); 749 splx(s); 750 } 751 752 /* unmask INTA interrupt */ 753 s = splhigh(); 754 sc->sc_pciinten |= PCIINT_INA; 755 bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN, 756 sc->sc_pciinten); 757 splx(s); 758 } 759