1 /* $NetBSD: s3c2800_intr.c,v 1.4 2003/05/12 07:48:37 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * IRQ handler for Samsung S3C2800 processor. 37 * It has integrated interrupt controller. 38 */ 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <uvm/uvm_extern.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 #include <arm/cpufunc.h> 46 47 #include <arm/s3c2xx0/s3c2800reg.h> 48 #include <arm/s3c2xx0/s3c2800var.h> 49 50 /* 51 * interrupt dispatch table. 52 */ 53 54 struct s3c2xx0_intr_dispatch handler[ICU_LEN]; 55 56 __volatile int softint_pending; 57 58 __volatile int current_spl_level; 59 __volatile int intr_mask; 60 61 /* interrupt masks for each level */ 62 int s3c2xx0_imask[NIPL]; 63 int s3c2xx0_ilevel[ICU_LEN]; 64 65 vaddr_t intctl_base; /* interrupt controller registers */ 66 #define icreg(offset) \ 67 (*(volatile uint32_t *)(intctl_base+(offset))) 68 69 /* 70 * Map a software interrupt queue to an interrupt priority level. 71 */ 72 static const int si_to_ipl[SI_NQUEUES] = { 73 IPL_SOFT, /* SI_SOFT */ 74 IPL_SOFTCLOCK, /* SI_SOFTCLOCK */ 75 IPL_SOFTNET, /* SI_SOFTNET */ 76 IPL_SOFTSERIAL, /* SI_SOFTSERIAL */ 77 }; 78 79 /* 80 * Clearing interrupt pending bits affects some built-in 81 * peripherals. For example, IIC starts transmitting next data when 82 * its interrupt pending bit is cleared. 83 * We need to leave those bits to peripheral handlers. 84 */ 85 #define PENDING_CLEAR_MASK (~((1<<S3C2800_INT_IIC0)|(1<<S3C2800_INT_IIC1))) 86 87 /* 88 * called from irq_entry. 89 */ 90 void s3c2800_irq_handler(struct clockframe *); 91 void 92 s3c2800_irq_handler(struct clockframe *frame) 93 { 94 uint32_t irqbits; 95 int irqno; 96 int saved_spl_level; 97 98 saved_spl_level = current_spl_level; 99 100 /* get pending IRQs */ 101 irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK; 102 103 for (irqno = 0; irqbits; ++irqno) { 104 if ((irqbits & (1 << irqno)) == 0) 105 continue; 106 /* raise spl to stop interrupts of lower priorities */ 107 if (saved_spl_level < handler[irqno].level) 108 s3c2xx0_setipl(handler[irqno].level); 109 110 /* clear pending bit */ 111 icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno); 112 #ifdef notyet 113 /* Enable interrupt */ 114 #endif 115 (*handler[irqno].func) ( 116 handler[irqno].cookie == 0 117 ? frame : handler[irqno].cookie); 118 #ifdef notyet 119 /* Disable interrupt */ 120 #endif 121 122 irqbits &= ~(1 << irqno); 123 } 124 125 /* restore spl to that was when this interrupt happen */ 126 s3c2xx0_setipl(saved_spl_level); 127 128 if (softint_pending & intr_mask) 129 s3c2xx0_do_pending(); 130 } 131 132 static const u_char s3c2800_ist[] = { 133 EXTINTR_LOW, /* NONE */ 134 EXTINTR_FALLING, /* PULSE */ 135 EXTINTR_FALLING, /* EDGE */ 136 EXTINTR_LOW, /* LEVEL */ 137 EXTINTR_HIGH, 138 EXTINTR_RISING, 139 EXTINTR_BOTH, 140 }; 141 142 void * 143 s3c2800_intr_establish(int irqno, int level, int type, 144 int (* func) (void *), void *cookie) 145 { 146 int save; 147 148 if (irqno < 0 || irqno >= ICU_LEN || 149 type < IST_NONE || IST_EDGE_BOTH < type) 150 panic("intr_establish: bogus irq or type"); 151 152 save = disable_interrupts(I32_bit); 153 154 handler[irqno].cookie = cookie; 155 handler[irqno].func = func; 156 handler[irqno].level = level; 157 158 s3c2xx0_update_intr_masks(irqno, level); 159 160 if (irqno <= S3C2800_INT_EXT(7)) { 161 /* 162 * Update external interrupt control 163 */ 164 uint32_t reg; 165 u_int trig; 166 167 trig = s3c2800_ist[type]; 168 169 reg = bus_space_read_4(s3c2xx0_softc->sc_iot, 170 s3c2xx0_softc->sc_gpio_ioh, 171 GPIO_EXTINTR); 172 173 reg = reg & ~(0x0f << (4*irqno)); 174 reg |= trig << (4*irqno); 175 176 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh, 177 GPIO_EXTINTR, reg); 178 } 179 180 intr_mask = s3c2xx0_imask[current_spl_level]; 181 *s3c2xx0_intr_mask_reg = intr_mask; 182 183 restore_interrupts(save); 184 185 return (&handler[irqno]); 186 } 187 188 189 void 190 s3c2800_intr_init(struct s3c2800_softc *sc) 191 { 192 intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot, 193 sc->sc_sx.sc_intctl_ioh); 194 195 s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK); 196 197 /* clear all pending interrupt */ 198 icreg(INTCTL_SRCPND) = 0xffffffff; 199 200 s3c2xx0_intr_init(handler, ICU_LEN); 201 202 } 203