1 /* $NetBSD: rk_dwhdmi.c,v 1.5 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_dwhdmi.c,v 1.5 2021/01/27 03:10:19 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 40 #include <drm/drmP.h> 41 #include <drm/drm_crtc_helper.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/fdt/fdt_port.h> 45 #include <dev/fdt/syscon.h> 46 47 #include <dev/ic/dw_hdmi.h> 48 49 #define RK3399_GRF_SOC_CON20 0x6250 50 #define HDMI_LCDC_SEL __BIT(6) 51 52 static const struct dwhdmi_mpll_config rk_dwhdmi_mpll_config[] = { 53 { 40000, 0x00b3, 0x0000, 0x0018 }, 54 { 65000, 0x0072, 0x0001, 0x0028 }, 55 { 66000, 0x013e, 0x0003, 0x0038 }, 56 { 83500, 0x0072, 0x0001, 0x0028 }, 57 { 146250, 0x0051, 0x0002, 0x0038 }, 58 { 148500, 0x0051, 0x0003, 0x0000 }, 59 { 272000, 0x0040, 0x0003, 0x0000 }, 60 { 340000, 0x0040, 0x0003, 0x0000 }, 61 { 0, 0x0051, 0x0003, 0x0000 }, 62 }; 63 64 static const struct dwhdmi_phy_config rk_dwhdmi_phy_config[] = { 65 { 74250, 0x8009, 0x0004, 0x0272 }, 66 { 148500, 0x802b, 0x0004, 0x028d }, 67 { 297000, 0x8039, 0x0005, 0x028d }, 68 { 594000, 0x8039, 0x0000, 0x019d }, 69 { 0, 0x0000, 0x0000, 0x0000 } 70 }; 71 72 enum { 73 DWHDMI_PORT_INPUT = 0, 74 DWHDMI_PORT_OUTPUT = 1, 75 }; 76 77 static const struct device_compatible_entry compat_data[] = { 78 { .compat = "rockchip,rk3399-dw-hdmi" }, 79 DEVICE_COMPAT_EOL 80 }; 81 82 struct rk_dwhdmi_softc { 83 struct dwhdmi_softc sc_base; 84 int sc_phandle; 85 struct clk *sc_clk_vpll; 86 87 struct fdt_device_ports sc_ports; 88 struct drm_display_mode sc_curmode; 89 struct drm_encoder sc_encoder; 90 struct syscon *sc_grf; 91 92 bool sc_activated; 93 }; 94 95 #define to_rk_dwhdmi_softc(x) container_of(x, struct rk_dwhdmi_softc, sc_base) 96 #define to_rk_dwhdmi_encoder(x) container_of(x, struct rk_dwhdmi_softc, sc_encoder) 97 98 static void 99 rk_dwhdmi_select_input(struct rk_dwhdmi_softc *sc, u_int crtc_index) 100 { 101 const uint32_t write_mask = HDMI_LCDC_SEL << 16; 102 const uint32_t write_val = crtc_index == 0 ? HDMI_LCDC_SEL : 0; 103 104 syscon_lock(sc->sc_grf); 105 syscon_write_4(sc->sc_grf, RK3399_GRF_SOC_CON20, write_mask | write_val); 106 syscon_unlock(sc->sc_grf); 107 } 108 109 static bool 110 rk_dwhdmi_encoder_mode_fixup(struct drm_encoder *encoder, 111 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 112 { 113 return true; 114 } 115 116 static void 117 rk_dwhdmi_encoder_mode_set(struct drm_encoder *encoder, 118 struct drm_display_mode *mode, struct drm_display_mode *adjusted) 119 { 120 } 121 122 static void 123 rk_dwhdmi_encoder_enable(struct drm_encoder *encoder) 124 { 125 } 126 127 static void 128 rk_dwhdmi_encoder_disable(struct drm_encoder *encoder) 129 { 130 } 131 132 static void 133 rk_dwhdmi_encoder_prepare(struct drm_encoder *encoder) 134 { 135 struct rk_dwhdmi_softc * const sc = to_rk_dwhdmi_encoder(encoder); 136 const u_int crtc_index = drm_crtc_index(encoder->crtc); 137 138 rk_dwhdmi_select_input(sc, crtc_index); 139 } 140 141 static void 142 rk_dwhdmi_encoder_commit(struct drm_encoder *encoder) 143 { 144 } 145 146 static const struct drm_encoder_funcs rk_dwhdmi_encoder_funcs = { 147 .destroy = drm_encoder_cleanup, 148 }; 149 150 static const struct drm_encoder_helper_funcs rk_dwhdmi_encoder_helper_funcs = { 151 .prepare = rk_dwhdmi_encoder_prepare, 152 .mode_fixup = rk_dwhdmi_encoder_mode_fixup, 153 .mode_set = rk_dwhdmi_encoder_mode_set, 154 .enable = rk_dwhdmi_encoder_enable, 155 .disable = rk_dwhdmi_encoder_disable, 156 .commit = rk_dwhdmi_encoder_commit, 157 }; 158 159 static int 160 rk_dwhdmi_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 161 { 162 struct rk_dwhdmi_softc * const sc = device_private(dev); 163 struct fdt_endpoint *in_ep = fdt_endpoint_remote(ep); 164 struct fdt_endpoint *out_ep, *out_rep; 165 struct drm_crtc *crtc; 166 int error; 167 168 if (sc->sc_activated != false) { 169 return 0; 170 } 171 172 if (!activate) 173 return EINVAL; 174 175 if (fdt_endpoint_port_index(ep) != DWHDMI_PORT_INPUT) 176 return EINVAL; 177 178 switch (fdt_endpoint_type(in_ep)) { 179 case EP_DRM_CRTC: 180 crtc = fdt_endpoint_get_data(in_ep); 181 break; 182 default: 183 crtc = NULL; 184 break; 185 } 186 187 if (crtc == NULL) 188 return EINVAL; 189 190 sc->sc_encoder.possible_crtcs = 3; // 1U << drm_crtc_index(crtc); /* XXX */ 191 drm_encoder_init(crtc->dev, &sc->sc_encoder, &rk_dwhdmi_encoder_funcs, 192 DRM_MODE_ENCODER_TMDS); 193 drm_encoder_helper_add(&sc->sc_encoder, &rk_dwhdmi_encoder_helper_funcs); 194 195 sc->sc_base.sc_connector.base.connector_type = DRM_MODE_CONNECTOR_HDMIA; 196 error = dwhdmi_bind(&sc->sc_base, &sc->sc_encoder); 197 if (error != 0) 198 return error; 199 sc->sc_activated = true; 200 201 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, DWHDMI_PORT_OUTPUT, 0); 202 if (out_ep != NULL) { 203 /* Ignore downstream connectors, we have our own. */ 204 out_rep = fdt_endpoint_remote(out_ep); 205 if (out_rep != NULL && fdt_endpoint_type(out_rep) == EP_DRM_CONNECTOR) 206 return 0; 207 208 error = fdt_endpoint_activate(out_ep, activate); 209 if (error != 0) 210 return error; 211 } 212 213 return 0; 214 } 215 216 static void * 217 rk_dwhdmi_ep_get_data(device_t dev, struct fdt_endpoint *ep) 218 { 219 struct rk_dwhdmi_softc * const sc = device_private(dev); 220 221 return &sc->sc_encoder; 222 } 223 224 static void 225 rk_dwhdmi_enable(struct dwhdmi_softc *dsc) 226 { 227 228 dwhdmi_phy_enable(dsc); 229 } 230 231 static void 232 rk_dwhdmi_mode_set(struct dwhdmi_softc *dsc, 233 struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 234 { 235 struct rk_dwhdmi_softc * const sc = to_rk_dwhdmi_softc(dsc); 236 int error; 237 238 if (sc->sc_clk_vpll != NULL) { 239 error = clk_set_rate(sc->sc_clk_vpll, adjusted_mode->clock * 1000); 240 if (error != 0) 241 device_printf(dsc->sc_dev, "couldn't set pixel clock to %u Hz: %d\n", 242 adjusted_mode->clock * 1000, error); 243 } 244 245 dwhdmi_phy_mode_set(dsc, mode, adjusted_mode); 246 } 247 248 static audio_dai_tag_t 249 rk_dwhdmi_dai_get_tag(device_t dev, const void *data, size_t len) 250 { 251 struct rk_dwhdmi_softc * const sc = device_private(dev); 252 253 if (len != 4) 254 return NULL; 255 256 return &sc->sc_base.sc_dai; 257 } 258 259 static struct fdtbus_dai_controller_func rk_dwhdmi_dai_funcs = { 260 .get_tag = rk_dwhdmi_dai_get_tag 261 }; 262 263 static int 264 rk_dwhdmi_match(device_t parent, cfdata_t cf, void *aux) 265 { 266 struct fdt_attach_args * const faa = aux; 267 268 return of_compatible_match(faa->faa_phandle, compat_data); 269 } 270 271 static void 272 rk_dwhdmi_attach(device_t parent, device_t self, void *aux) 273 { 274 struct rk_dwhdmi_softc * const sc = device_private(self); 275 struct fdt_attach_args * const faa = aux; 276 const int phandle = faa->faa_phandle; 277 bus_addr_t addr; 278 bus_size_t size; 279 280 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 281 aprint_error(": couldn't get registers\n"); 282 return; 283 } 284 285 /* Required */ 286 if (fdtbus_clock_enable(phandle, "iahb", true) != 0) { 287 aprint_error(": couldn't enable iahb clock\n"); 288 return; 289 } 290 291 /* Required */ 292 if (fdtbus_clock_enable(phandle, "isfr", true) != 0) { 293 aprint_error(": couldn't enable isfr clock\n"); 294 return; 295 } 296 297 /* Optional */ 298 sc->sc_clk_vpll = fdtbus_clock_get(phandle, "vpll"); 299 if (sc->sc_clk_vpll != NULL && clk_enable(sc->sc_clk_vpll) != 0) { 300 aprint_error(": couldn't enable vpll clock\n"); 301 return; 302 } 303 304 /* Optional */ 305 if (fdtbus_clock_enable(phandle, "grf", false) != 0) { 306 aprint_error(": couldn't enable grf clock\n"); 307 return; 308 } 309 310 /* Optional */ 311 if (fdtbus_clock_enable(phandle, "cec", false) != 0) { 312 aprint_error(": couldn't enable cec clock\n"); 313 return; 314 } 315 316 sc->sc_base.sc_dev = self; 317 if (of_getprop_uint32(phandle, "reg-io-width", &sc->sc_base.sc_reg_width) != 0) 318 sc->sc_base.sc_reg_width = 4; 319 sc->sc_base.sc_bst = faa->faa_bst; 320 if (bus_space_map(sc->sc_base.sc_bst, addr, size, 0, &sc->sc_base.sc_bsh) != 0) { 321 aprint_error(": couldn't map registers\n"); 322 return; 323 } 324 sc->sc_phandle = faa->faa_phandle; 325 sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 326 if (sc->sc_grf == NULL) { 327 aprint_error(": couldn't get grf syscon\n"); 328 return; 329 } 330 331 aprint_naive("\n"); 332 aprint_normal(": HDMI TX\n"); 333 334 sc->sc_base.sc_ic = fdtbus_i2c_acquire(phandle, "ddc-i2c-bus"); 335 if (of_hasprop(phandle, "ddc-i2c-bus") && sc->sc_base.sc_ic == NULL) { 336 aprint_error_dev(self, "couldn't find external I2C master\n"); 337 return; 338 } 339 340 sc->sc_base.sc_flags |= DWHDMI_USE_INTERNAL_PHY; 341 sc->sc_base.sc_detect = dwhdmi_phy_detect; 342 sc->sc_base.sc_enable = rk_dwhdmi_enable; 343 sc->sc_base.sc_disable = dwhdmi_phy_disable; 344 sc->sc_base.sc_mode_set = rk_dwhdmi_mode_set; 345 sc->sc_base.sc_mpll_config = rk_dwhdmi_mpll_config; 346 sc->sc_base.sc_phy_config = rk_dwhdmi_phy_config; 347 348 if (dwhdmi_attach(&sc->sc_base) != 0) { 349 aprint_error_dev(self, "failed to attach driver\n"); 350 return; 351 } 352 353 sc->sc_ports.dp_ep_activate = rk_dwhdmi_ep_activate; 354 sc->sc_ports.dp_ep_get_data = rk_dwhdmi_ep_get_data; 355 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_ENCODER); 356 357 fdtbus_register_dai_controller(self, phandle, &rk_dwhdmi_dai_funcs); 358 } 359 360 CFATTACH_DECL_NEW(rk_dwhdmi, sizeof(struct rk_dwhdmi_softc), 361 rk_dwhdmi_match, rk_dwhdmi_attach, NULL, NULL); 362