1 /* $NetBSD: rk_cru.c,v 1.4 2018/06/30 17:54:07 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_fdt_arm.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_cru.c,v 1.4 2018/06/30 17:54:07 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #include <dev/clk/clk_backend.h> 43 44 #include <arm/rockchip/rk_cru.h> 45 46 #define CRU_SOFTRST_CON0 0x0300 47 48 static void * 49 rk_cru_reset_acquire(device_t dev, const void *data, size_t len) 50 { 51 if (len != 4) 52 return NULL; 53 54 return (void *)(uintptr_t)be32dec(data); 55 } 56 57 static void 58 rk_cru_reset_release(device_t dev, void *priv) 59 { 60 } 61 62 static int 63 rk_cru_reset_assert(device_t dev, void *priv) 64 { 65 struct rk_cru_softc * const sc = device_private(dev); 66 const uintptr_t reset_id = (uintptr_t)priv; 67 const bus_size_t reg = CRU_SOFTRST_CON0 + (reset_id / 16) * 4; 68 const u_int shift = reset_id % 16; 69 70 CRU_WRITE(sc, reg, (1 << (shift + 16)) | (1 << shift)); 71 72 return 0; 73 } 74 75 static int 76 rk_cru_reset_deassert(device_t dev, void *priv) 77 { 78 struct rk_cru_softc * const sc = device_private(dev); 79 const uintptr_t reset_id = (uintptr_t)priv; 80 const bus_size_t reg = CRU_SOFTRST_CON0 + (reset_id / 16) * 4; 81 const u_int shift = reset_id % 16; 82 83 CRU_WRITE(sc, reg, (1 << (shift + 16)) | (0 << shift)); 84 85 return 0; 86 } 87 88 static const struct fdtbus_reset_controller_func rk_cru_fdtreset_funcs = { 89 .acquire = rk_cru_reset_acquire, 90 .release = rk_cru_reset_release, 91 .reset_assert = rk_cru_reset_assert, 92 .reset_deassert = rk_cru_reset_deassert, 93 }; 94 95 static struct clk * 96 rk_cru_clock_decode(device_t dev, const void *data, size_t len) 97 { 98 struct rk_cru_softc * const sc = device_private(dev); 99 struct rk_cru_clk *clk; 100 101 if (len != 4) 102 return NULL; 103 104 const u_int clock_id = be32dec(data); 105 106 for (int i = 0; i < sc->sc_nclks; i++) { 107 clk = &sc->sc_clks[i]; 108 if (clk->id == clock_id) 109 return &clk->base; 110 } 111 112 return NULL; 113 } 114 115 static const struct fdtbus_clock_controller_func rk_cru_fdtclock_funcs = { 116 .decode = rk_cru_clock_decode, 117 }; 118 119 static struct clk * 120 rk_cru_clock_get(void *priv, const char *name) 121 { 122 struct rk_cru_softc * const sc = priv; 123 struct rk_cru_clk *clk; 124 125 clk = rk_cru_clock_find(sc, name); 126 if (clk == NULL) 127 return NULL; 128 129 return &clk->base; 130 } 131 132 static void 133 rk_cru_clock_put(void *priv, struct clk *clk) 134 { 135 } 136 137 static u_int 138 rk_cru_clock_get_rate(void *priv, struct clk *clkp) 139 { 140 struct rk_cru_softc * const sc = priv; 141 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 142 struct clk *clkp_parent; 143 144 if (clk->get_rate) 145 return clk->get_rate(sc, clk); 146 147 clkp_parent = clk_get_parent(clkp); 148 if (clkp_parent == NULL) { 149 aprint_error("%s: no parent for %s\n", __func__, clk->base.name); 150 return 0; 151 } 152 153 return clk_get_rate(clkp_parent); 154 } 155 156 static int 157 rk_cru_clock_set_rate(void *priv, struct clk *clkp, u_int rate) 158 { 159 struct rk_cru_softc * const sc = priv; 160 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 161 struct clk *clkp_parent; 162 163 if (clkp->flags & CLK_SET_RATE_PARENT) { 164 clkp_parent = clk_get_parent(clkp); 165 if (clkp_parent == NULL) { 166 aprint_error("%s: no parent for %s\n", __func__, clk->base.name); 167 return ENXIO; 168 } 169 return clk_set_rate(clkp_parent, rate); 170 } 171 172 if (clk->set_rate) 173 return clk->set_rate(sc, clk, rate); 174 175 return ENXIO; 176 } 177 178 static u_int 179 rk_cru_clock_round_rate(void *priv, struct clk *clkp, u_int rate) 180 { 181 struct rk_cru_softc * const sc = priv; 182 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 183 struct clk *clkp_parent; 184 185 if (clkp->flags & CLK_SET_RATE_PARENT) { 186 clkp_parent = clk_get_parent(clkp); 187 if (clkp_parent == NULL) { 188 aprint_error("%s: no parent for %s\n", __func__, clk->base.name); 189 return 0; 190 } 191 return clk_round_rate(clkp_parent, rate); 192 } 193 194 if (clk->round_rate) 195 return clk->round_rate(sc, clk, rate); 196 197 return 0; 198 } 199 200 static int 201 rk_cru_clock_enable(void *priv, struct clk *clkp) 202 { 203 struct rk_cru_softc * const sc = priv; 204 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 205 struct clk *clkp_parent; 206 int error = 0; 207 208 clkp_parent = clk_get_parent(clkp); 209 if (clkp_parent != NULL) { 210 error = clk_enable(clkp_parent); 211 if (error != 0) 212 return error; 213 } 214 215 if (clk->enable) 216 error = clk->enable(sc, clk, 1); 217 218 return error; 219 } 220 221 static int 222 rk_cru_clock_disable(void *priv, struct clk *clkp) 223 { 224 struct rk_cru_softc * const sc = priv; 225 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 226 int error = EINVAL; 227 228 if (clk->enable) 229 error = clk->enable(sc, clk, 0); 230 231 return error; 232 } 233 234 static int 235 rk_cru_clock_set_parent(void *priv, struct clk *clkp, 236 struct clk *clkp_parent) 237 { 238 struct rk_cru_softc * const sc = priv; 239 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 240 241 if (clk->set_parent == NULL) 242 return EINVAL; 243 244 return clk->set_parent(sc, clk, clkp_parent->name); 245 } 246 247 static struct clk * 248 rk_cru_clock_get_parent(void *priv, struct clk *clkp) 249 { 250 struct rk_cru_softc * const sc = priv; 251 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 252 struct rk_cru_clk *clk_parent; 253 const char *parent; 254 255 if (clk->get_parent == NULL) 256 return NULL; 257 258 parent = clk->get_parent(sc, clk); 259 if (parent == NULL) 260 return NULL; 261 262 clk_parent = rk_cru_clock_find(sc, parent); 263 if (clk_parent != NULL) 264 return &clk_parent->base; 265 266 /* No parent in this domain, try FDT */ 267 return fdtbus_clock_byname(parent); 268 } 269 270 static const struct clk_funcs rk_cru_clock_funcs = { 271 .get = rk_cru_clock_get, 272 .put = rk_cru_clock_put, 273 .get_rate = rk_cru_clock_get_rate, 274 .set_rate = rk_cru_clock_set_rate, 275 .round_rate = rk_cru_clock_round_rate, 276 .enable = rk_cru_clock_enable, 277 .disable = rk_cru_clock_disable, 278 .set_parent = rk_cru_clock_set_parent, 279 .get_parent = rk_cru_clock_get_parent, 280 }; 281 282 struct rk_cru_clk * 283 rk_cru_clock_find(struct rk_cru_softc *sc, const char *name) 284 { 285 for (int i = 0; i < sc->sc_nclks; i++) { 286 if (sc->sc_clks[i].base.name == NULL) 287 continue; 288 if (strcmp(sc->sc_clks[i].base.name, name) == 0) 289 return &sc->sc_clks[i]; 290 } 291 292 return NULL; 293 } 294 295 int 296 rk_cru_attach(struct rk_cru_softc *sc) 297 { 298 bus_addr_t addr; 299 bus_size_t size; 300 int i; 301 302 if (of_hasprop(sc->sc_phandle, "rockchip,grf")) { 303 sc->sc_grf = fdtbus_syscon_acquire(sc->sc_phandle, "rockchip,grf"); 304 if (sc->sc_grf == NULL) { 305 aprint_error(": couldn't get grf syscon\n"); 306 return ENXIO; 307 } 308 } 309 310 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr, &size) != 0) { 311 aprint_error(": couldn't get registers\n"); 312 return ENXIO; 313 } 314 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 315 aprint_error(": couldn't map registers\n"); 316 return ENXIO; 317 } 318 319 sc->sc_clkdom.name = device_xname(sc->sc_dev); 320 sc->sc_clkdom.funcs = &rk_cru_clock_funcs; 321 sc->sc_clkdom.priv = sc; 322 for (i = 0; i < sc->sc_nclks; i++) { 323 sc->sc_clks[i].base.domain = &sc->sc_clkdom; 324 clk_attach(&sc->sc_clks[i].base); 325 } 326 327 fdtbus_register_clock_controller(sc->sc_dev, sc->sc_phandle, 328 &rk_cru_fdtclock_funcs); 329 330 fdtbus_register_reset_controller(sc->sc_dev, sc->sc_phandle, 331 &rk_cru_fdtreset_funcs); 332 333 return 0; 334 } 335 336 void 337 rk_cru_print(struct rk_cru_softc *sc) 338 { 339 struct rk_cru_clk *clk; 340 struct clk *clkp_parent; 341 const char *type; 342 int i; 343 344 for (i = 0; i < sc->sc_nclks; i++) { 345 clk = &sc->sc_clks[i]; 346 if (clk->type == RK_CRU_UNKNOWN) 347 continue; 348 349 clkp_parent = clk_get_parent(&clk->base); 350 351 switch (clk->type) { 352 case RK_CRU_PLL: type = "pll"; break; 353 case RK_CRU_ARM: type = "arm"; break; 354 case RK_CRU_COMPOSITE: type = "comp"; break; 355 case RK_CRU_GATE: type = "gate"; break; 356 case RK_CRU_MUX: type = "mux"; break; 357 default: type = "???"; break; 358 } 359 360 aprint_debug_dev(sc->sc_dev, 361 "%3d %-14s %2s %-14s %-7s ", 362 clk->id, 363 clk->base.name, 364 clkp_parent ? "<-" : "", 365 clkp_parent ? clkp_parent->name : "", 366 type); 367 aprint_debug("%10d Hz\n", clk_get_rate(&clk->base)); 368 } 369 } 370