1 /* $NetBSD: rk_cru.c,v 1.9 2018/11/17 16:51:51 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_console.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: rk_cru.c,v 1.9 2018/11/17 16:51:51 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/cpu.h> 38 #include <sys/device.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #include <dev/clk/clk_backend.h> 43 44 #include <arm/rockchip/rk_cru.h> 45 46 static void * 47 rk_cru_reset_acquire(device_t dev, const void *data, size_t len) 48 { 49 if (len != 4) 50 return NULL; 51 52 return (void *)(uintptr_t)be32dec(data); 53 } 54 55 static void 56 rk_cru_reset_release(device_t dev, void *priv) 57 { 58 } 59 60 static int 61 rk_cru_reset_assert(device_t dev, void *priv) 62 { 63 struct rk_cru_softc * const sc = device_private(dev); 64 const uintptr_t reset_id = (uintptr_t)priv; 65 const bus_size_t reg = sc->sc_softrst_base + (reset_id / 16) * 4; 66 const u_int shift = reset_id % 16; 67 68 CRU_WRITE(sc, reg, (1 << (shift + 16)) | (1 << shift)); 69 70 return 0; 71 } 72 73 static int 74 rk_cru_reset_deassert(device_t dev, void *priv) 75 { 76 struct rk_cru_softc * const sc = device_private(dev); 77 const uintptr_t reset_id = (uintptr_t)priv; 78 const bus_size_t reg = sc->sc_softrst_base + (reset_id / 16) * 4; 79 const u_int shift = reset_id % 16; 80 81 CRU_WRITE(sc, reg, (1 << (shift + 16)) | (0 << shift)); 82 83 return 0; 84 } 85 86 static const struct fdtbus_reset_controller_func rk_cru_fdtreset_funcs = { 87 .acquire = rk_cru_reset_acquire, 88 .release = rk_cru_reset_release, 89 .reset_assert = rk_cru_reset_assert, 90 .reset_deassert = rk_cru_reset_deassert, 91 }; 92 93 static struct clk * 94 rk_cru_clock_decode(device_t dev, int cc_phandle, const void *data, size_t len) 95 { 96 struct rk_cru_softc * const sc = device_private(dev); 97 struct rk_cru_clk *clk; 98 99 if (len != 4) 100 return NULL; 101 102 const u_int clock_id = be32dec(data); 103 104 for (int i = 0; i < sc->sc_nclks; i++) { 105 clk = &sc->sc_clks[i]; 106 if (clk->id == clock_id) 107 return &clk->base; 108 } 109 110 return NULL; 111 } 112 113 static const struct fdtbus_clock_controller_func rk_cru_fdtclock_funcs = { 114 .decode = rk_cru_clock_decode, 115 }; 116 117 static struct clk * 118 rk_cru_clock_get(void *priv, const char *name) 119 { 120 struct rk_cru_softc * const sc = priv; 121 struct rk_cru_clk *clk; 122 123 clk = rk_cru_clock_find(sc, name); 124 if (clk == NULL) 125 return NULL; 126 127 return &clk->base; 128 } 129 130 static void 131 rk_cru_clock_put(void *priv, struct clk *clk) 132 { 133 } 134 135 static u_int 136 rk_cru_clock_get_rate(void *priv, struct clk *clkp) 137 { 138 struct rk_cru_softc * const sc = priv; 139 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 140 struct clk *clkp_parent; 141 142 if (clk->get_rate) 143 return clk->get_rate(sc, clk); 144 145 clkp_parent = clk_get_parent(clkp); 146 if (clkp_parent == NULL) { 147 aprint_debug("%s: no parent for %s\n", __func__, clk->base.name); 148 return 0; 149 } 150 151 return clk_get_rate(clkp_parent); 152 } 153 154 static int 155 rk_cru_clock_set_rate(void *priv, struct clk *clkp, u_int rate) 156 { 157 struct rk_cru_softc * const sc = priv; 158 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 159 struct clk *clkp_parent; 160 161 if (clkp->flags & CLK_SET_RATE_PARENT) { 162 clkp_parent = clk_get_parent(clkp); 163 if (clkp_parent == NULL) { 164 aprint_error("%s: no parent for %s\n", __func__, clk->base.name); 165 return ENXIO; 166 } 167 return clk_set_rate(clkp_parent, rate); 168 } 169 170 if (clk->set_rate) 171 return clk->set_rate(sc, clk, rate); 172 173 return ENXIO; 174 } 175 176 static u_int 177 rk_cru_clock_round_rate(void *priv, struct clk *clkp, u_int rate) 178 { 179 struct rk_cru_softc * const sc = priv; 180 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 181 struct clk *clkp_parent; 182 183 if (clkp->flags & CLK_SET_RATE_PARENT) { 184 clkp_parent = clk_get_parent(clkp); 185 if (clkp_parent == NULL) { 186 aprint_error("%s: no parent for %s\n", __func__, clk->base.name); 187 return 0; 188 } 189 return clk_round_rate(clkp_parent, rate); 190 } 191 192 if (clk->round_rate) 193 return clk->round_rate(sc, clk, rate); 194 195 return 0; 196 } 197 198 static int 199 rk_cru_clock_enable(void *priv, struct clk *clkp) 200 { 201 struct rk_cru_softc * const sc = priv; 202 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 203 struct clk *clkp_parent; 204 int error = 0; 205 206 clkp_parent = clk_get_parent(clkp); 207 if (clkp_parent != NULL) { 208 error = clk_enable(clkp_parent); 209 if (error != 0) 210 return error; 211 } 212 213 if (clk->enable) 214 error = clk->enable(sc, clk, 1); 215 216 return error; 217 } 218 219 static int 220 rk_cru_clock_disable(void *priv, struct clk *clkp) 221 { 222 struct rk_cru_softc * const sc = priv; 223 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 224 int error = EINVAL; 225 226 if (clk->enable) 227 error = clk->enable(sc, clk, 0); 228 229 return error; 230 } 231 232 static int 233 rk_cru_clock_set_parent(void *priv, struct clk *clkp, 234 struct clk *clkp_parent) 235 { 236 struct rk_cru_softc * const sc = priv; 237 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 238 239 if (clk->set_parent == NULL) 240 return EINVAL; 241 242 return clk->set_parent(sc, clk, clkp_parent->name); 243 } 244 245 static struct clk * 246 rk_cru_clock_get_parent(void *priv, struct clk *clkp) 247 { 248 struct rk_cru_softc * const sc = priv; 249 struct rk_cru_clk *clk = (struct rk_cru_clk *)clkp; 250 struct rk_cru_clk *clk_parent; 251 const char *parent; 252 253 if (clk->get_parent == NULL) 254 return NULL; 255 256 parent = clk->get_parent(sc, clk); 257 if (parent == NULL) 258 return NULL; 259 260 clk_parent = rk_cru_clock_find(sc, parent); 261 if (clk_parent != NULL) 262 return &clk_parent->base; 263 264 /* No parent in this domain, try FDT */ 265 return fdtbus_clock_byname(parent); 266 } 267 268 static const struct clk_funcs rk_cru_clock_funcs = { 269 .get = rk_cru_clock_get, 270 .put = rk_cru_clock_put, 271 .get_rate = rk_cru_clock_get_rate, 272 .set_rate = rk_cru_clock_set_rate, 273 .round_rate = rk_cru_clock_round_rate, 274 .enable = rk_cru_clock_enable, 275 .disable = rk_cru_clock_disable, 276 .set_parent = rk_cru_clock_set_parent, 277 .get_parent = rk_cru_clock_get_parent, 278 }; 279 280 struct rk_cru_clk * 281 rk_cru_clock_find(struct rk_cru_softc *sc, const char *name) 282 { 283 for (int i = 0; i < sc->sc_nclks; i++) { 284 if (sc->sc_clks[i].base.name == NULL) 285 continue; 286 if (strcmp(sc->sc_clks[i].base.name, name) == 0) 287 return &sc->sc_clks[i]; 288 } 289 290 return NULL; 291 } 292 293 int 294 rk_cru_attach(struct rk_cru_softc *sc) 295 { 296 bus_addr_t addr; 297 bus_size_t size; 298 int i; 299 300 if (of_hasprop(sc->sc_phandle, "rockchip,grf")) { 301 sc->sc_grf = fdtbus_syscon_acquire(sc->sc_phandle, "rockchip,grf"); 302 if (sc->sc_grf == NULL) { 303 aprint_error(": couldn't get grf syscon\n"); 304 return ENXIO; 305 } 306 } 307 308 if (fdtbus_get_reg(sc->sc_phandle, 0, &addr, &size) != 0) { 309 aprint_error(": couldn't get registers\n"); 310 return ENXIO; 311 } 312 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 313 aprint_error(": couldn't map registers\n"); 314 return ENXIO; 315 } 316 317 sc->sc_clkdom.name = device_xname(sc->sc_dev); 318 sc->sc_clkdom.funcs = &rk_cru_clock_funcs; 319 sc->sc_clkdom.priv = sc; 320 for (i = 0; i < sc->sc_nclks; i++) { 321 sc->sc_clks[i].base.domain = &sc->sc_clkdom; 322 clk_attach(&sc->sc_clks[i].base); 323 } 324 325 fdtbus_register_clock_controller(sc->sc_dev, sc->sc_phandle, 326 &rk_cru_fdtclock_funcs); 327 328 fdtbus_register_reset_controller(sc->sc_dev, sc->sc_phandle, 329 &rk_cru_fdtreset_funcs); 330 331 return 0; 332 } 333 334 void 335 rk_cru_print(struct rk_cru_softc *sc) 336 { 337 struct rk_cru_clk *clk; 338 struct clk *clkp_parent; 339 const char *type; 340 int i; 341 342 for (i = 0; i < sc->sc_nclks; i++) { 343 clk = &sc->sc_clks[i]; 344 if (clk->type == RK_CRU_UNKNOWN) 345 continue; 346 347 clkp_parent = clk_get_parent(&clk->base); 348 349 switch (clk->type) { 350 case RK_CRU_PLL: type = "pll"; break; 351 case RK_CRU_ARM: type = "arm"; break; 352 case RK_CRU_COMPOSITE: type = "comp"; break; 353 case RK_CRU_GATE: type = "gate"; break; 354 case RK_CRU_MUX: type = "mux"; break; 355 default: type = "???"; break; 356 } 357 358 aprint_debug_dev(sc->sc_dev, 359 "%3d %-14s %2s %-14s %-7s ", 360 clk->id, 361 clk->base.name, 362 clkp_parent ? "<-" : "", 363 clkp_parent ? clkp_parent->name : "", 364 type); 365 aprint_debug("%10d Hz\n", clk_get_rate(&clk->base)); 366 } 367 } 368