1/* $NetBSD: ofw_irq.S,v 1.3 2003/11/05 21:10:59 scw Exp $ */ 2 3/* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Low level irq and fiq handlers 38 * 39 * Created : 27/09/94 40 */ 41 42#include "opt_irqstats.h" 43 44#include "assym.h" 45#include <machine/asm.h> 46#include <machine/cpu.h> 47#include <machine/frame.h> 48#include <machine/irqhandler.h> 49 50 .text 51 .align 0 52 53/* 54 * 55 * irq_entry 56 * 57 * Main entry point for the IRQ vector 58 * 59 * This function is called only on timer ticks, passed on to the 60 * kernel from the OFW tick handler. 61 * 62 * For now, I am trying to re-use as much of the code from the 63 * IOMD interrupt-handler as possible. In time, I will strip this 64 * down to something OFW-specific. 65 * 66 * Here's the original, IOMD-specific description: 67 * This function reads the irq request bits in the IOMD registers 68 * IRQRQA, IRQRQB and DMARQ 69 * It then calls an installed handler for each bit that is set. 70 * The function stray_irqhandler is called if a handler is not defined 71 * for a particular interrupt. 72 * If a interrupt handler is found then it is called with r0 containing 73 * the argument defined in the handler structure. If the field ih_arg 74 * is zero then a pointer to the IRQ frame on the stack is passed instead. 75 */ 76 77Ldisabled_mask: 78 .word _C_LABEL(disabled_mask) 79 80Lcurrent_spl_level: 81 .word _C_LABEL(current_spl_level) 82 83Lcurrent_intr_depth: 84 .word _C_LABEL(current_intr_depth) 85 86Lspl_masks: 87 .word _C_LABEL(spl_masks) 88 89Lofw_ticktmp: 90 .word _C_LABEL(ofw_ticktmp) 91 92Lirq_entry: 93 .word irq_entry 94 95Lofwirqstk: /* hack */ 96 .word ofwirqstk + 4096 97 98AST_ALIGNMENT_FAULT_LOCALS 99 100/* 101 * Regsister usage 102 * 103 * r6 - Address of current handler 104 * r7 - Pointer to handler pointer list 105 * r8 - Current IRQ requests. 106 * r9 - Used to count through possible IRQ bits. 107 * r10 - Base address of IOMD 108 */ 109 110ASENTRY_NP(irq_entry) 111 /* 112 * We come here following an OFW-handled timer tick. 113 * 114 * We are in the SVC frame, and interrupts are disabled. 115 * The state of the interrupted context is partially in 116 * the registers and partially in the global storage area 117 * labeled ofw_ticktmp. ofw_ticktmp is filled-in by the 118 * tick callback that is invoked by OFW on the way out of 119 * its interrupt handler. ofw_ticktmp contains the following: 120 * 121 * pc // interrupted instruction 122 * lr_usr 123 * sp_usr 124 * r1 // makes r1 available for scratch 125 * r0 // makes r0 available for scratch 126 * spsr_svc // cpsr of interrupted context 127 * 128 * The prologue of this routine must re-construct the 129 * machine state that existed at the time OFW's interrupt- 130 * handler fielded the interrupt. That allows us to use 131 * the rest of the code in this routine, and have it all 132 * "just work." 133 */ 134 135 /* 136 * Switch to IRQ mode. 137 * First check the spsr in ofw_ticktmp to see what the FIQ bit should be. 138 * 139 * I need 2 scratch registers to do this. 140 * Fortunately, r0 and r1 are already saved in ofw_ticktmp. 141 * How convenient. 142 */ 143 ldr r0, Lofw_ticktmp 144 ldr r0, [r0] 145 and r0, r0, #F32_bit 146 mov r1, #(I32_bit | PSR_IRQ32_MODE) 147 orr r1, r1, r0 148 msr cpsr_all, r1 149 150 /* Now we're in IRQ mode. */ 151 /* Restore contents of ofw_ticktmp. */ 152 adr r0, Lofwirqstk /* Bummer! Mitch hasn't left me a stack. */ 153 ldr sp, [r0] /* I'll use my own for now... */ 154 ldr r0, Lofw_ticktmp /* r0 now points to ofw_ticktmp[0] */ 155 ldr r1, [r0], #(4*3) /* skip over saved {r0, r1} */ 156 msr spsr_all, r1 /* restore spsr */ 157 ldmia r0, {sp, lr}^ /* restore user sp and lr */ 158 add r0, r0, #(4*2) /* previous instruction can't writeback */ 159 /* this one can't use banked registers */ 160 ldr lr, [r0], #(-4*4) /* restore pc; point r0 at ofw_ticktmp[1] */ 161 add lr, lr, #4 /* pc += 4; will be decremented below */ 162 ldmia r0, {r0, r1} /* restore r0 and r1 */ 163 164 /* OK, the machine state should be identical now to that when */ 165 /* OFW fielded the interrupt. So just fall through... */ 166 167 sub lr, lr, #0x00000004 /* Adjust the lr */ 168 169 PUSHFRAMEINSVC /* Push an interrupt frame */ 170 171 /* 172 * Can't field this interrupt now if priority is _SPL_CLOCK 173 * or higher. For now, we'll just ignore the interrupt. 174 * Soon, we will have to schedule it for later action. 175 */ 176 ldr r0, Lcurrent_spl_level 177 ldr r0, [r0] 178 cmp r0, #_SPL_CLOCK 179 blt ofwtakeint 180 181 PULLFRAMEFROMSVCANDEXIT 182 movs pc, lr /* Exit */ 183 184 /* 185 * Stuff a bit-mask into r8 indicating which interrupts 186 * are pending. In our case, that is just the timer0 187 * interrupt: (1 << TIMER0). The existing code will take 188 * care of invoking that handler and the softint/ast stuff 189 * which follows it. 190 */ 191ofwtakeint: 192#if defined(COMPAT_15) && defined(EXEC_AOUT) 193 ldr r0, [sp] /* Fetch SPSR */ 194#endif 195 ENABLE_ALIGNMENT_FAULTS 196 197 mov r8, #0x00000001 /* timer interrupt pending! */ 198 mov r8, r8, lsl #IRQ_TIMER0 199 200 /* 201 * Note that we have entered the IRQ handler. 202 * We are in SVC mode so we cannot use the processor mode 203 * to determine if we are in an IRQ. Instead we will count the 204 * each time the interrupt handler is nested. 205 */ 206 207 ldr r0, Lcurrent_intr_depth 208 ldr r1, [r0] 209 add r1, r1, #1 210 str r1, [r0] 211 212 /* Block the current requested interrupts */ 213 ldr r1, Ldisabled_mask 214 ldr r0, [r1] 215 stmfd sp!, {r0} 216 orr r0, r0, r8 217 218 /* 219 * Need to block all interrupts at the IPL or lower for 220 * all asserted interrupts. 221 * This basically emulates hardware interrupt priority levels. 222 * Means we need to go through the interrupt mask and for 223 * every asserted interrupt we need to mask out all other 224 * interrupts at the same or lower IPL. 225 * If only we could wait until the main loop but we need to sort 226 * this out first so interrupts can be re-enabled. 227 * 228 * This would benefit from a special ffs type routine 229 */ 230 231 mov r9, #(_SPL_LEVELS - 1) 232 ldr r7, Lspl_masks 233 234Lfind_highest_ipl: 235 ldr r2, [r7, r9, lsl #2] 236 tst r8, r2 237 subeq r9, r9, #1 238 beq Lfind_highest_ipl 239 240 /* r9 = SPL level of highest priority interrupt */ 241 add r9, r9, #1 242 ldr r2, [r7, r9, lsl #2] 243 mvn r2, r2 244 orr r0, r0, r2 245 246 str r0, [r1] 247 248 ldr r0, Lcurrent_spl_level 249 ldr r1, [r0] 250 str r9, [r0] 251 stmfd sp!, {r1} 252 253 /* Update the irq masks */ 254 bl _C_LABEL(irq_setmasks) 255 256 mrs r0, cpsr_all /* Enable IRQ's */ 257 bic r0, r0, #I32_bit 258 msr cpsr_all, r0 259 260 ldr r7, Lirqhandlers 261 mov r9, #0x00000001 262 263irqloop: 264 /* This would benefit from a special ffs type routine */ 265 tst r8, r9 /* Is a bit set ? */ 266 beq nextirq /* No ? try next bit */ 267 268 ldr r6, [r7] /* Get address of first handler structure */ 269 270 teq r6, #0x00000000 /* Do we have a handler */ 271 moveq r0, r8 /* IRQ requests as arg 0 */ 272 beq _C_LABEL(stray_irqhandler) /* call special handler */ 273 274 ldr r0, Lcnt 275 ldr r1, [r0, #(V_INTR)] 276 add r1, r1, #0x00000001 277 str r1, [r0, #(V_INTR)] 278 279/* 280 * XXX: Should stats be accumlated for every interrupt routine called 281 * or for every physical interrupt that is serviced. 282 */ 283 284#ifdef IRQSTATS 285 ldr r0, Lintrcnt 286 ldr r1, [r6, #(IH_NUM)] 287 288 add r0, r0, r1, lsl #2 289 ldr r1, [r0] 290 add r1, r1, #0x00000001 291 str r1, [r0] 292#endif /* IRQSTATS */ 293 294irqchainloop: 295 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 296 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 297 addeq r0, sp, #8 /* ... stack frame */ 298 mov lr, pc /* return address */ 299 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 300 301 teq r0, #0x00000001 /* Was the irq serviced ? */ 302 beq irqdone 303 304 ldr r6, [r6, #(IH_NEXT)] 305 teq r6, #0x00000000 306 bne irqchainloop 307 308irqdone: 309nextirq: 310 add r7, r7, #0x00000004 /* update pointer to handlers */ 311 mov r9, r9, lsl #1 /* move on to next bit */ 312 teq r9, #(1 << 24) /* done the last bit ? */ 313 bne irqloop /* no - loop back. */ 314 315 ldmfd sp!, {r2} 316 ldr r1, Lcurrent_spl_level 317 str r2, [r1] 318 319 /* Restore previous disabled mask */ 320 ldmfd sp!, {r2} 321 ldr r1, Ldisabled_mask 322 str r2, [r1] 323 bl _C_LABEL(irq_setmasks) 324 325 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 326 327 /* Kill IRQ's in preparation for exit */ 328 mrs r0, cpsr_all 329 orr r0, r0, #(I32_bit) 330 msr cpsr_all, r0 331 332 /* Decrement the nest count */ 333 ldr r0, Lcurrent_intr_depth 334 ldr r1, [r0] 335 sub r1, r1, #1 336 str r1, [r0] 337 338 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 339 PULLFRAMEFROMSVCANDEXIT 340 movs pc, lr /* Exit */ 341 342Lspl_mask: 343 .word _C_LABEL(spl_mask) /* irq's allowed at current spl level */ 344 345Lcurrent_mask: 346 .word _C_LABEL(current_mask) /* irq's that are usable */ 347 348 349ENTRY(irq_setmasks) 350 /* Do nothing */ 351 mov pc, lr 352 353 354Lcnt: 355 .word _C_LABEL(uvmexp) 356 357Lintrcnt: 358 .word _C_LABEL(intrcnt) 359 360 361Lirqhandlers: 362 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 363 364 .text 365 .global _C_LABEL(dotickgrovelling) 366 367/* 368 * Do magic to cause OFW to call our irq_entry 369 * routine when it returns from its tick-handling. 370 * 371 * This consists of two sub-tasks: 372 * - save some machine state in ofw_ticktmp 373 * - punch some new machine state into the 374 * OFW-supplied frame 375 * 376 * We are running in the IRQ frame, with 377 * interrupts disabled. 378 * 379 * r0 - base of saved OFW interrupt frame, which 380 * has the following format: 381 * 382 * pc // interrupted instruction 383 * lr // lr of interrupted context 384 * sp // sp of interrupted context 385 * r12 386 * ... // non-banked register values 387 * ... // of interrupted context 388 * r0 389 * spsr // psr of interrupted context 390 * 391 */ 392 393_C_LABEL(dotickgrovelling): 394 /*assert((cpsr & PSR_MODE) == PSR_IRQ32_MODE);*/ 395 396 stmfd sp!, {r1-r5} /* scratch registers r1-r5 */ 397 398 /* 399 * Sub-task 1: 400 * 401 * Our irq_entry routine needs to re-construct 402 * the state of the machine at the time OFW 403 * fielded the interrupt, so that we can use 404 * the rest of the standard interrupt-handling 405 * code. Specifically, irq_entry needs to get 406 * at the following machine state: 407 * 408 * pc // interrupted instruction 409 * lr_usr 410 * sp_usr 411 * r0-r12 // the non-banked registers 412 * // at the time of interruption 413 * spsr // cpsr of interrupted context 414 * 415 * The non-banked registers will be valid at the 416 * time irq_entry is called, but the other values 417 * will not be. We must save them here, in the 418 * ofw_ticktmp storage block. We also save r0 419 * and r1 so that we have some free registers 420 * when it's time to do the re-construction. 421 * 422 * Note that interrupts are not enabled before 423 * irq_entry is entered, so we don't have to 424 * worry about ofw_ticktmp getting clobbered. 425 */ 426 ldr r1, Lofw_ticktmp /* r1 points to ofw_ticktmp[0] */ 427 428 ldr r2, [r0, #0] /* ofwframe[0] is spsr */ 429 stmia r1!, {r2} /* put it in ofw_ticktmp[0] */ 430 431 ldr r2, [r0, #(4*1)] /* ofwframe[1] is saved r0 */ 432 stmia r1!, {r2} /* put it in ofw_ticktmp[1] */ 433 434 ldr r2, [r0, #(4*2)] /* ofwframe[2] is saved r1 */ 435 stmia r1!, {r2} /* put it in ofw_ticktmp[2] */ 436 437 stmia r1, {sp, lr}^ /* put {sp,lr}_usr in ofw_ticktmp[3,4]; */ 438 /* the user registers are still valid */ 439 /* because we haven't left IRQ mode */ 440 add r1, r1, #(4*2) /* previous instruction can't writeback */ 441 /* this one can't use banked registers */ 442 443 ldr r2, [r0, #(4*16)] /* ofwframe[16] is pc */ 444 stmia r1!, {r2} /* put it in ofw_ticktmp[5] */ 445 446 447 /* 448 * Sub-task 2: 449 * 450 * Diddle the OFW-supplied frame such that 451 * control passes to irq_entry when OFW does 452 * its return from interrupt. There are 4 453 * fields in that frame that we need to plug: 454 * 455 * pc // gets irq_entry 456 * lr // gets lr_svc 457 * sp // gets sp_svc 458 * spsr // gets (I32_bit | PSR_SVC32_MODE) 459 * 460 */ 461 mov r1, #(I32_bit | PSR_SVC32_MODE) 462 str r1, [r0, #0] /* plug spsr */ 463 464 /* Sneak into SVC mode to get sp and lr */ 465 mrs r3, cpsr_all 466 bic r3, r3, #(PSR_MODE) 467 orr r3, r3, #(PSR_SVC32_MODE) 468 msr cpsr_all, r3 469 mov r4, lr /* snarf lr_svc */ 470 mov r5, sp /* snarf sp_svc */ 471 bic r3, r3, #(PSR_MODE) 472 orr r3, r3, #(PSR_IRQ32_MODE) 473 msr cpsr_all, r3 474 str r5, [r0, #(4*14)] /* plug sp */ 475 str r4, [r0, #(4*15)] /* plug lr */ 476 477 ldr r1, Lirq_entry 478 str r1, [r0, #(4*16)] /* plug pc */ 479 480 ldmfd sp!, {r1-r5} 481 mov pc, lr 482 483 484 .bss 485 .align 0 486 487_C_LABEL(ofw_ticktmp): 488 .space 4 * 6 /* temporary storage for 6 words of machine state */ 489 490ofwirqstk: /* hack */ 491 .space 4096 492 493#ifdef IRQSTATS 494/* These symbols are used by vmstat */ 495 496 .text 497 .global _C_LABEL(_intrnames) 498_C_LABEL(_intrnames): 499 .word _C_LABEL(intrnames) 500 501 .data 502 503 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt) 504_C_LABEL(intrnames): 505 .asciz "interrupt 0 " 506 .asciz "interrupt 1 " 507 .asciz "interrupt 2 " 508 .asciz "interrupt 3 " 509 .asciz "interrupt 4 " 510 .asciz "interrupt 5 " 511 .asciz "interrupt 6 " 512 .asciz "interrupt 7 " 513 .asciz "interrupt 8 " 514 .asciz "interrupt 9 " 515 .asciz "interrupt 10 " 516 .asciz "interrupt 11 " 517 .asciz "interrupt 12 " 518 .asciz "interrupt 13 " 519 .asciz "interrupt 14 " 520 .asciz "interrupt 15 " 521 .asciz "interrupt 16 " 522 .asciz "interrupt 17 " 523 .asciz "interrupt 18 " 524 .asciz "interrupt 19 " 525 .asciz "interrupt 20 " 526 .asciz "interrupt 21 " 527 .asciz "interrupt 22 " 528 .asciz "interrupt 23 " 529 .asciz "interrupt 24 " 530 .asciz "interrupt 25 " 531 .asciz "interrupt 26 " 532 .asciz "interrupt 27 " 533 .asciz "interrupt 28 " 534 .asciz "interrupt 29 " 535 .asciz "interrupt 30 " 536 .asciz "interrupt 31 " 537 538_C_LABEL(sintrnames): 539 .asciz "softclock " 540 .asciz "softnet " 541 .asciz "softserial " 542 .asciz "softintr 3 " 543 .asciz "softintr 4 " 544 .asciz "softintr 5 " 545 .asciz "softintr 6 " 546 .asciz "softintr 7 " 547 .asciz "softintr 8 " 548 .asciz "softintr 9 " 549 .asciz "softintr 10 " 550 .asciz "softintr 11 " 551 .asciz "softintr 12 " 552 .asciz "softintr 13 " 553 .asciz "softintr 14 " 554 .asciz "softintr 15 " 555 .asciz "softintr 16 " 556 .asciz "softintr 17 " 557 .asciz "softintr 18 " 558 .asciz "softintr 19 " 559 .asciz "softintr 20 " 560 .asciz "softintr 21 " 561 .asciz "softintr 22 " 562 .asciz "softintr 23 " 563 .asciz "softintr 24 " 564 .asciz "softintr 25 " 565 .asciz "softintr 26 " 566 .asciz "softintr 27 " 567 .asciz "softintr 28 " 568 .asciz "softintr 29 " 569 .asciz "softintr 30 " 570 .asciz "softintr 31 " 571_C_LABEL(eintrnames): 572 573 .bss 574 .align 0 575_C_LABEL(intrcnt): 576 .space 32*4 /* XXX Should be linked to number of interrupts */ 577 578_C_LABEL(sintrcnt): 579 .space 32*4 /* XXX Should be linked to number of interrupts */ 580_C_LABEL(eintrcnt): 581 582#else /* IRQSTATS */ 583/* Dummy entries to keep vmstat happy */ 584 585 .text 586 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 587_C_LABEL(intrnames): 588 .long 0 589_C_LABEL(eintrnames): 590 591_C_LABEL(intrcnt): 592 .long 0 593_C_LABEL(eintrcnt): 594#endif /* IRQSTATS */ 595