1/* $NetBSD: ofw_irq.S,v 1.15 2013/12/02 18:36:10 joerg Exp $ */ 2 3/* 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Mark Brinicombe 21 * for the NetBSD Project. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Low level irq and fiq handlers 38 * 39 * Created : 27/09/94 40 */ 41 42#include "assym.h" 43#include <arm/asm.h> 44#include <arm/locore.h> 45 46#include <machine/irqhandler.h> 47 48 .text 49 .align 0 50 51/* 52 * 53 * irq_entry 54 * 55 * Main entry point for the IRQ vector 56 * 57 * This function is called only on timer ticks, passed on to the 58 * kernel from the OFW tick handler. 59 * 60 * For now, I am trying to re-use as much of the code from the 61 * IOMD interrupt-handler as possible. In time, I will strip this 62 * down to something OFW-specific. 63 * 64 * Here's the original, IOMD-specific description: 65 * This function reads the irq request bits in the IOMD registers 66 * IRQRQA, IRQRQB and DMARQ 67 * It then calls an installed handler for each bit that is set. 68 * The function stray_irqhandler is called if a handler is not defined 69 * for a particular interrupt. 70 * If a interrupt handler is found then it is called with r0 containing 71 * the argument defined in the handler structure. If the field ih_arg 72 * is zero then a pointer to the IRQ frame on the stack is passed instead. 73 */ 74 75Ldisabled_mask: 76 .word _C_LABEL(disabled_mask) 77 78Lspl_masks: 79 .word _C_LABEL(spl_masks) 80 81Lofw_ticktmp: 82 .word _C_LABEL(ofw_ticktmp) 83 84Lirq_entry: 85 .word irq_entry 86 87Lofwirqstk: /* hack */ 88 .word ofwirqstk + 4096 89 90LOCK_CAS_CHECK_LOCALS 91 92AST_ALIGNMENT_FAULT_LOCALS 93 94/* 95 * Regsister usage 96 * 97 * r4 - Address of cpu_info (on entry) 98 * r5 - Pointer to handler pointer list 99 * r6 - Address of current handler 100 * r7 - pspr mode (must be preserved) 101 * r8 - Current IRQ requests. 102 * r9 - Used to count through possible IRQ bits. 103 * r10 - Base address of IOMD 104 */ 105 106ASENTRY_NP(irq_entry) 107 /* 108 * We come here following an OFW-handled timer tick. 109 * 110 * We are in the SVC frame, and interrupts are disabled. 111 * The state of the interrupted context is partially in 112 * the registers and partially in the global storage area 113 * labeled ofw_ticktmp. ofw_ticktmp is filled-in by the 114 * tick callback that is invoked by OFW on the way out of 115 * its interrupt handler. ofw_ticktmp contains the following: 116 * 117 * pc // interrupted instruction 118 * lr_usr 119 * sp_usr 120 * r1 // makes r1 available for scratch 121 * r0 // makes r0 available for scratch 122 * spsr_svc // cpsr of interrupted context 123 * 124 * The prologue of this routine must re-construct the 125 * machine state that existed at the time OFW's interrupt- 126 * handler fielded the interrupt. That allows us to use 127 * the rest of the code in this routine, and have it all 128 * "just work." 129 */ 130 131 /* 132 * Switch to IRQ mode. 133 * First check the spsr in ofw_ticktmp to see what the FIQ bit should be. 134 * 135 * I need 2 scratch registers to do this. 136 * Fortunately, r0 and r1 are already saved in ofw_ticktmp. 137 * How convenient. 138 */ 139 ldr r0, Lofw_ticktmp 140 ldr r0, [r0] 141 and r0, r0, #F32_bit 142 mov r1, #(I32_bit | PSR_IRQ32_MODE) 143 orr r1, r1, r0 144 msr cpsr_all, r1 145 146 /* Now we're in IRQ mode. */ 147 /* Restore contents of ofw_ticktmp. */ 148 adr r0, Lofwirqstk /* Bummer! Mitch hasn't left me a stack. */ 149 ldr sp, [r0] /* I'll use my own for now... */ 150 ldr r0, Lofw_ticktmp /* r0 now points to ofw_ticktmp[0] */ 151 ldr r1, [r0], #(4*3) /* skip over saved {r0, r1} */ 152 msr spsr_all, r1 /* restore spsr */ 153 ldmia r0, {sp, lr}^ /* restore user sp and lr */ 154 add r0, r0, #(4*2) /* previous instruction can't writeback */ 155 /* this one can't use banked registers */ 156 ldr lr, [r0], #(-4*4) /* restore pc; point r0 at ofw_ticktmp[1] */ 157 add lr, lr, #4 /* pc += 4; will be decremented below */ 158 ldmia r0, {r0, r1} /* restore r0 and r1 */ 159 160 /* OK, the machine state should be identical now to that when */ 161 /* OFW fielded the interrupt. So just fall through... */ 162 163 sub lr, lr, #0x00000004 /* Adjust the lr */ 164 165 PUSHFRAMEINSVC /* Push an interrupt frame */ 166 167 /* 168 * Can't field this interrupt now if priority is IPL_CLOCK 169 * or higher. For now, we'll just ignore the interrupt. 170 * Soon, we will have to schedule it for later action. 171 */ 172 ldr r0, Lcurrent_spl_level 173 ldr r0, [r4, #CI_CPL] 174 cmp r0, #IPL_CLOCK 175 blt ofwtakeint 176 177 PULLFRAMEFROMSVCANDEXIT 178 movs pc, lr /* Exit */ 179 180 /* 181 * Stuff a bit-mask into r8 indicating which interrupts 182 * are pending. In our case, that is just the timer0 183 * interrupt: (1 << TIMER0). The existing code will take 184 * care of invoking that handler and the softint/ast stuff 185 * which follows it. 186 */ 187ofwtakeint: 188#ifdef EXEC_AOUT 189 ldr r0, [sp] /* Fetch SPSR */ 190#endif 191 ENABLE_ALIGNMENT_FAULTS 192 193 mov r8, #0x00000001 /* timer interrupt pending! */ 194 mov r8, r8, lsl #IRQ_TIMER0 195 196 /* 197 * Note that we have entered the IRQ handler. 198 * We are in SVC mode so we cannot use the processor mode 199 * to determine if we are in an IRQ. Instead we will count the 200 * each time the interrupt handler is nested. 201 */ 202 203 ldr r1, [r4, #CI_INTR_DEPTH] 204 add r1, r1, #1 205 str r1, [r4, #CI_INTR_DEPTH] 206 207 /* Block the current requested interrupts */ 208 ldr r1, Ldisabled_mask 209 ldr r0, [r1] 210 stmfd sp!, {r0} 211 orr r0, r0, r8 212 213 /* 214 * Need to block all interrupts at the IPL or lower for 215 * all asserted interrupts. 216 * This basically emulates hardware interrupt priority levels. 217 * Means we need to go through the interrupt mask and for 218 * every asserted interrupt we need to mask out all other 219 * interrupts at the same or lower IPL. 220 * If only we could wait until the main loop but we need to sort 221 * this out first so interrupts can be re-enabled. 222 * 223 * This would benefit from a special ffs type routine 224 */ 225 226 mov r9, #(NIPL - 1) 227 ldr r5, Lspl_masks 228 229Lfind_highest_ipl: 230 ldr r2, [r5, r9, lsl #2] 231 tst r8, r2 232 subeq r9, r9, #1 233 beq Lfind_highest_ipl 234 235 /* r9 = SPL level of highest priority interrupt */ 236 add r9, r9, #1 237 ldr r2, [r5, r9, lsl #2] 238 mvn r2, r2 239 orr r0, r0, r2 240 241 str r0, [r1] 242 243 ldr r0, Lcurrent_spl_level 244 ldr r1, [r4, #CI_CPL] 245 str r9, [r4, #CI_CPL] 246 stmfd sp!, {r1} 247 248 /* Update the irq masks */ 249 bl _C_LABEL(irq_setmasks) 250 251 mrs r0, cpsr /* Enable IRQ's */ 252 bic r0, r0, #I32_bit 253 msr cpsr_all, r0 254 255 ldr r5, Lirqhandlers 256 mov r9, #0x00000001 257 258irqloop: 259 /* This would benefit from a special ffs type routine */ 260 tst r8, r9 /* Is a bit set ? */ 261 beq nextirq /* No ? try next bit */ 262 263 ldr r6, [r5] /* Get address of first handler structure */ 264 265 teq r6, #0x00000000 /* Do we have a handler */ 266 moveq r0, r8 /* IRQ requests as arg 0 */ 267 beq _C_LABEL(stray_irqhandler) /* call special handler */ 268 269 ldr r1, [r4, #(CI_CC_NINTR)] 270 ldr r2, [r4, #(CI_CC_NINTR+4)] 271#ifdef _ARMEL 272 adds r1, r1, #0x00000001 273 adc r2, r2, #0x00000000 274#else 275 adds r2, r2, #0x00000001 276 adc r1, r1, #0x00000000 277#endif 278 str r1, [r4, #(CI_CC_NINTR)] 279 str r2, [r4, #(CI_CC_NINTR+4)] 280 281irqchainloop: 282 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 283 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 284 addeq r0, sp, #8 /* ... stack frame */ 285 mov lr, pc /* return address */ 286 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 287 288 teq r0, #0x00000001 /* Was the irq serviced ? */ 289 beq irqdone 290 291 ldr r6, [r6, #(IH_NEXT)] 292 teq r6, #0x00000000 293 bne irqchainloop 294 b nextirq 295 296irqdone: 297 add r3, r6, #IH_EV_COUNT /* get address of ih's ev_count */ 298 ldmia r3, {r1-r2} /* load ev_count */ 299 adds r1, r1, #0x00000001 /* 64bit incr (lo) */ 300 adc r2, r2, #0x00000000 /* 64bit incr (hi) */ 301 stmia r3, {r1-r2} /* store ev_count */ 302 303nextirq: 304 add r5, r5, #0x00000004 /* update pointer to handlers */ 305 mov r9, r9, lsl #1 /* move on to next bit */ 306 teq r9, #(1 << 24) /* done the last bit ? */ 307 bne irqloop /* no - loop back. */ 308 309 ldmfd sp!, {r2} 310 str r2, [r4, #CI_CPL] 311 312 /* Restore previous disabled mask */ 313 ldmfd sp!, {r2} 314 ldr r1, Ldisabled_mask 315 str r2, [r1] 316 bl _C_LABEL(irq_setmasks) 317 318 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 319 320 /* Kill IRQ's in preparation for exit */ 321 mrs r0, cpsr 322 orr r0, r0, #(I32_bit) 323 msr cpsr_all, r0 324 325 /* Decrement the nest count */ 326 ldr r1, [r4, #CI_INTR_DEPTH] 327 sub r1, r1, #1 328 str r1, [r4, #CI_INTR_DEPTH] 329 330 LOCK_CAS_CHECK 331 332 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 333 PULLFRAMEFROMSVCANDEXIT 334 movs pc, lr /* Exit */ 335 336Lcurrent_mask: 337 .word _C_LABEL(current_mask) /* irq's that are usable */ 338 339 340ENTRY(irq_setmasks) 341 /* Do nothing */ 342 mov pc, lr 343 344 345Lirqhandlers: 346 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 347 348 .text 349 .global _C_LABEL(dotickgrovelling) 350 351/* 352 * Do magic to cause OFW to call our irq_entry 353 * routine when it returns from its tick-handling. 354 * 355 * This consists of two sub-tasks: 356 * - save some machine state in ofw_ticktmp 357 * - punch some new machine state into the 358 * OFW-supplied frame 359 * 360 * We are running in the IRQ frame, with 361 * interrupts disabled. 362 * 363 * r0 - base of saved OFW interrupt frame, which 364 * has the following format: 365 * 366 * pc // interrupted instruction 367 * lr // lr of interrupted context 368 * sp // sp of interrupted context 369 * r12 370 * ... // non-banked register values 371 * ... // of interrupted context 372 * r0 373 * spsr // psr of interrupted context 374 * 375 */ 376 377_C_LABEL(dotickgrovelling): 378 /*assert((cpsr & PSR_MODE) == PSR_IRQ32_MODE);*/ 379 380 stmfd sp!, {r1-r5} /* scratch registers r1-r5 */ 381 382 /* 383 * Sub-task 1: 384 * 385 * Our irq_entry routine needs to re-construct 386 * the state of the machine at the time OFW 387 * fielded the interrupt, so that we can use 388 * the rest of the standard interrupt-handling 389 * code. Specifically, irq_entry needs to get 390 * at the following machine state: 391 * 392 * pc // interrupted instruction 393 * lr_usr 394 * sp_usr 395 * r0-r12 // the non-banked registers 396 * // at the time of interruption 397 * spsr // cpsr of interrupted context 398 * 399 * The non-banked registers will be valid at the 400 * time irq_entry is called, but the other values 401 * will not be. We must save them here, in the 402 * ofw_ticktmp storage block. We also save r0 403 * and r1 so that we have some free registers 404 * when it's time to do the re-construction. 405 * 406 * Note that interrupts are not enabled before 407 * irq_entry is entered, so we don't have to 408 * worry about ofw_ticktmp getting clobbered. 409 */ 410 ldr r1, Lofw_ticktmp /* r1 points to ofw_ticktmp[0] */ 411 412 ldr r2, [r0, #0] /* ofwframe[0] is spsr */ 413 stmia r1!, {r2} /* put it in ofw_ticktmp[0] */ 414 415 ldr r2, [r0, #(4*1)] /* ofwframe[1] is saved r0 */ 416 stmia r1!, {r2} /* put it in ofw_ticktmp[1] */ 417 418 ldr r2, [r0, #(4*2)] /* ofwframe[2] is saved r1 */ 419 stmia r1!, {r2} /* put it in ofw_ticktmp[2] */ 420 421 stmia r1, {sp, lr}^ /* put {sp,lr}_usr in ofw_ticktmp[3,4]; */ 422 /* the user registers are still valid */ 423 /* because we haven't left IRQ mode */ 424 add r1, r1, #(4*2) /* previous instruction can't writeback */ 425 /* this one can't use banked registers */ 426 427 ldr r2, [r0, #(4*16)] /* ofwframe[16] is pc */ 428 stmia r1!, {r2} /* put it in ofw_ticktmp[5] */ 429 430 431 /* 432 * Sub-task 2: 433 * 434 * Diddle the OFW-supplied frame such that 435 * control passes to irq_entry when OFW does 436 * its return from interrupt. There are 4 437 * fields in that frame that we need to plug: 438 * 439 * pc // gets irq_entry 440 * lr // gets lr_svc 441 * sp // gets sp_svc 442 * spsr // gets (I32_bit | PSR_SVC32_MODE) 443 * 444 */ 445 mov r1, #(I32_bit | PSR_SVC32_MODE) 446 str r1, [r0, #0] /* plug spsr */ 447 448 /* Sneak into SVC mode to get sp and lr */ 449 mrs r3, cpsr 450 bic r3, r3, #(PSR_MODE) 451 orr r3, r3, #(PSR_SVC32_MODE) 452 msr cpsr_all, r3 453 mov r4, lr /* snarf lr_svc */ 454 mov r5, sp /* snarf sp_svc */ 455 bic r3, r3, #(PSR_MODE) 456 orr r3, r3, #(PSR_IRQ32_MODE) 457 msr cpsr_all, r3 458 str r5, [r0, #(4*14)] /* plug sp */ 459 str r4, [r0, #(4*15)] /* plug lr */ 460 461 ldr r1, Lirq_entry 462 str r1, [r0, #(4*16)] /* plug pc */ 463 464 ldmfd sp!, {r1-r5} 465 mov pc, lr 466 467 468 .bss 469 .align 0 470 471_C_LABEL(ofw_ticktmp): 472 .space 4 * 6 /* temporary storage for 6 words of machine state */ 473 474ofwirqstk: /* hack */ 475 .space 4096 476