1 /* $NetBSD: imx6_reg.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_NXP_IMX6_REG_H_ 33 #define _ARM_NXP_IMX6_REG_H_ 34 35 #define IMX6_IOREG_PBASE IMX6_AIPS1_BASE 36 #define IMX6_IOREG_SIZE (IMX6_AIPS1_SIZE + IMX6_AIPS2_SIZE) 37 38 #define IMX6_ARMCORE_PBASE IMX6_MPCORE_BASE 39 #define IMX6_ARMCORE_SIZE IMX6_MPCORE_SIZE 40 41 #define IMX6_IO_SIZE (IMX6_IOREG_SIZE + IMX6_ARMCORE_SIZE) 42 43 #define ARMCORE_SCU_BASE 0x00000000 44 #define ARMCORE_L2C_BASE 0x00002000 45 46 #define IMX6_MEM_BASE 0x10000000 47 #define IMX6_MEM_SIZE 0xF0000000 48 49 #define IMX6_CS0_BASE 0x08000000 50 #define IMX6_CS0_SIZE 0x08000000 51 52 #define IMX6_IPU2_BASE 0x02a00000 53 #define IMX6_IPU1_BASE 0x02600000 54 #define IMX6_IPU_SIZE 0x00400000 55 56 #define IMX6_HSI_BASE 0x02208000 57 #define IMX6_HSI_SIZE 0x00004000 58 59 #define IMX6_OPENVG_BASE 0x02204000 60 #define IMX6_OPENVG_SIZE 0x00004000 61 62 #define IMX6_SATA_BASE 0x02200000 63 #define IMX6_SATA_SIZE 0x00004000 64 65 #define IMX6_AIPS2_BASE 0x02100000 66 #define IMX6_AIPS2_SIZE 0x00100000 67 68 #define IMX6_AIPS1_BASE 0x02000000 69 #define IMX6_AIPS1_SIZE 0x00100000 70 71 #define IMX6_PCIE_BASE 0x01ffc000 72 #define IMX6_PCIE_SIZE 0x00004000 73 74 #define IMX6_PCIEMEM_BASE 0x01000000 75 #define IMX6_PCIEMEM_SIZE 0x00ffc000 76 77 #define IMX6_GPV1_BASE 0x00c00000 78 #define IMX6_GPV1_SIZE 0x00100000 79 80 #define IMX6_GPV0_BASE 0x00b00000 81 #define IMX6_GPV0_SIZE 0x00100000 82 83 #define IMX6_L2CC_BASE 0x00a02000 84 #define IMX6_L2CC_SIZE 0x00001000 85 86 #define IMX6_MPCORE_BASE 0x00a00000 87 #define IMX6_MPCORE_SIZE 0x00100000 88 89 #define IMX6_OCRAM1_BASE 0x00940000 90 #define IMX6_OCRAM1_SIZE 0x000c0000 91 92 #define IMX6_OCRAM0_BASE 0x00900000 93 #define IMX6_OCRAM0_SIZE 0x00040000 94 95 #define IMX6_GPV4_BASE 0x00800000 96 #define IMX6_GPV4_SIZE 0x00100000 97 98 #define IMX6_GPV3_BASE 0x00300000 99 #define IMX6_GPV3_SIZE 0x00100000 100 101 #define IMX6_GPV2_BASE 0x00200000 102 #define IMX6_GPV2_SIZE 0x00100000 103 104 #define IMX6_DTPC_BASE 0x00138000 105 #define IMX6_DTPC_SIZE 0x00004000 106 107 #define IMX6_GPU2D_BASE 0x00134000 108 #define IMX6_GPU2D_SIZE 0x00004000 109 110 #define IMX6_GPU3D_BASE 0x00130000 111 #define IMX6_GPU3D_SIZE 0x00004000 112 113 #define IMX6_HDMI_BASE 0x00120000 114 #define IMX6_HDMI_SIZE 0x00009000 115 116 #define IMX6_APBHDMA_BASE 0x00110000 117 #define IMX6_APBHDMA_SIZE 0x00002000 118 119 #define IMX6_GPMI_BASE 0x00112000 120 #define IMX6_GPMI_SIZE 0x00002000 121 122 #define IMX6_BCH_BASE 0x00114000 123 #define IMX6_BCH_SIZE 0x00004000 124 125 #define IMX6_CAAM_BASE 0x00100000 126 #define IMX6_CAAM_SIZE 0x00004000 127 128 #define IMX6_ROMCP_BASE 0x00000000 129 #define IMX6_ROMCP_SIZE 0x00018000 130 131 #define AIPS1_SDMA_BASE 0x000ec000 132 #define AIPS1_DCIC2_BASE 0x000e8000 133 #define AIPS1_DCIC1_BASE 0x000e4000 134 #define AIPS1_IOMUXC_BASE 0x000e0000 135 #define AIPS1_IOMUXC_SIZE 0x00004000 136 #define AIPS1_GPC_BASE 0x000dc000 137 #define AIPS1_SRC_BASE 0x000d8000 138 #define AIPS1_SRC_SIZE 0x00004000 139 #define AIPS1_EPIT2_BASE 0x000d4000 140 #define AIPS1_EPIT1_BASE 0x000d0000 141 #define AIPS1_EPIT_SIZE 0x00000020 142 #define AIPS1_SNVS_BASE 0x000cc000 143 #define AIPS1_SNVS_SIZE 0x00000c00 144 #define AIPS1_USBPHY2_BASE 0x000ca000 145 #define AIPS1_USBPHY1_BASE 0x000c9000 146 #define AIPS1_USBPHY_SIZE 0x00001000 147 148 #define AIPS1_CCM_BASE 0x000c4000 149 #define AIPS1_CCM_SIZE 0x00004000 150 151 #define AIPS1_WDOG2_BASE 0x000c0000 152 #define AIPS1_WDOG1_BASE 0x000bc000 153 #define AIPS1_WDOG_SIZE 0x00000010 154 #define AIPS1_KPP_BASE 0x000b8000 155 #define AIPS1_ENET2_BASE 0x000b4000 /* iMX6UL */ 156 #define AIPS1_GPIO7_BASE 0x000b4000 157 #define AIPS1_GPIO6_BASE 0x000b0000 158 #define AIPS1_GPIO5_BASE 0x000ac000 159 #define AIPS1_GPIO4_BASE 0x000a8000 160 #define AIPS1_GPIO3_BASE 0x000a4000 161 #define AIPS1_GPIO2_BASE 0x000a0000 162 #define AIPS1_GPIO1_BASE 0x0009c000 163 #define GPIO_NGROUPS 7 164 #define AIPS1_GPT_BASE 0x00098000 165 #define AIPS1_CAN2_BASE 0x00094000 166 #define AIPS1_CAN1_BASE 0x00090000 167 #define AIPS1_PWM4_BASE 0x0008c000 168 #define AIPS1_PWM3_BASE 0x00088000 169 #define AIPS1_PWM2_BASE 0x00084000 170 #define AIPS1_PWM1_BASE 0x00080000 171 #define AIPS1_CONFIG_BASE 0x0007c000 172 #define AIPS1_VPU_BASE 0x00040000 173 #define AIPS1_SPBA_BASE 0x0003c000 174 #define AIPS1_ASRC_BASE 0x00034000 175 #define AIPS1_SSI3_BASE 0x00030000 176 #define AIPS1_SSI2_BASE 0x0002c000 177 #define AIPS1_SSI1_BASE 0x00028000 178 #define AIPS1_ESAI_BASE 0x00024000 179 #define AIPS1_UART1_BASE 0x00020000 180 #define AIPS1_UART7_BASE 0x00018000 /* iMX6UL */ 181 #define AIPS1_ECSPI5_BASE 0x00018000 182 #define AIPS1_ECSPI4_BASE 0x00014000 183 #define AIPS1_ECSPI3_BASE 0x00010000 184 #define AIPS1_ECSPI2_BASE 0x0000c000 185 #define AIPS1_ECSPI1_BASE 0x00008000 186 #define AIPS1_SPDIF_BASE 0x00004000 187 188 #define AIPS2_UART6_BASE 0x000fc000 /* iMX6UL */ 189 #define AIPS2_UART5_BASE 0x000f4000 190 #define AIPS2_UART4_BASE 0x000f0000 191 #define AIPS2_UART3_BASE 0x000ec000 192 #define AIPS2_UART2_BASE 0x000e8000 193 #define AIPS2_WDOG3_BASE 0x000e4000 /* iMX6UL */ 194 #define AIPS2_VDOA_BASE 0x000e3000 195 #define AIPS2_MIPIDSI_BASE 0x000e0000 196 #define AIPS2_MIPICSI_BASE 0x000dc000 197 #define AIPS2_AUDMUX_BASE 0x000d8000 198 #define AIPS2_TZASC2_BASE 0x000d4000 199 #define AIPS2_TZASC1_BASE 0x000d0000 200 #define AIPS2_CSU_BASE 0x000c0000 201 #define AIPS2_OCOTP_CTRL_BASE 0x000bc000 202 #define AIPS2_OCOTP_CTRL_SIZE 0x00000700 203 #define AIPS2_WEIM_BASE 0x000b8000 204 #define AIPS2_MMDC2_BASE 0x000b4000 205 #define AIPS2_MMDC1_BASE 0x000b0000 206 #define AIPS2_ROMCP_BASE 0x000ac000 207 208 #define AIPS2_I2C3_BASE 0x000a8000 209 #define AIPS2_I2C2_BASE 0x000a4000 210 #define AIPS2_I2C1_BASE 0x000a0000 211 #define I2C_SIZE 0x4000 212 213 #define AIPS2_USDHC4_BASE 0x0009c000 214 #define AIPS2_USDHC3_BASE 0x00098000 215 #define AIPS2_USDHC2_BASE 0x00094000 216 #define AIPS2_USDHC1_BASE 0x00090000 217 #define AIPS2_USDHC_SIZE 0x000000d0 218 #define AIPS2_MLB150_BASE 0x0008c000 219 #define AIPS2_ENET_BASE 0x00088000 220 #define AIPS2_USBOH_BASE 0x00084000 221 #define AIPS2_USBOH_SIZE 0x00000800 222 #define AIPS2_CONFIG_BASE 0x0007c000 223 #define AIPS2_DAP_BASE 0x00040000 224 #define AIPS2_CAAM_BASE 0x00000000 225 226 #endif /* _ARM_NXP_IMX6_REG_H_ */ 227