1 /* $NetBSD: imx6_platform.c,v 1.8 2023/05/04 13:28:04 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.8 2023/05/04 13:28:04 bouyer Exp $"); 31 32 #include "arml2cc.h" 33 #include "opt_console.h" 34 #include "opt_fdt.h" 35 #include "opt_multiprocessor.h" 36 #include "opt_soc.h" 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/fdt/arm_fdtvar.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <arm/arm32/machdep.h> 51 52 #include <machine/bootconfig.h> 53 #include <arm/cpufunc.h> 54 55 #include <arm/cortex/a9tmr_var.h> 56 #include <arm/cortex/scu_reg.h> 57 #include <arm/cortex/gic_reg.h> 58 #include <arm/cortex/pl310_var.h> 59 60 #include <arm/nxp/imx6_reg.h> 61 #include <arm/nxp/imx6_srcreg.h> 62 #include <arm/imx/imxuartreg.h> 63 #include <arm/imx/imxwdogreg.h> 64 65 #include <arm/nxp/imx6_platform.h> 66 67 #include <libfdt.h> 68 69 #define IMX_REF_FREQ 80000000 70 #define IMX6SX_REF_FREQ 24000000 71 72 #ifdef VERBOSE_INIT_ARM 73 #define VPRINTF(...) printf(__VA_ARGS__) 74 #else 75 #define VPRINTF(...) __nothing 76 #endif 77 78 extern struct bus_space armv7_generic_bs_tag; 79 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 80 81 static const struct pmap_devmap * 82 imx_platform_devmap(void) 83 { 84 static const struct pmap_devmap devmap[] = { 85 DEVMAP_ENTRY(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE, IMX6_IOREG_SIZE), 86 DEVMAP_ENTRY(KERNEL_IO_ARMCORE_VBASE, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE), 87 DEVMAP_ENTRY_END 88 }; 89 90 return devmap; 91 } 92 93 static const struct pmap_devmap * 94 imx6sx_platform_devmap(void) 95 { 96 static const struct pmap_devmap devmap[] = { 97 DEVMAP_ENTRY(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE, IMX6SX_IOREG_SIZE), 98 DEVMAP_ENTRY(KERNEL_IO_ARMCORE_VBASE, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE), 99 DEVMAP_ENTRY_END 100 }; 101 102 return devmap; 103 } 104 105 static void 106 imx_platform_init_attach_args(struct fdt_attach_args *faa) 107 { 108 faa->faa_bst = &armv7_generic_bs_tag; 109 faa->faa_dmat = &arm_generic_dma_tag; 110 } 111 112 void imx_platform_early_putchar(char); 113 114 void __noasan 115 imx_platform_early_putchar(char c) 116 { 117 #ifdef CONSADDR 118 #define CONSADDR_VA ((CONSADDR - IMX6_IOREG_PBASE) + KERNEL_IO_IOREG_VBASE) 119 120 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 121 (volatile uint32_t *)CONSADDR_VA : 122 (volatile uint32_t *)CONSADDR; 123 124 while ((le32toh(uartaddr[(IMX_USR2/4)]) & IMX_USR2_TXDC) == 0) 125 ; 126 127 uartaddr[(IMX_UTXD/4)] = htole32(c); 128 #endif 129 } 130 131 static void 132 imx_platform_device_register(device_t self, void *aux) 133 { 134 prop_dictionary_t prop = device_properties(self); 135 136 if (device_is_a(self, "atphy")) { 137 static const struct device_compatible_entry compat_data[] = { 138 { .compat = "fsl,imx6dl-sabresd" }, 139 { .compat = "fsl,imx6q-sabresd" }, 140 { .compat = "fsl,imx6qp-sabresd" }, 141 { .compat = "solidrun,hummingboard2/q" }, 142 { .compat = "solidrun,hummingboard2/dl" }, 143 DEVICE_COMPAT_EOL 144 }; 145 if (of_compatible_match(OF_finddevice("/"), compat_data)) 146 prop_dictionary_set_uint32(prop, "clk_25m", 125000000); 147 } 148 } 149 150 static u_int 151 imx_platform_uart_freq(void) 152 { 153 return IMX_REF_FREQ; 154 } 155 156 static u_int 157 imx6sx_platform_uart_freq(void) 158 { 159 return IMX6SX_REF_FREQ; 160 } 161 162 163 static void 164 imx_platform_bootstrap(void) 165 { 166 #if NARML2CC > 0 167 bus_space_tag_t bst = &armv7_generic_bs_tag; 168 bus_space_handle_t bsh; 169 if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh)) 170 panic("couldn't map armcore registers"); 171 arml2cc_init(bst, bsh, ARMCORE_L2C_BASE); 172 bus_space_unmap(bst, bsh, IMX6_ARMCORE_SIZE); 173 #endif 174 175 arm_fdt_cpu_bootstrap(); 176 } 177 178 static int 179 imx_platform_mpstart(void) 180 { 181 #if defined(MULTIPROCESSOR) 182 bus_space_tag_t bst = &armv7_generic_bs_tag; 183 bus_space_handle_t bsh; 184 185 if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh) != 0) 186 panic("couldn't map armcore registers"); 187 188 /* Enable Snoop Control Unit */ 189 bus_space_write_4(bst, bsh, SCU_INV_ALL_REG, 0xff); 190 bus_space_write_4(bst, bsh, SCU_CTL, 191 bus_space_read_4(bst, bsh, SCU_CTL) | SCU_CTL_SCU_ENA); 192 193 bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE); 194 195 if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_SRC_BASE, AIPS1_SRC_SIZE, 0, &bsh) != 0) 196 panic("couldn't map SRC"); 197 198 uint32_t srcctl = bus_space_read_4(bst, bsh, SRC_SCR); 199 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 200 201 srcctl &= ~(SRC_SCR_CORE1_ENABLE | SRC_SCR_CORE2_ENABLE | 202 SRC_SCR_CORE3_ENABLE); 203 bus_space_write_4(bst, bsh, SRC_SCR, srcctl); 204 205 for (int i = 1; i < arm_cpu_max; i++) { 206 bus_space_write_4(bst, bsh, SRC_GPRN_ENTRY(i), mpstart); 207 srcctl |= SRC_SCR_COREN_RST(i); 208 srcctl |= SRC_SCR_COREN_ENABLE(i); 209 } 210 bus_space_write_4(bst, bsh, SRC_SCR, srcctl); 211 212 bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE); 213 214 return arm_fdt_cpu_mpstart(); 215 #else 216 return 0; 217 #endif 218 } 219 220 static void 221 imx6_platform_reset(void) 222 { 223 bus_space_tag_t bst = &armv7_generic_bs_tag; 224 bus_space_handle_t bsh; 225 226 if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE, AIPS1_WDOG_SIZE, 0, &bsh)) 227 panic("couldn't map wdog1 registers"); 228 229 delay(1000); /* wait for flushing FIFO of serial console */ 230 231 cpsid(I32_bit|F32_bit); 232 233 /* software reset signal on wdog */ 234 bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE); 235 236 /* 237 * write twice due to errata. 238 * Reference: ERR004346: IMX6DQCE Chip Errata for the i.MX 6Dual/6Quad 239 */ 240 bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE); 241 242 for (;;) 243 __asm("wfi"); 244 } 245 246 static const struct fdt_platform imx6_platform = { 247 .fp_devmap = imx_platform_devmap, 248 .fp_bootstrap = imx_platform_bootstrap, 249 .fp_init_attach_args = imx_platform_init_attach_args, 250 .fp_device_register = imx_platform_device_register, 251 .fp_reset = imx6_platform_reset, 252 .fp_delay = a9ptmr_delay, 253 .fp_uart_freq = imx_platform_uart_freq, 254 .fp_mpstart = imx_platform_mpstart, 255 }; 256 257 static const struct fdt_platform imx6sx_platform = { 258 .fp_devmap = imx6sx_platform_devmap, 259 .fp_bootstrap = imx_platform_bootstrap, 260 .fp_init_attach_args = imx_platform_init_attach_args, 261 .fp_device_register = imx_platform_device_register, 262 .fp_reset = imx6_platform_reset, 263 .fp_delay = a9ptmr_delay, 264 .fp_uart_freq = imx6sx_platform_uart_freq, 265 .fp_mpstart = imx_platform_mpstart, 266 }; 267 268 FDT_PLATFORM(imx6dl, "fsl,imx6dl", &imx6_platform); 269 FDT_PLATFORM(imx6sx, "fsl,imx6sx", &imx6sx_platform); 270 FDT_PLATFORM(imx6q, "fsl,imx6q", &imx6_platform); 271 FDT_PLATFORM(imx6qp, "fsl,imx6qp", &imx6_platform); 272