1 /* $NetBSD: imx6_clk.c,v 1.3 2021/01/30 09:36:46 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_clk.c,v 1.3 2021/01/30 09:36:46 skrll Exp $"); 31 32 #include "opt_fdt.h" 33 34 #include <sys/types.h> 35 #include <sys/time.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/sysctl.h> 39 #include <sys/cpufreq.h> 40 #include <sys/malloc.h> 41 #include <sys/kmem.h> 42 #include <sys/param.h> 43 44 #include <arm/nxp/imx6_ccmvar.h> 45 46 #include <dev/clk/clk_backend.h> 47 #include <dev/fdt/fdtvar.h> 48 49 static struct clk *imx6_clk_decode(device_t, int, const void *, size_t); 50 51 static const struct fdtbus_clock_controller_func imx6_ccm_fdtclock_funcs = { 52 .decode = imx6_clk_decode 53 }; 54 55 static struct clk * 56 imx6_clk_decode(device_t dev, int cc_phandle, const void *data, size_t len) 57 { 58 struct clk *clk; 59 60 /* #clock-cells should be 1 */ 61 if (len != 4) 62 return NULL; 63 64 const u_int clock_id = be32dec(data); 65 66 clk = imx6_get_clock_by_id(clock_id); 67 if (clk) 68 return clk; 69 70 return NULL; 71 } 72 73 static void 74 imx6_clk_fixed_from_fdt(const char *name) 75 { 76 struct imx6_clk *iclk = (struct imx6_clk *)imx6_get_clock(name); 77 78 KASSERT(iclk != NULL); 79 80 char *path = kmem_asprintf("/clocks/%s", name); 81 int phandle = OF_finddevice(path); 82 kmem_free(path, strlen(path) + 1); 83 84 if (of_getprop_uint32(phandle, "clock-frequency", &iclk->clk.fixed.rate) != 0) 85 iclk->clk.fixed.rate = 0; 86 } 87 88 static int imx6ccm_match(device_t, cfdata_t, void *); 89 static void imx6ccm_attach(device_t, device_t, void *); 90 91 CFATTACH_DECL_NEW(imx6ccm, sizeof(struct imx6ccm_softc), 92 imx6ccm_match, imx6ccm_attach, NULL, NULL); 93 94 static const struct device_compatible_entry compat_data[] = { 95 { .compat = "fsl,imx6q-ccm" }, 96 DEVICE_COMPAT_EOL 97 }; 98 99 static int 100 imx6ccm_match(device_t parent, cfdata_t cfdata, void *aux) 101 { 102 struct fdt_attach_args * const faa = aux; 103 104 return of_compatible_match(faa->faa_phandle, compat_data); 105 } 106 107 static void 108 imx6ccm_attach(device_t parent, device_t self, void *aux) 109 { 110 struct imx6ccm_softc * const sc = device_private(self); 111 struct fdt_attach_args * const faa = aux; 112 bus_addr_t addr; 113 bus_size_t size; 114 115 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 116 aprint_error(": couldn't get registers\n"); 117 return; 118 } 119 120 sc->sc_dev = self; 121 sc->sc_iot = faa->faa_bst; 122 123 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 124 aprint_error(": can't map ccm registers\n"); 125 return; 126 } 127 128 int phandle = OF_finddevice("/soc/aips-bus/anatop"); 129 fdtbus_get_reg(phandle, 0, &addr, &size); 130 131 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh_analog)) { 132 aprint_error(": can't map anatop registers\n"); 133 return; 134 } 135 136 aprint_naive("\n"); 137 aprint_normal(": Clock Control Module\n"); 138 139 imx6ccm_attach_common(self); 140 141 imx6_clk_fixed_from_fdt("ckil"); 142 imx6_clk_fixed_from_fdt("ckih"); 143 imx6_clk_fixed_from_fdt("osc"); 144 imx6_clk_fixed_from_fdt("anaclk1"); 145 imx6_clk_fixed_from_fdt("anaclk2"); 146 147 fdtbus_register_clock_controller(self, faa->faa_phandle, 148 &imx6_ccm_fdtclock_funcs); 149 } 150 151