1 /* $NetBSD: imx6_clk.c,v 1.4 2022/09/27 06:36:42 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_clk.c,v 1.4 2022/09/27 06:36:42 skrll Exp $"); 31 32 #include "opt_fdt.h" 33 34 #include <sys/types.h> 35 #include <sys/time.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/sysctl.h> 39 #include <sys/cpufreq.h> 40 #include <sys/kmem.h> 41 #include <sys/param.h> 42 43 #include <arm/nxp/imx6_ccmvar.h> 44 45 #include <dev/clk/clk_backend.h> 46 #include <dev/fdt/fdtvar.h> 47 48 static struct clk *imx6_clk_decode(device_t, int, const void *, size_t); 49 50 static const struct fdtbus_clock_controller_func imx6_ccm_fdtclock_funcs = { 51 .decode = imx6_clk_decode 52 }; 53 54 static struct clk * 55 imx6_clk_decode(device_t dev, int cc_phandle, const void *data, size_t len) 56 { 57 struct clk *clk; 58 59 /* #clock-cells should be 1 */ 60 if (len != 4) 61 return NULL; 62 63 const u_int clock_id = be32dec(data); 64 65 clk = imx6_get_clock_by_id(clock_id); 66 if (clk) 67 return clk; 68 69 return NULL; 70 } 71 72 static void 73 imx6_clk_fixed_from_fdt(const char *name) 74 { 75 struct imx6_clk *iclk = (struct imx6_clk *)imx6_get_clock(name); 76 77 KASSERT(iclk != NULL); 78 79 char *path = kmem_asprintf("/clocks/%s", name); 80 int phandle = OF_finddevice(path); 81 kmem_free(path, strlen(path) + 1); 82 83 if (of_getprop_uint32(phandle, "clock-frequency", &iclk->clk.fixed.rate) != 0) 84 iclk->clk.fixed.rate = 0; 85 } 86 87 static int imx6ccm_match(device_t, cfdata_t, void *); 88 static void imx6ccm_attach(device_t, device_t, void *); 89 90 CFATTACH_DECL_NEW(imx6ccm, sizeof(struct imx6ccm_softc), 91 imx6ccm_match, imx6ccm_attach, NULL, NULL); 92 93 static const struct device_compatible_entry compat_data[] = { 94 { .compat = "fsl,imx6q-ccm" }, 95 DEVICE_COMPAT_EOL 96 }; 97 98 static int 99 imx6ccm_match(device_t parent, cfdata_t cfdata, void *aux) 100 { 101 struct fdt_attach_args * const faa = aux; 102 103 return of_compatible_match(faa->faa_phandle, compat_data); 104 } 105 106 static void 107 imx6ccm_attach(device_t parent, device_t self, void *aux) 108 { 109 struct imx6ccm_softc * const sc = device_private(self); 110 struct fdt_attach_args * const faa = aux; 111 bus_addr_t addr; 112 bus_size_t size; 113 114 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 115 aprint_error(": couldn't get registers\n"); 116 return; 117 } 118 119 sc->sc_dev = self; 120 sc->sc_iot = faa->faa_bst; 121 122 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 123 aprint_error(": can't map ccm registers\n"); 124 return; 125 } 126 127 int phandle = OF_finddevice("/soc/aips-bus/anatop"); 128 fdtbus_get_reg(phandle, 0, &addr, &size); 129 130 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh_analog)) { 131 aprint_error(": can't map anatop registers\n"); 132 return; 133 } 134 135 aprint_naive("\n"); 136 aprint_normal(": Clock Control Module\n"); 137 138 imx6ccm_attach_common(self); 139 140 imx6_clk_fixed_from_fdt("ckil"); 141 imx6_clk_fixed_from_fdt("ckih"); 142 imx6_clk_fixed_from_fdt("osc"); 143 imx6_clk_fixed_from_fdt("anaclk1"); 144 imx6_clk_fixed_from_fdt("anaclk2"); 145 146 fdtbus_register_clock_controller(self, faa->faa_phandle, 147 &imx6_ccm_fdtclock_funcs); 148 } 149 150