1 /* $NetBSD: tegra_xusb.c,v 1.17 2019/01/08 18:04:00 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.17 2019/01/08 18:04:00 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_size[]; 78 extern const char _binary_tegra124_xusb_bin_start[]; 79 #endif 80 81 #ifdef TEGRA210_XUSB_BIN_STATIC 82 extern const char _binary_tegra210_xusb_bin_size[]; 83 extern const char _binary_tegra210_xusb_bin_start[]; 84 #endif 85 86 enum xusb_type { 87 XUSB_T124 = 1, 88 XUSB_T210 89 }; 90 91 struct tegra_xhci_data { 92 enum xusb_type txd_type; 93 const char * const * txd_supplies; 94 size_t txd_nsupplies; 95 bool txd_scale_ss_clock; 96 }; 97 98 const char *tegra124_xhci_supplies[] = { 99 "dvddio-pex-supply", 100 "hvddio-pex-supply", 101 "avdd-usb-supply", 102 "avdd-pll-utmip-supply", 103 "avdd-pll-uerefe-supply", 104 "dvdd-usb-ss-pll-supply", 105 "hvdd-usb-ss-pll-e-supply" 106 }; 107 108 struct tegra_xhci_data tegra124_xhci_data = { 109 .txd_type = XUSB_T124, 110 .txd_supplies = tegra124_xhci_supplies, 111 .txd_nsupplies = __arraycount(tegra124_xhci_supplies), 112 .txd_scale_ss_clock = true, 113 }; 114 115 const char *tegra210_xhci_supplies[] = { 116 "dvddio-pex", 117 "hvddio-pex", 118 "avdd-usb", 119 "avdd-pll-utmip", 120 "avdd-pll-uerefe", 121 "dvdd-pex-pll", 122 "hvdd-pex-pll-e", 123 }; 124 125 struct tegra_xhci_data tegra210_xhci_data = { 126 .txd_type = XUSB_T210, 127 .txd_supplies = tegra210_xhci_supplies, 128 .txd_nsupplies = __arraycount(tegra210_xhci_supplies), 129 .txd_scale_ss_clock = false, 130 }; 131 132 static const struct of_compat_data compat_data[] = { 133 { "nvidia,tegra124-xusb", (uintptr_t)&tegra124_xhci_data }, 134 { "nvidia,tegra210-xusb", (uintptr_t)&tegra210_xhci_data }, 135 { NULL } 136 }; 137 138 struct fw_dma { 139 bus_dmamap_t map; 140 void * addr; 141 bus_dma_segment_t segs[1]; 142 int nsegs; 143 size_t size; 144 }; 145 146 struct tegra_xusb_softc { 147 struct xhci_softc sc_xhci; 148 int sc_phandle; 149 bus_space_handle_t sc_bsh_xhci; 150 bus_space_handle_t sc_bsh_fpci; 151 bus_space_handle_t sc_bsh_ipfs; 152 void *sc_ih; 153 void *sc_ih_mbox; 154 struct fw_dma sc_fw_dma; 155 struct clk *sc_clk_ss_src; 156 157 struct tegra_xhci_data *sc_txd; 158 }; 159 160 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 161 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 162 uint32_t); 163 164 static void tegra_xusb_init(struct tegra_xusb_softc * const); 165 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 166 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 167 size_t); 168 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 169 170 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 171 172 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 173 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 174 175 static int 176 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 177 { 178 struct fdt_attach_args * const faa = aux; 179 180 return of_match_compat_data(faa->faa_phandle, compat_data); 181 } 182 183 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 184 do { \ 185 if (cond) { \ 186 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 187 return; \ 188 } \ 189 } while (0) 190 191 static void 192 tegra_xusb_attach(device_t parent, device_t self, void *aux) 193 { 194 struct tegra_xusb_softc * const psc = device_private(self); 195 struct xhci_softc * const sc = &psc->sc_xhci; 196 struct fdt_attach_args * const faa = aux; 197 bool wait_for_root = true; 198 char intrstr[128]; 199 bus_addr_t addr; 200 bus_size_t size; 201 struct fdtbus_reset *rst; 202 struct fdtbus_phy *phy; 203 struct clk *clk; 204 uint32_t rate; 205 int error, n; 206 207 aprint_naive("\n"); 208 aprint_normal(": XUSB\n"); 209 210 sc->sc_dev = self; 211 sc->sc_iot = faa->faa_bst; 212 sc->sc_bus.ub_hcpriv = sc; 213 sc->sc_bus.ub_dmatag = faa->faa_dmat; 214 sc->sc_quirks = XHCI_DEFERRED_START; 215 psc->sc_phandle = faa->faa_phandle; 216 217 uintptr_t data = of_search_compatible(faa->faa_phandle, compat_data)->data; 218 psc->sc_txd = (struct tegra_xhci_data *)data; 219 220 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 221 aprint_error(": couldn't get registers\n"); 222 return; 223 } 224 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 225 if (error) { 226 aprint_error(": couldn't map %#" PRIx64 ": %d", 227 (uint64_t)addr, error); 228 return; 229 } 230 DPRINTF(sc->sc_dev, "mapped %#" PRIx64 "\n", (uint64_t)addr); 231 232 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 233 aprint_error(": couldn't get registers\n"); 234 return; 235 } 236 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 237 if (error) { 238 aprint_error(": couldn't map %#" PRIx64 ": %d", 239 (uint64_t)addr, error); 240 return; 241 } 242 DPRINTF(sc->sc_dev, "mapped %#" PRIx64 "\n", (uint64_t)addr); 243 244 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 245 aprint_error(": couldn't get registers\n"); 246 return; 247 } 248 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 249 if (error) { 250 aprint_error(": couldn't map %#" PRIx64 ": %d", 251 (uint64_t)addr, error); 252 return; 253 } 254 DPRINTF(sc->sc_dev, "mapped %#" PRIx64 "\n", (uint64_t)addr); 255 256 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 257 aprint_error_dev(self, "failed to decode interrupt\n"); 258 return; 259 } 260 261 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 262 FDT_INTR_MPSAFE, xhci_intr, sc); 263 if (psc->sc_ih == NULL) { 264 aprint_error_dev(self, "failed to establish interrupt on %s\n", 265 intrstr); 266 return; 267 } 268 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 269 270 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 271 aprint_error_dev(self, "failed to decode interrupt\n"); 272 return; 273 } 274 275 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 276 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 277 if (psc->sc_ih_mbox == NULL) { 278 aprint_error_dev(self, "failed to establish interrupt on %s\n", 279 intrstr); 280 return; 281 } 282 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 283 284 /* Enable PHYs */ 285 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 286 if (fdtbus_phy_enable(phy, true) != 0) 287 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 288 289 /* Enable XUSB power rails */ 290 291 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 292 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 293 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 294 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 295 296 /* Enable XUSB clocks */ 297 298 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 299 rate = clk_get_rate(clk); 300 error = clk_enable(clk); /* XXX set frequency */ 301 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 302 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 303 304 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 305 rate = clk_get_rate(clk); 306 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 307 error = clk_set_rate(clk, 102000000); 308 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 309 310 rate = clk_get_rate(clk); 311 error = clk_enable(clk); /* XXX set frequency */ 312 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 313 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 314 315 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 316 rate = clk_get_rate(clk); 317 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 318 error = clk_set_rate(clk, 204000000); 319 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 320 321 rate = clk_get_rate(clk); 322 error = clk_enable(clk); 323 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 324 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 325 326 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 327 rate = clk_get_rate(clk); 328 error = clk_enable(clk); /* XXX set frequency */ 329 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 330 331 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 332 rate = clk_get_rate(clk); 333 error = clk_enable(clk); /* XXX set frequency */ 334 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 335 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 336 337 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 338 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 339 "failed to get xusb_ss_src clock"); 340 341 if (psc->sc_txd->txd_scale_ss_clock) { 342 rate = clk_get_rate(psc->sc_clk_ss_src); 343 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 344 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 345 rate = clk_get_rate(psc->sc_clk_ss_src); 346 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 347 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 348 349 rate = clk_get_rate(psc->sc_clk_ss_src); 350 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 351 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 352 353 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 354 rate = clk_get_rate(psc->sc_clk_ss_src); 355 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 356 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 357 } 358 359 rate = clk_get_rate(psc->sc_clk_ss_src); 360 error = clk_enable(psc->sc_clk_ss_src); 361 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 362 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 363 364 #if 0 365 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 366 error = 0; 367 rate = clk_get_rate(clk); 368 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 369 #endif 370 371 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 372 rate = clk_get_rate(clk); 373 error = clk_enable(clk); /* XXX set frequency */ 374 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 375 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 376 377 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 378 fdtbus_reset_deassert(rst); 379 380 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 381 fdtbus_reset_deassert(rst); 382 383 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 384 fdtbus_reset_deassert(rst); 385 386 DELAY(1); 387 388 tegra_xusb_init_regulators(psc); 389 390 tegra_xusb_init(psc); 391 392 #if defined(TEGRA124_XUSB_BIN_STATIC) 393 if (psc->sc_txd->txd_type == XUSB_T124) 394 wait_for_root = false; 395 #endif 396 #if defined(TEGRA210_XUSB_BIN_STATIC) 397 if (psc->sc_txd->txd_type == XUSB_T210) 398 wait_for_root = false; 399 #endif 400 401 if (wait_for_root) 402 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 403 else 404 tegra_xusb_mountroot(sc->sc_dev); 405 } 406 407 static void 408 tegra_xusb_mountroot(device_t self) 409 { 410 struct tegra_xusb_softc * const psc = device_private(self); 411 struct xhci_softc * const sc = &psc->sc_xhci; 412 const bus_space_tag_t bst = sc->sc_iot; 413 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 414 struct clk *clk; 415 struct fdtbus_reset *rst; 416 uint32_t rate; 417 uint32_t val; 418 int error; 419 420 DPRINTF(sc->sc_dev, "%s()\n", __func__); 421 422 val = bus_space_read_4(bst, ipfsh, 0x0); 423 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 424 425 if (tegra_xusb_open_fw(psc) != 0) 426 return; 427 DPRINTF(sc->sc_dev, "post fw\n"); 428 429 tegra_xusbpad_xhci_enable(); 430 431 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 432 rate = clk_get_rate(clk); 433 error = clk_enable(clk); 434 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 435 436 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 437 rate = clk_get_rate(clk); 438 error = clk_enable(clk); 439 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 440 441 val = bus_space_read_4(bst, ipfsh, 0x0); 442 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 443 444 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 445 fdtbus_reset_deassert(rst); 446 447 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 448 fdtbus_reset_deassert(rst); 449 450 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 451 fdtbus_reset_deassert(rst); 452 453 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 454 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 455 456 val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV) 457 & PCI_USBREV_MASK; 458 switch (val) { 459 case PCI_USBREV_3_0: 460 sc->sc_bus.ub_revision = USBREV_3_0; 461 break; 462 case PCI_USBREV_3_1: 463 sc->sc_bus.ub_revision = USBREV_3_1; 464 break; 465 default: 466 if (val < PCI_USBREV_3_0) { 467 aprint_error_dev(self, "Unknown revision (%02x)\n", val); 468 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 469 } else { 470 /* Default to the latest revision */ 471 aprint_normal_dev(self, 472 "Unknown revision (%02x). Set to 3.1.\n", val); 473 sc->sc_bus.ub_revision = USBREV_3_1; 474 } 475 break; 476 } 477 478 error = xhci_init(sc); 479 if (error) { 480 aprint_error_dev(self, "init failed, error=%d\n", error); 481 return; 482 } 483 484 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 485 486 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 487 488 xhci_start(sc); 489 490 error = xusb_mailbox_send(psc, 0x01000000); 491 if (error) { 492 aprint_error_dev(self, "send failed, error=%d\n", error); 493 } 494 } 495 496 static int 497 tegra_xusb_intr_mbox(void *v) 498 { 499 struct tegra_xusb_softc * const psc = v; 500 struct xhci_softc * const sc = &psc->sc_xhci; 501 const bus_space_tag_t bst = sc->sc_iot; 502 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 503 uint32_t val; 504 uint32_t irv; 505 uint32_t msg; 506 int error; 507 508 DPRINTF(sc->sc_dev, "%s()\n", __func__); 509 510 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 511 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 512 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 513 514 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 515 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 516 517 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 518 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 519 520 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 521 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 522 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 523 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 524 525 bool sendresp = true; 526 u_int rate; 527 528 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 529 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 530 531 switch (type) { 532 case 2: 533 case 3: 534 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 535 break; 536 case 4: 537 case 5: 538 if (psc->sc_txd->txd_scale_ss_clock) { 539 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 540 rate = clk_get_rate(psc->sc_clk_ss_src); 541 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 542 rate); 543 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 544 if (error != 0) 545 goto clk_fail; 546 rate = clk_get_rate(psc->sc_clk_ss_src); 547 DPRINTF(sc->sc_dev, 548 "rate of psc->sc_clk_ss_src %u after\n", rate); 549 if (data == (rate / 1000)) { 550 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 551 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 552 } else 553 clk_fail: 554 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 555 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 556 } else { 557 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 558 __SHIFTIN(data, MAILBOX_DATA_DATA); 559 } 560 xusb_mailbox_send(psc, msg); 561 break; 562 case 9: 563 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 564 __SHIFTIN(128, MAILBOX_DATA_TYPE); 565 xusb_mailbox_send(psc, msg); 566 break; 567 case 6: 568 case 128: 569 case 129: 570 sendresp = false; 571 break; 572 default: 573 sendresp = false; 574 break; 575 } 576 577 if (sendresp == false) 578 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 579 MAILBOX_OWNER_NONE); 580 581 return irv; 582 } 583 584 static void 585 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 586 { 587 588 device_t dev = psc->sc_xhci.sc_dev; 589 const int phandle = psc->sc_phandle; 590 struct fdtbus_regulator *reg; 591 int n, error; 592 593 for (n = 0; n < psc->sc_txd->txd_nsupplies; n++) { 594 if (!of_hasprop(phandle, psc->sc_txd->txd_supplies[n])) 595 continue; 596 reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]); 597 if (reg == NULL) { 598 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 599 psc->sc_txd->txd_supplies[n]); 600 continue; 601 } 602 error = fdtbus_regulator_enable(reg); 603 if (error != 0) 604 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 605 psc->sc_txd->txd_supplies[n], error); 606 } 607 } 608 609 static void 610 tegra_xusb_init(struct tegra_xusb_softc * const psc) 611 { 612 struct xhci_softc * const sc = &psc->sc_xhci; 613 const bus_space_tag_t bst = sc->sc_iot; 614 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 615 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 616 617 DPRINTF(sc->sc_dev, "%s()\n", __func__); 618 619 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 620 bus_space_read_4(bst, ipfsh, 0x0)); 621 622 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 623 bus_space_read_4(bst, ipfsh, 0x40)); 624 625 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 626 bus_space_read_4(bst, ipfsh, 0x80)); 627 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 628 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 629 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 630 bus_space_read_4(bst, ipfsh, 0x80)); 631 632 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 633 bus_space_read_4(bst, ipfsh, 0x180)); 634 /* EN_FPCI */ 635 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 636 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 637 bus_space_read_4(bst, ipfsh, 0x180)); 638 639 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 640 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 641 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 642 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 643 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 644 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 645 646 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 647 bus_space_read_4(bst, fpcih, PCI_BAR0)); 648 /* match FPCI BAR0 to above */ 649 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 650 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 651 bus_space_read_4(bst, fpcih, PCI_BAR0)); 652 653 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 654 bus_space_read_4(bst, ipfsh, 0x188)); 655 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 656 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 657 bus_space_read_4(bst, ipfsh, 0x188)); 658 659 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 660 bus_space_read_4(bst, fpcih, 0x1bc)); 661 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 662 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 663 bus_space_read_4(bst, fpcih, 0x1bc)); 664 } 665 666 static int 667 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 668 struct fw_dma * const p) 669 { 670 struct xhci_softc * const sc = &psc->sc_xhci; 671 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 672 int err; 673 674 p->size = size; 675 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 676 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 677 if (err) 678 return err; 679 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 680 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 681 if (err) 682 goto free; 683 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 684 &p->map); 685 if (err) 686 goto unmap; 687 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 688 BUS_DMA_NOWAIT); 689 if (err) 690 goto destroy; 691 692 return 0; 693 694 destroy: 695 bus_dmamap_destroy(dmat, p->map); 696 unmap: 697 bus_dmamem_unmap(dmat, p->addr, p->size); 698 free: 699 bus_dmamem_free(dmat, p->segs, p->nsegs); 700 701 return err; 702 } 703 704 static void 705 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 706 { 707 const struct xhci_softc * const sc = &psc->sc_xhci; 708 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 709 710 bus_dmamap_unload(dmat, p->map); 711 bus_dmamap_destroy(dmat, p->map); 712 bus_dmamem_unmap(dmat, p->addr, p->size); 713 bus_dmamem_free(dmat, p->segs, p->nsegs); 714 } 715 716 #define FWHEADER_BOOT_CODETAG 8 717 #define FWHEADER_BOOT_CODESIZE 12 718 #define FWHEADER_FWIMG_LEN 100 719 #define FWHEADER__LEN 256 720 721 static int 722 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 723 { 724 struct xhci_softc * const sc = &psc->sc_xhci; 725 firmware_handle_t fw; 726 size_t firmware_size = 0; 727 void *firmware_image; 728 const char *fw_path = NULL; 729 void *fw_static = NULL; 730 int error; 731 732 switch (psc->sc_txd->txd_type) { 733 case XUSB_T124: 734 #if defined(TEGRA124_XUSB_BIN_STATIC) 735 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 736 fw_static = __UNCONST(_binary_tegra124_xusb_bin_start); 737 #else 738 fw_path = "nvidia/tegra124"; 739 #endif 740 break; 741 case XUSB_T210: 742 #if defined(TEGRA210_XUSB_BIN_STATIC) 743 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 744 fw_static = __UNCONST(_binary_tegra210_xusb_bin_start); 745 #else 746 fw_path = "nvidia/tegra210"; 747 #endif 748 break; 749 default: 750 return EINVAL; 751 } 752 753 if (fw_path != NULL) { 754 error = firmware_open(fw_path, "xusb.bin", &fw); 755 if (error != 0) { 756 aprint_error_dev(sc->sc_dev, 757 "couldn't load firmware from %s/xusb.bin: %d\n", 758 fw_path, error); 759 return error; 760 } 761 firmware_size = firmware_get_size(fw); 762 } 763 764 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 765 &psc->sc_fw_dma); 766 if (error != 0) 767 return error; 768 firmware_image = psc->sc_fw_dma.addr; 769 770 if (fw_path != NULL) { 771 error = firmware_read(fw, 0, firmware_image, firmware_size); 772 if (error != 0) { 773 fw_dma_free(psc, &psc->sc_fw_dma); 774 firmware_close(fw); 775 return error; 776 } 777 firmware_close(fw); 778 } else { 779 memcpy(firmware_image, fw_static, firmware_size); 780 } 781 782 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 783 } 784 785 static int 786 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 787 size_t firmware_size) 788 { 789 struct xhci_softc * const sc = &psc->sc_xhci; 790 const uint8_t *header; 791 792 header = firmware_image; 793 794 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 795 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 796 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 797 798 if (fwimg_len != firmware_size) 799 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 800 fwimg_len, firmware_size); 801 802 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 803 firmware_size, BUS_DMASYNC_PREWRITE); 804 805 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 806 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 807 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 808 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 809 810 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 811 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 812 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 813 fwimg_len); 814 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 815 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 816 817 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 818 FWHEADER__LEN; 819 820 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 821 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 822 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 823 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 824 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 825 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 826 827 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 828 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 829 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 830 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 831 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 832 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 833 834 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 835 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 836 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 837 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 838 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 839 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 840 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 841 842 const u_int code_tag_blocks = 843 howmany(boot_codetag, IMEM_BLOCK_SIZE); 844 const u_int code_size_blocks = 845 howmany(boot_codesize, IMEM_BLOCK_SIZE); 846 const u_int code_blocks = code_tag_blocks + code_size_blocks; 847 848 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 849 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 850 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 851 __SHIFTIN(code_tag_blocks, 852 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 853 __SHIFTIN(code_size_blocks, 854 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 855 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 856 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 857 858 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 859 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 860 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 861 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 862 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 863 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 864 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 865 866 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 867 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 868 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 869 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 870 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 871 872 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 873 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 874 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 875 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 876 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 877 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 878 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 879 880 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 881 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 882 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 883 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 884 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 885 886 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 887 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 888 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 889 boot_codetag); 890 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 891 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 892 893 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 894 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 895 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 896 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 897 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 898 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 899 900 return 0; 901 } 902 903 static uint32_t 904 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 905 { 906 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 907 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 908 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 909 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 910 911 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 912 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 913 } 914 915 static void 916 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 917 uint32_t value) 918 { 919 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 920 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 921 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 922 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 923 924 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 925 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 926 } 927 928 static int 929 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 930 { 931 struct xhci_softc * const sc = &psc->sc_xhci; 932 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 933 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 934 uint32_t val; 935 bool wait = false; 936 937 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 938 939 if (!(type == 128 || type == 129)) { 940 val = bus_space_read_4(bst, fpcih, 941 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 942 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 943 val); 944 if (val != MAILBOX_OWNER_NONE) { 945 return EBUSY; 946 } 947 948 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 949 MAILBOX_OWNER_SW); 950 951 val = bus_space_read_4(bst, fpcih, 952 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 953 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 954 val); 955 if (val != MAILBOX_OWNER_SW) { 956 return EBUSY; 957 } 958 959 wait = true; 960 } 961 962 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 963 964 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 965 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 966 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 967 968 if (wait) { 969 970 for (u_int i = 0; i < 2500; i++) { 971 val = bus_space_read_4(bst, fpcih, 972 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 973 DPRINTF(sc->sc_dev, 974 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 975 if (val == MAILBOX_OWNER_NONE) { 976 break; 977 } 978 DELAY(10); 979 } 980 981 val = bus_space_read_4(bst, fpcih, 982 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 983 DPRINTF(sc->sc_dev, 984 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 985 if (val != MAILBOX_OWNER_NONE) { 986 aprint_error_dev(sc->sc_dev, 987 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 988 } 989 } 990 991 return 0; 992 } 993