1 /* $NetBSD: tegra_xusb.c,v 1.15 2018/07/16 23:11:47 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.15 2018/07/16 23:11:47 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_size[]; 78 extern const char _binary_tegra124_xusb_bin_start[]; 79 #endif 80 81 #ifdef TEGRA210_XUSB_BIN_STATIC 82 extern const char _binary_tegra210_xusb_bin_size[]; 83 extern const char _binary_tegra210_xusb_bin_start[]; 84 #endif 85 86 enum xusb_type { 87 XUSB_T124 = 1, 88 XUSB_T210 89 }; 90 91 static const struct of_compat_data compat_data[] = { 92 { "nvidia,tegra124-xusb", XUSB_T124 }, 93 { "nvidia,tegra210-xusb", XUSB_T210 }, 94 { NULL } 95 }; 96 97 struct fw_dma { 98 bus_dmamap_t map; 99 void * addr; 100 bus_dma_segment_t segs[1]; 101 int nsegs; 102 size_t size; 103 }; 104 105 struct tegra_xusb_softc { 106 struct xhci_softc sc_xhci; 107 int sc_phandle; 108 bus_space_handle_t sc_bsh_xhci; 109 bus_space_handle_t sc_bsh_fpci; 110 bus_space_handle_t sc_bsh_ipfs; 111 void *sc_ih; 112 void *sc_ih_mbox; 113 struct fw_dma sc_fw_dma; 114 struct clk *sc_clk_ss_src; 115 enum xusb_type sc_type; 116 117 bool sc_scale_ss_clock; 118 }; 119 120 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 121 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 122 uint32_t); 123 124 static void tegra_xusb_init(struct tegra_xusb_softc * const); 125 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 126 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 127 size_t); 128 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 129 130 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 131 132 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 133 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 134 135 static int 136 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 137 { 138 struct fdt_attach_args * const faa = aux; 139 140 return of_match_compat_data(faa->faa_phandle, compat_data); 141 } 142 143 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 144 do { \ 145 if (cond) { \ 146 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 147 return; \ 148 } \ 149 } while (0) 150 151 static void 152 tegra_xusb_attach(device_t parent, device_t self, void *aux) 153 { 154 struct tegra_xusb_softc * const psc = device_private(self); 155 struct xhci_softc * const sc = &psc->sc_xhci; 156 struct fdt_attach_args * const faa = aux; 157 bool wait_for_root = true; 158 char intrstr[128]; 159 bus_addr_t addr; 160 bus_size_t size; 161 struct fdtbus_reset *rst; 162 struct fdtbus_phy *phy; 163 struct clk *clk; 164 uint32_t rate; 165 int error, n; 166 167 aprint_naive("\n"); 168 aprint_normal(": XUSB\n"); 169 170 sc->sc_dev = self; 171 sc->sc_iot = faa->faa_bst; 172 sc->sc_bus.ub_hcpriv = sc; 173 sc->sc_bus.ub_dmatag = faa->faa_dmat; 174 sc->sc_quirks = XHCI_DEFERRED_START; 175 psc->sc_phandle = faa->faa_phandle; 176 psc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 177 178 switch (psc->sc_type) { 179 case XUSB_T124: 180 psc->sc_scale_ss_clock = true; 181 break; 182 default: 183 psc->sc_scale_ss_clock = false; 184 break; 185 } 186 187 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 188 aprint_error(": couldn't get registers\n"); 189 return; 190 } 191 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 192 if (error) { 193 aprint_error(": couldn't map %#" PRIx64 ": %d", 194 (uint64_t)addr, error); 195 return; 196 } 197 DPRINTF(sc->sc_dev, "mapped %#" PRIx64 "\n", (uint64_t)addr); 198 199 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 200 aprint_error(": couldn't get registers\n"); 201 return; 202 } 203 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 204 if (error) { 205 aprint_error(": couldn't map %#" PRIx64 ": %d", 206 (uint64_t)addr, error); 207 return; 208 } 209 DPRINTF(sc->sc_dev, "mapped %#" PRIx64 "\n", (uint64_t)addr); 210 211 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 212 aprint_error(": couldn't get registers\n"); 213 return; 214 } 215 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 216 if (error) { 217 aprint_error(": couldn't map %#" PRIx64 ": %d", 218 (uint64_t)addr, error); 219 return; 220 } 221 DPRINTF(sc->sc_dev, "mapped %#" PRIx64 "\n", (uint64_t)addr); 222 223 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 224 aprint_error_dev(self, "failed to decode interrupt\n"); 225 return; 226 } 227 228 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 229 FDT_INTR_MPSAFE, xhci_intr, sc); 230 if (psc->sc_ih == NULL) { 231 aprint_error_dev(self, "failed to establish interrupt on %s\n", 232 intrstr); 233 return; 234 } 235 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 236 237 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 238 aprint_error_dev(self, "failed to decode interrupt\n"); 239 return; 240 } 241 242 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 243 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 244 if (psc->sc_ih_mbox == NULL) { 245 aprint_error_dev(self, "failed to establish interrupt on %s\n", 246 intrstr); 247 return; 248 } 249 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 250 251 /* Enable PHYs */ 252 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 253 if (fdtbus_phy_enable(phy, true) != 0) 254 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 255 256 /* Enable XUSB power rails */ 257 258 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 259 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 260 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 261 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 262 263 /* Enable XUSB clocks */ 264 265 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 266 rate = clk_get_rate(clk); 267 error = clk_enable(clk); /* XXX set frequency */ 268 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 269 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 270 271 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 272 rate = clk_get_rate(clk); 273 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 274 error = clk_set_rate(clk, 102000000); 275 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 276 277 rate = clk_get_rate(clk); 278 error = clk_enable(clk); /* XXX set frequency */ 279 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 280 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 281 282 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 283 rate = clk_get_rate(clk); 284 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 285 error = clk_set_rate(clk, 204000000); 286 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 287 288 rate = clk_get_rate(clk); 289 error = clk_enable(clk); 290 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 291 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 292 293 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 294 rate = clk_get_rate(clk); 295 error = clk_enable(clk); /* XXX set frequency */ 296 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 297 298 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 299 rate = clk_get_rate(clk); 300 error = clk_enable(clk); /* XXX set frequency */ 301 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 302 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 303 304 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 305 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 306 "failed to get xusb_ss_src clock"); 307 308 if (psc->sc_scale_ss_clock) { 309 rate = clk_get_rate(psc->sc_clk_ss_src); 310 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 311 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 312 rate = clk_get_rate(psc->sc_clk_ss_src); 313 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 314 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 315 316 rate = clk_get_rate(psc->sc_clk_ss_src); 317 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 318 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 319 320 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 321 rate = clk_get_rate(psc->sc_clk_ss_src); 322 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 323 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 324 } 325 326 rate = clk_get_rate(psc->sc_clk_ss_src); 327 error = clk_enable(psc->sc_clk_ss_src); 328 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 329 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 330 331 #if 0 332 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 333 error = 0; 334 rate = clk_get_rate(clk); 335 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 336 #endif 337 338 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 339 rate = clk_get_rate(clk); 340 error = clk_enable(clk); /* XXX set frequency */ 341 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 342 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 343 344 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 345 fdtbus_reset_deassert(rst); 346 347 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 348 fdtbus_reset_deassert(rst); 349 350 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 351 fdtbus_reset_deassert(rst); 352 353 DELAY(1); 354 355 tegra_xusb_init_regulators(psc); 356 357 tegra_xusb_init(psc); 358 359 #if defined(TEGRA124_XUSB_BIN_STATIC) 360 if (psc->sc_type == XUSB_T124) 361 wait_for_root = false; 362 #endif 363 #if defined(TEGRA210_XUSB_BIN_STATIC) 364 if (psc->sc_type == XUSB_T210) 365 wait_for_root = false; 366 #endif 367 368 if (wait_for_root) 369 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 370 else 371 tegra_xusb_mountroot(sc->sc_dev); 372 } 373 374 static void 375 tegra_xusb_mountroot(device_t self) 376 { 377 struct tegra_xusb_softc * const psc = device_private(self); 378 struct xhci_softc * const sc = &psc->sc_xhci; 379 const bus_space_tag_t bst = sc->sc_iot; 380 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 381 struct clk *clk; 382 struct fdtbus_reset *rst; 383 uint32_t rate; 384 uint32_t val; 385 int error; 386 387 DPRINTF(sc->sc_dev, "%s()\n", __func__); 388 389 val = bus_space_read_4(bst, ipfsh, 0x0); 390 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 391 392 if (tegra_xusb_open_fw(psc) != 0) 393 return; 394 DPRINTF(sc->sc_dev, "post fw\n"); 395 396 tegra_xusbpad_xhci_enable(); 397 398 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 399 rate = clk_get_rate(clk); 400 error = clk_enable(clk); 401 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 402 403 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 404 rate = clk_get_rate(clk); 405 error = clk_enable(clk); 406 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 407 408 val = bus_space_read_4(bst, ipfsh, 0x0); 409 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 410 411 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 412 fdtbus_reset_deassert(rst); 413 414 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 415 fdtbus_reset_deassert(rst); 416 417 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 418 fdtbus_reset_deassert(rst); 419 420 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 421 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 422 423 val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV) 424 & PCI_USBREV_MASK; 425 switch (val) { 426 case PCI_USBREV_3_0: 427 sc->sc_bus.ub_revision = USBREV_3_0; 428 break; 429 case PCI_USBREV_3_1: 430 sc->sc_bus.ub_revision = USBREV_3_1; 431 break; 432 default: 433 if (val < PCI_USBREV_3_0) { 434 aprint_error_dev(self, "Unknown revision (%02x)\n", val); 435 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 436 } else { 437 /* Default to the latest revision */ 438 aprint_normal_dev(self, 439 "Unknown revision (%02x). Set to 3.1.\n", val); 440 sc->sc_bus.ub_revision = USBREV_3_1; 441 } 442 break; 443 } 444 445 error = xhci_init(sc); 446 if (error) { 447 aprint_error_dev(self, "init failed, error=%d\n", error); 448 return; 449 } 450 451 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 452 453 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 454 455 xhci_start(sc); 456 457 error = xusb_mailbox_send(psc, 0x01000000); 458 if (error) { 459 aprint_error_dev(self, "send failed, error=%d\n", error); 460 } 461 } 462 463 static int 464 tegra_xusb_intr_mbox(void *v) 465 { 466 struct tegra_xusb_softc * const psc = v; 467 struct xhci_softc * const sc = &psc->sc_xhci; 468 const bus_space_tag_t bst = sc->sc_iot; 469 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 470 uint32_t val; 471 uint32_t irv; 472 uint32_t msg; 473 int error; 474 475 DPRINTF(sc->sc_dev, "%s()\n", __func__); 476 477 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 478 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 479 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 480 481 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 482 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 483 484 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 485 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 486 487 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 488 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 489 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 490 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 491 492 bool sendresp = true; 493 u_int rate; 494 495 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 496 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 497 498 switch (type) { 499 case 2: 500 case 3: 501 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 502 break; 503 case 4: 504 case 5: 505 if (psc->sc_scale_ss_clock) { 506 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 507 rate = clk_get_rate(psc->sc_clk_ss_src); 508 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 509 rate); 510 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 511 if (error != 0) 512 goto clk_fail; 513 rate = clk_get_rate(psc->sc_clk_ss_src); 514 DPRINTF(sc->sc_dev, 515 "rate of psc->sc_clk_ss_src %u after\n", rate); 516 if (data == (rate / 1000)) { 517 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 518 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 519 } else 520 clk_fail: 521 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 522 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 523 } else { 524 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 525 __SHIFTIN(data, MAILBOX_DATA_DATA); 526 } 527 xusb_mailbox_send(psc, msg); 528 break; 529 case 9: 530 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 531 __SHIFTIN(128, MAILBOX_DATA_TYPE); 532 xusb_mailbox_send(psc, msg); 533 break; 534 case 6: 535 case 128: 536 case 129: 537 sendresp = false; 538 break; 539 default: 540 sendresp = false; 541 break; 542 } 543 544 if (sendresp == false) 545 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 546 MAILBOX_OWNER_NONE); 547 548 return irv; 549 } 550 551 static void 552 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 553 { 554 const char * supply_names[] = { 555 "dvddio-pex-supply", 556 "hvddio-pex-supply", 557 "avdd-usb-supply", 558 "avdd-pll-utmip-supply", 559 "avdd-pll-uerefe-supply", 560 "dvdd-usb-ss-pll-supply", 561 "hvdd-usb-ss-pll-e-supply" 562 }; 563 device_t dev = psc->sc_xhci.sc_dev; 564 const int phandle = psc->sc_phandle; 565 struct fdtbus_regulator *reg; 566 int n, error; 567 568 for (n = 0; n < __arraycount(supply_names); n++) { 569 if (!of_hasprop(phandle, supply_names[n])) 570 continue; 571 reg = fdtbus_regulator_acquire(phandle, supply_names[n]); 572 if (reg == NULL) { 573 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 574 supply_names[n]); 575 continue; 576 } 577 error = fdtbus_regulator_enable(reg); 578 if (error != 0) 579 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 580 supply_names[n], error); 581 } 582 } 583 584 static void 585 tegra_xusb_init(struct tegra_xusb_softc * const psc) 586 { 587 struct xhci_softc * const sc = &psc->sc_xhci; 588 const bus_space_tag_t bst = sc->sc_iot; 589 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 590 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 591 592 DPRINTF(sc->sc_dev, "%s()\n", __func__); 593 594 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 595 bus_space_read_4(bst, ipfsh, 0x0)); 596 597 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 598 bus_space_read_4(bst, ipfsh, 0x40)); 599 600 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 601 bus_space_read_4(bst, ipfsh, 0x80)); 602 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 603 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 604 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 605 bus_space_read_4(bst, ipfsh, 0x80)); 606 607 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 608 bus_space_read_4(bst, ipfsh, 0x180)); 609 /* EN_FPCI */ 610 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 611 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 612 bus_space_read_4(bst, ipfsh, 0x180)); 613 614 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 615 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 616 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 617 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 618 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 619 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 620 621 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 622 bus_space_read_4(bst, fpcih, PCI_BAR0)); 623 /* match FPCI BAR0 to above */ 624 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 625 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 626 bus_space_read_4(bst, fpcih, PCI_BAR0)); 627 628 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 629 bus_space_read_4(bst, ipfsh, 0x188)); 630 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 631 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 632 bus_space_read_4(bst, ipfsh, 0x188)); 633 634 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 635 bus_space_read_4(bst, fpcih, 0x1bc)); 636 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 637 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 638 bus_space_read_4(bst, fpcih, 0x1bc)); 639 } 640 641 static int 642 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 643 struct fw_dma * const p) 644 { 645 struct xhci_softc * const sc = &psc->sc_xhci; 646 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 647 int err; 648 649 p->size = size; 650 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 651 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 652 if (err) 653 return err; 654 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 655 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 656 if (err) 657 goto free; 658 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 659 &p->map); 660 if (err) 661 goto unmap; 662 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 663 BUS_DMA_NOWAIT); 664 if (err) 665 goto destroy; 666 667 return 0; 668 669 destroy: 670 bus_dmamap_destroy(dmat, p->map); 671 unmap: 672 bus_dmamem_unmap(dmat, p->addr, p->size); 673 free: 674 bus_dmamem_free(dmat, p->segs, p->nsegs); 675 676 return err; 677 } 678 679 #if !defined(TEGRA124_XUSB_BIN_STATIC) 680 static void 681 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 682 { 683 const struct xhci_softc * const sc = &psc->sc_xhci; 684 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 685 686 bus_dmamap_unload(dmat, p->map); 687 bus_dmamap_destroy(dmat, p->map); 688 bus_dmamem_unmap(dmat, p->addr, p->size); 689 bus_dmamem_free(dmat, p->segs, p->nsegs); 690 } 691 #endif 692 693 #define FWHEADER_BOOT_CODETAG 8 694 #define FWHEADER_BOOT_CODESIZE 12 695 #define FWHEADER_FWIMG_LEN 100 696 #define FWHEADER__LEN 256 697 698 static int 699 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 700 { 701 struct xhci_softc * const sc = &psc->sc_xhci; 702 firmware_handle_t fw; 703 size_t firmware_size = 0; 704 void *firmware_image; 705 const char *fw_path = NULL; 706 void *fw_static = NULL; 707 int error; 708 709 switch (psc->sc_type) { 710 case XUSB_T124: 711 #if defined(TEGRA124_XUSB_BIN_STATIC) 712 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 713 fw_static = _binary_tegra124_xusb_bin_start; 714 #else 715 fw_path = "nvidia/tegra124"; 716 #endif 717 break; 718 case XUSB_T210: 719 #if defined(TEGRA210_XUSB_BIN_STATIC) 720 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 721 fw_static = _binary_tegra210_xusb_bin_start; 722 #else 723 fw_path = "nvidia/tegra210"; 724 #endif 725 break; 726 default: 727 return EINVAL; 728 } 729 730 if (fw_path != NULL) { 731 error = firmware_open(fw_path, "xusb.bin", &fw); 732 if (error != 0) { 733 aprint_error_dev(sc->sc_dev, 734 "couldn't load firmware from %s/xusb.bin: %d\n", 735 fw_path, error); 736 return error; 737 } 738 firmware_size = firmware_get_size(fw); 739 } 740 741 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 742 &psc->sc_fw_dma); 743 if (error != 0) 744 return error; 745 firmware_image = psc->sc_fw_dma.addr; 746 747 if (fw_path != NULL) { 748 error = firmware_read(fw, 0, firmware_image, firmware_size); 749 if (error != 0) { 750 fw_dma_free(psc, &psc->sc_fw_dma); 751 firmware_close(fw); 752 return error; 753 } 754 firmware_close(fw); 755 } else { 756 memcpy(firmware_image, fw_static, firmware_size); 757 } 758 759 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 760 } 761 762 static int 763 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 764 size_t firmware_size) 765 { 766 struct xhci_softc * const sc = &psc->sc_xhci; 767 const uint8_t *header; 768 769 header = firmware_image; 770 771 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 772 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 773 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 774 775 if (fwimg_len != firmware_size) 776 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 777 fwimg_len, firmware_size); 778 779 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 780 firmware_size, BUS_DMASYNC_PREWRITE); 781 782 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 783 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 784 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 785 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 786 787 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 788 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 789 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 790 fwimg_len); 791 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 792 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 793 794 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 795 FWHEADER__LEN; 796 797 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 798 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 799 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 800 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 801 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 802 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 803 804 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 805 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 806 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 807 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 808 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 809 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 810 811 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 812 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 813 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 814 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 815 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 816 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 817 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 818 819 const u_int code_tag_blocks = 820 howmany(boot_codetag, IMEM_BLOCK_SIZE); 821 const u_int code_size_blocks = 822 howmany(boot_codesize, IMEM_BLOCK_SIZE); 823 const u_int code_blocks = code_tag_blocks + code_size_blocks; 824 825 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 826 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 827 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 828 __SHIFTIN(code_tag_blocks, 829 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 830 __SHIFTIN(code_size_blocks, 831 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 832 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 833 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 834 835 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 836 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 837 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 838 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 839 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 840 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 841 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 842 843 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 844 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 845 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 846 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 847 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 848 849 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 850 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 851 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 852 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 853 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 854 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 855 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 856 857 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 858 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 859 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 860 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 861 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 862 863 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 864 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 865 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 866 boot_codetag); 867 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 868 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 869 870 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 871 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 872 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 873 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 874 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 875 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 876 877 return 0; 878 } 879 880 static uint32_t 881 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 882 { 883 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 884 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 885 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 886 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 887 888 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 889 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 890 } 891 892 static void 893 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 894 uint32_t value) 895 { 896 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 897 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 898 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 899 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 900 901 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 902 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 903 } 904 905 static int 906 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 907 { 908 struct xhci_softc * const sc = &psc->sc_xhci; 909 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 910 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 911 uint32_t val; 912 bool wait = false; 913 914 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 915 916 if (!(type == 128 || type == 129)) { 917 val = bus_space_read_4(bst, fpcih, 918 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 919 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 920 val); 921 if (val != MAILBOX_OWNER_NONE) { 922 return EBUSY; 923 } 924 925 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 926 MAILBOX_OWNER_SW); 927 928 val = bus_space_read_4(bst, fpcih, 929 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 930 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 931 val); 932 if (val != MAILBOX_OWNER_SW) { 933 return EBUSY; 934 } 935 936 wait = true; 937 } 938 939 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 940 941 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 942 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 943 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 944 945 if (wait) { 946 947 for (u_int i = 0; i < 2500; i++) { 948 val = bus_space_read_4(bst, fpcih, 949 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 950 DPRINTF(sc->sc_dev, 951 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 952 if (val == MAILBOX_OWNER_NONE) { 953 break; 954 } 955 DELAY(10); 956 } 957 958 val = bus_space_read_4(bst, fpcih, 959 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 960 DPRINTF(sc->sc_dev, 961 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 962 if (val != MAILBOX_OWNER_NONE) { 963 aprint_error_dev(sc->sc_dev, 964 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 965 } 966 } 967 968 return 0; 969 } 970