1 /* $NetBSD: tegra_xusb.c,v 1.2 2017/01/03 12:37:08 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.2 2017/01/03 12:37:08 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <dev/firmload.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <dev/usb/xhcireg.h> 58 #include <dev/usb/xhcivar.h> 59 60 static int tegra_xusb_match(device_t, cfdata_t, void *); 61 static void tegra_xusb_attach(device_t, device_t, void *); 62 static void tegra_xusb_mountroot(device_t); 63 64 static int tegra_xusb_intr_mbox(void *); 65 66 #ifdef TEGRA124_XUSB_BIN_STATIC 67 extern const char _binary_tegra124_xusb_bin_size[]; 68 extern const char _binary_tegra124_xusb_bin_start[]; 69 #endif 70 71 struct fw_dma { 72 bus_dmamap_t map; 73 void * addr; 74 bus_dma_segment_t segs[1]; 75 int nsegs; 76 size_t size; 77 }; 78 79 struct tegra_xusb_softc { 80 struct xhci_softc sc_xhci; 81 int sc_phandle; 82 bus_space_handle_t sc_bsh_xhci; 83 bus_space_handle_t sc_bsh_fpci; 84 bus_space_handle_t sc_bsh_ipfs; 85 void *sc_ih; 86 void *sc_ih_mbox; 87 struct fw_dma sc_fw_dma; 88 struct clk *sc_clk_ss_src; 89 }; 90 91 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 92 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 93 uint32_t); 94 95 static void tegra_xusb_init(struct tegra_xusb_softc * const); 96 static void tegra_xusb_load_fw(struct tegra_xusb_softc * const); 97 98 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 99 100 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 101 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 102 103 static int 104 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 105 { 106 const char * const compatible[] = { "nvidia,tegra124-xusb", NULL }; 107 struct fdt_attach_args * const faa = aux; 108 109 return of_match_compatible(faa->faa_phandle, compatible); 110 } 111 112 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 113 do { \ 114 if (cond) { \ 115 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 116 return; \ 117 } \ 118 } while (0) 119 120 static void 121 tegra_xusb_attach(device_t parent, device_t self, void *aux) 122 { 123 struct tegra_xusb_softc * const psc = device_private(self); 124 struct xhci_softc * const sc = &psc->sc_xhci; 125 struct fdt_attach_args * const faa = aux; 126 char intrstr[128]; 127 bus_addr_t addr; 128 bus_size_t size; 129 int error; 130 struct clk *clk; 131 uint32_t rate; 132 struct fdtbus_reset *rst; 133 134 aprint_naive("\n"); 135 aprint_normal(": XUSB\n"); 136 137 sc->sc_dev = self; 138 sc->sc_iot = faa->faa_bst; 139 sc->sc_bus.ub_hcpriv = sc; 140 sc->sc_bus.ub_dmatag = faa->faa_dmat; 141 psc->sc_phandle = faa->faa_phandle; 142 143 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 144 aprint_error(": couldn't get registers\n"); 145 return; 146 } 147 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 148 if (error) { 149 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 150 return; 151 } 152 printf("mapped %#llx\n", (uint64_t)addr); 153 154 if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) { 155 aprint_error(": couldn't get registers\n"); 156 return; 157 } 158 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 159 if (error) { 160 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 161 return; 162 } 163 printf("mapped %#llx\n", (uint64_t)addr); 164 165 if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) { 166 aprint_error(": couldn't get registers\n"); 167 return; 168 } 169 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 170 if (error) { 171 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 172 return; 173 } 174 printf("mapped %#llx\n", (uint64_t)addr); 175 176 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 177 aprint_error_dev(self, "failed to decode interrupt\n"); 178 return; 179 } 180 181 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 182 0, xhci_intr, sc); 183 if (psc->sc_ih == NULL) { 184 aprint_error_dev(self, "failed to establish interrupt on %s\n", 185 intrstr); 186 return; 187 } 188 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 189 190 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 191 aprint_error_dev(self, "failed to decode interrupt\n"); 192 return; 193 } 194 195 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 196 0, tegra_xusb_intr_mbox, psc); 197 if (psc->sc_ih_mbox == NULL) { 198 aprint_error_dev(self, "failed to establish interrupt on %s\n", 199 intrstr); 200 return; 201 } 202 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 203 204 struct clk * const pll_p_out0 = clk_get("pll_p_out0"); 205 KASSERT(pll_p_out0 != NULL); 206 207 struct clk * const pll_u_48 = clk_get("pll_u_48"); 208 KASSERT(pll_u_48 != NULL); 209 210 struct clk * const pll_u_480 = clk_get("pll_u_480"); 211 KASSERT(pll_u_480 != NULL); 212 213 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 214 rate = clk_get_rate(clk); 215 error = clk_enable(clk); /* XXX set frequency */ 216 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 217 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 218 219 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 220 error = clk_set_parent(clk, pll_p_out0); 221 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock parent"); 222 223 rate = clk_get_rate(clk); 224 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 225 error = clk_set_rate(clk, 102000000); 226 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 227 228 rate = clk_get_rate(clk); 229 error = clk_enable(clk); /* XXX set frequency */ 230 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 231 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 232 233 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 234 error = clk_set_parent(clk, pll_p_out0); 235 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock parent"); 236 237 rate = clk_get_rate(clk); 238 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 239 error = clk_set_rate(clk, 204000000); 240 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 241 242 rate = clk_get_rate(clk); 243 error = clk_enable(clk); 244 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 245 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 246 247 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 248 rate = clk_get_rate(clk); 249 error = clk_enable(clk); /* XXX set frequency */ 250 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 251 252 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 253 rate = clk_get_rate(clk); 254 error = clk_enable(clk); /* XXX set frequency */ 255 device_printf(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 256 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 257 258 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 259 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 260 "failed to get xusb_ss_src clock"); 261 rate = clk_get_rate(psc->sc_clk_ss_src); 262 device_printf(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 263 264 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 265 rate = clk_get_rate(psc->sc_clk_ss_src); 266 device_printf(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, 267 error); 268 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 269 270 error = clk_set_parent(psc->sc_clk_ss_src, pll_u_480); 271 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock parent"); 272 273 rate = clk_get_rate(psc->sc_clk_ss_src); 274 device_printf(sc->sc_dev, "ss_src rate %u\n", rate); 275 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 276 277 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 278 rate = clk_get_rate(psc->sc_clk_ss_src); 279 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 280 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 281 282 error = clk_enable(psc->sc_clk_ss_src); 283 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 284 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 285 286 #if 0 287 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 288 error = 0; 289 rate = clk_get_rate(clk); 290 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 291 #endif 292 293 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 294 error = clk_set_parent(clk, pll_u_48); 295 tegra_xusb_attach_check(sc, error, "failed to set xusb_fs_src clock parent"); 296 297 rate = clk_get_rate(clk); 298 error = clk_enable(clk); /* XXX set frequency */ 299 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 300 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 301 302 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 303 fdtbus_reset_deassert(rst); 304 305 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 306 fdtbus_reset_deassert(rst); 307 308 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 309 fdtbus_reset_deassert(rst); 310 311 DELAY(1); 312 313 tegra_xusb_init(psc); 314 315 #if defined(TEGRA124_XUSB_BIN_STATIC) 316 tegra_xusb_mountroot(sc->sc_dev); 317 #else 318 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 319 #endif 320 } 321 322 static void 323 tegra_xusb_mountroot(device_t self) 324 { 325 struct tegra_xusb_softc * const psc = device_private(self); 326 struct xhci_softc * const sc = &psc->sc_xhci; 327 const bus_space_tag_t bst = sc->sc_iot; 328 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 329 struct clk *clk; 330 struct fdtbus_reset *rst; 331 uint32_t rate; 332 uint32_t val; 333 int error; 334 335 device_printf(sc->sc_dev, "%s()\n", __func__); 336 337 val = bus_space_read_4(bst, ipfsh, 0x0); 338 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 339 340 tegra_xusb_load_fw(psc); 341 device_printf(sc->sc_dev, "post fw\n"); 342 343 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 344 rate = clk_get_rate(clk); 345 error = clk_enable(clk); 346 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 347 348 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 349 rate = clk_get_rate(clk); 350 error = clk_enable(clk); 351 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 352 353 val = bus_space_read_4(bst, ipfsh, 0x0); 354 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 355 356 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 357 fdtbus_reset_deassert(rst); 358 359 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 360 fdtbus_reset_deassert(rst); 361 362 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 363 fdtbus_reset_deassert(rst); 364 365 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 366 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 367 368 369 error = xhci_init(sc); 370 if (error) { 371 aprint_error_dev(self, "init failed, error=%d\n", error); 372 return; 373 } 374 375 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 376 377 error = xusb_mailbox_send(psc, 0x01000000); 378 if (error) { 379 aprint_error_dev(self, "send failed, error=%d\n", error); 380 } 381 } 382 383 static int 384 tegra_xusb_intr_mbox(void *v) 385 { 386 struct tegra_xusb_softc * const psc = v; 387 struct xhci_softc * const sc = &psc->sc_xhci; 388 const bus_space_tag_t bst = sc->sc_iot; 389 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 390 uint32_t val; 391 uint32_t irv; 392 uint32_t msg; 393 int error; 394 395 device_printf(sc->sc_dev, "%s()\n", __func__); 396 397 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 398 device_printf(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 399 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 400 401 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 402 device_printf(sc->sc_dev, "firmware hang\n"); 403 404 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 405 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 406 407 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 408 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 409 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 410 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 411 412 bool sendresp = true; 413 u_int rate; 414 415 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 416 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 417 418 switch (type) { 419 case 2: 420 case 3: 421 device_printf(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 422 break; 423 case 4: 424 case 5: 425 device_printf(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 426 rate = clk_get_rate(psc->sc_clk_ss_src); 427 device_printf(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 428 rate); 429 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 430 if (error != 0) 431 goto clk_fail; 432 rate = clk_get_rate(psc->sc_clk_ss_src); 433 device_printf(sc->sc_dev, 434 "rate of psc->sc_clk_ss_src %u after\n", rate); 435 if (data == (rate / 1000)) { 436 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 437 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 438 } else 439 clk_fail: 440 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 441 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 442 xusb_mailbox_send(psc, msg); 443 break; 444 case 9: 445 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 446 __SHIFTIN(128, MAILBOX_DATA_TYPE); 447 xusb_mailbox_send(psc, msg); 448 break; 449 case 6: 450 case 128: 451 case 129: 452 sendresp = false; 453 break; 454 default: 455 sendresp = false; 456 break; 457 } 458 459 if (sendresp == false) 460 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 461 MAILBOX_OWNER_NONE); 462 463 return irv; 464 } 465 466 static void 467 tegra_xusb_init(struct tegra_xusb_softc * const psc) 468 { 469 struct xhci_softc * const sc = &psc->sc_xhci; 470 const bus_space_tag_t bst = sc->sc_iot; 471 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 472 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 473 474 device_printf(sc->sc_dev, "%s()\n", __func__); 475 476 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 477 bus_space_read_4(bst, ipfsh, 0x0)); 478 479 device_printf(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 480 bus_space_read_4(bst, ipfsh, 0x40)); 481 482 device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 483 bus_space_read_4(bst, ipfsh, 0x80)); 484 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 485 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 486 device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 487 bus_space_read_4(bst, ipfsh, 0x80)); 488 489 device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 490 bus_space_read_4(bst, ipfsh, 0x180)); 491 /* EN_FPCI */ 492 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 493 device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 494 bus_space_read_4(bst, ipfsh, 0x180)); 495 496 device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 497 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 498 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 499 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 500 device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 501 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 502 503 device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 504 bus_space_read_4(bst, fpcih, PCI_BAR0)); 505 /* match FPCI BAR0 to above */ 506 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 507 device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 508 bus_space_read_4(bst, fpcih, PCI_BAR0)); 509 510 device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 511 bus_space_read_4(bst, ipfsh, 0x188)); 512 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 513 device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 514 bus_space_read_4(bst, ipfsh, 0x188)); 515 516 device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 517 bus_space_read_4(bst, fpcih, 0x1bc)); 518 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 519 device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 520 bus_space_read_4(bst, fpcih, 0x1bc)); 521 } 522 523 static int 524 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 525 struct fw_dma * const p) 526 { 527 struct xhci_softc * const sc = &psc->sc_xhci; 528 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 529 int err; 530 531 p->size = size; 532 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 533 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 534 if (err) 535 return err; 536 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 537 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 538 if (err) 539 goto free; 540 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 541 &p->map); 542 if (err) 543 goto unmap; 544 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 545 BUS_DMA_NOWAIT); 546 if (err) 547 goto destroy; 548 549 return 0; 550 551 destroy: 552 bus_dmamap_destroy(dmat, p->map); 553 unmap: 554 bus_dmamem_unmap(dmat, p->addr, p->size); 555 free: 556 bus_dmamem_free(dmat, p->segs, p->nsegs); 557 558 return err; 559 } 560 561 #if !defined(TEGRA124_XUSB_BIN_STATIC) 562 static void 563 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 564 { 565 const struct xhci_softc * const sc = &psc->sc_xhci; 566 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 567 568 bus_dmamap_unload(dmat, p->map); 569 bus_dmamap_destroy(dmat, p->map); 570 bus_dmamem_unmap(dmat, p->addr, p->size); 571 bus_dmamem_free(dmat, p->segs, p->nsegs); 572 } 573 #endif 574 575 #define FWHEADER_BOOT_CODETAG 8 576 #define FWHEADER_BOOT_CODESIZE 12 577 #define FWHEADER_FWIMG_LEN 100 578 #define FWHEADER__LEN 256 579 580 static void 581 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc) 582 { 583 struct xhci_softc * const sc = &psc->sc_xhci; 584 #if !defined(TEGRA124_XUSB_BIN_STATIC) 585 firmware_handle_t fw; 586 #endif 587 int error; 588 size_t firmware_size; 589 void * firmware_image; 590 const uint8_t *header; 591 592 #if defined(TEGRA124_XUSB_BIN_STATIC) 593 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 594 #else 595 if ((error = firmware_open("nvidia/tegra124", "xusb.bin", &fw)) != 0) { 596 aprint_error_dev(sc->sc_dev, 597 "could not open firmware file %s: %d\n", "xusb.bin", error); 598 return; 599 } 600 firmware_size = firmware_get_size(fw); 601 #endif 602 603 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, &psc->sc_fw_dma); 604 if (error != 0) { 605 #if !defined(TEGRA124_XUSB_BIN_STATIC) 606 firmware_close(fw); 607 #endif 608 return; 609 } 610 611 firmware_image = psc->sc_fw_dma.addr; 612 device_printf(sc->sc_dev, "blob %p len %zu\n", firmware_image, 613 firmware_size); 614 615 #if defined(TEGRA124_XUSB_BIN_STATIC) 616 memcpy(firmware_image, _binary_tegra124_xusb_bin_start, firmware_size); 617 #else 618 error = firmware_read(fw, 0, firmware_image, firmware_size); 619 if (error != 0) { 620 fw_dma_free(psc, &psc->sc_fw_dma); 621 firmware_close(fw); 622 return; 623 } 624 firmware_close(fw); 625 #endif 626 627 header = firmware_image; 628 629 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 630 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 631 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 632 633 if (fwimg_len != firmware_size) 634 device_printf(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 635 fwimg_len, firmware_size); 636 637 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 638 firmware_size, BUS_DMASYNC_PREWRITE); 639 640 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 641 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 642 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 643 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 644 645 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 646 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 647 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 648 fwimg_len); 649 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 650 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 651 652 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 653 FWHEADER__LEN; 654 655 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 656 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 657 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 658 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 659 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 660 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 661 662 device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 663 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 664 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 665 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 666 device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 667 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 668 669 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 670 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 671 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 672 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 673 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 674 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 675 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 676 677 const u_int code_tag_blocks = 678 howmany(boot_codetag, IMEM_BLOCK_SIZE); 679 const u_int code_size_blocks = 680 howmany(boot_codesize, IMEM_BLOCK_SIZE); 681 const u_int code_blocks = code_tag_blocks + code_size_blocks; 682 683 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 684 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 685 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 686 __SHIFTIN(code_tag_blocks, 687 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 688 __SHIFTIN(code_size_blocks, 689 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 690 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 691 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 692 693 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 694 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 695 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 696 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 697 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 698 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 699 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 700 701 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 702 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 703 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 704 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 705 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 706 707 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 708 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 709 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 710 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 711 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 712 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 713 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 714 715 device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 716 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 717 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 718 device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 719 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 720 721 device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 722 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 723 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 724 boot_codetag); 725 device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 726 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 727 728 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 729 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 730 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 731 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 732 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 733 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 734 } 735 736 static uint32_t 737 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 738 { 739 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 740 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 741 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 742 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 743 744 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 745 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 746 } 747 748 static void 749 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 750 uint32_t value) 751 { 752 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 753 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 754 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 755 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 756 757 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 758 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 759 } 760 761 static int 762 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 763 { 764 struct xhci_softc * const sc = &psc->sc_xhci; 765 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 766 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 767 uint32_t val; 768 bool wait = false; 769 770 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 771 772 if (!(type == 128 || type == 129)) { 773 val = bus_space_read_4(bst, fpcih, 774 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 775 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 776 val); 777 if (val != MAILBOX_OWNER_NONE) { 778 return EBUSY; 779 } 780 781 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 782 MAILBOX_OWNER_SW); 783 784 val = bus_space_read_4(bst, fpcih, 785 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 786 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 787 val); 788 if (val != MAILBOX_OWNER_SW) { 789 return EBUSY; 790 } 791 792 wait = true; 793 } 794 795 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 796 797 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 798 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 799 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 800 801 if (wait) { 802 803 for (u_int i = 0; i < 2500; i++) { 804 val = bus_space_read_4(bst, fpcih, 805 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 806 device_printf(sc->sc_dev, 807 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 808 if (val == MAILBOX_OWNER_NONE) { 809 break; 810 } 811 DELAY(10); 812 } 813 814 val = bus_space_read_4(bst, fpcih, 815 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 816 device_printf(sc->sc_dev, 817 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 818 if (val != MAILBOX_OWNER_NONE) { 819 device_printf(sc->sc_dev, 820 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 821 } 822 } 823 824 return 0; 825 } 826