xref: /netbsd-src/sys/arch/arm/nvidia/tegra_platform.c (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /* $NetBSD: tegra_platform.c,v 1.13 2018/07/08 11:37:50 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include "opt_tegra.h"
30 #include "opt_multiprocessor.h"
31 #include "opt_fdt_arm.h"
32 
33 #include "ukbd.h"
34 
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.13 2018/07/08 11:37:50 jmcneill Exp $");
37 
38 #include <sys/param.h>
39 #include <sys/bus.h>
40 #include <sys/cpu.h>
41 #include <sys/device.h>
42 #include <sys/termios.h>
43 
44 #include <dev/fdt/fdtvar.h>
45 
46 #include <uvm/uvm_extern.h>
47 
48 #include <machine/bootconfig.h>
49 #include <arm/cpufunc.h>
50 
51 #include <arm/nvidia/tegra_reg.h>
52 #include <arm/nvidia/tegra_var.h>
53 #include <arm/nvidia/tegra_platform.h>
54 
55 #include <arm/fdt/arm_fdtvar.h>
56 
57 #include <arm/arm/psci.h>
58 #include <arm/fdt/psci_fdt.h>
59 
60 #if NUKBD > 0
61 #include <dev/usb/ukbdvar.h>
62 #endif
63 
64 #include <dev/ic/ns16550reg.h>
65 #include <dev/ic/comreg.h>
66 
67 #define	PLLP_OUT0_FREQ	408000000
68 
69 void tegra_platform_early_putchar(char);
70 
71 static const struct pmap_devmap *
72 tegra_platform_devmap(void)
73 {
74 	static const struct pmap_devmap devmap[] = {
75 		DEVMAP_ENTRY(TEGRA_HOST1X_VBASE,
76 			     TEGRA_HOST1X_BASE,
77 			     TEGRA_HOST1X_SIZE),
78 		DEVMAP_ENTRY(TEGRA_PPSB_VBASE,
79 			     TEGRA_PPSB_BASE,
80 			     TEGRA_PPSB_SIZE),
81 		DEVMAP_ENTRY(TEGRA_APB_VBASE,
82 			     TEGRA_APB_BASE,
83 			     TEGRA_APB_SIZE),
84 		DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE,
85 			     TEGRA_AHB_A2_BASE,
86 			     TEGRA_AHB_A2_SIZE),
87 		DEVMAP_ENTRY_END
88 	};
89 
90 	return devmap;
91 }
92 
93 #ifdef SOC_TEGRA124
94 static void
95 tegra124_platform_bootstrap(void)
96 {
97 	tegra_bootstrap();
98 
99 #ifdef MULTIPROCESSOR
100 	tegra124_mpinit();
101 #endif
102 }
103 #endif
104 
105 #ifdef SOC_TEGRA210
106 static void
107 tegra210_platform_bootstrap(void)
108 {
109 	tegra_bootstrap();
110 
111 #if defined(MULTIPROCESSOR) && defined(__aarch64__)
112 	psci_fdt_bootstrap();
113 #endif
114 }
115 #endif
116 
117 static void
118 tegra_platform_init_attach_args(struct fdt_attach_args *faa)
119 {
120 	extern struct bus_space arm_generic_bs_tag;
121 	extern struct bus_space arm_generic_a4x_bs_tag;
122 	extern struct arm32_bus_dma_tag arm_generic_dma_tag;
123 
124 	faa->faa_bst = &arm_generic_bs_tag;
125 	faa->faa_a4x_bst = &arm_generic_a4x_bs_tag;
126 	faa->faa_dmat = &arm_generic_dma_tag;
127 }
128 
129 void
130 tegra_platform_early_putchar(char c)
131 {
132 #ifdef CONSADDR
133 #define CONSADDR_VA	(CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
134 
135 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
136 	    (volatile uint32_t *)CONSADDR_VA :
137 	    (volatile uint32_t *)CONSADDR;
138 
139 	while ((uartaddr[com_lsr] & LSR_TXRDY) == 0)
140 		;
141 
142 	uartaddr[com_data] = c;
143 #endif
144 }
145 
146 static void
147 tegra_platform_device_register(device_t self, void *aux)
148 {
149 	prop_dictionary_t dict = device_properties(self);
150 
151 	if (device_is_a(self, "tegrafb") &&
152 	    match_bootconf_option(boot_args, "console", "fb")) {
153 		prop_dictionary_set_bool(dict, "is_console", true);
154 #if NUKBD > 0
155 		ukbd_cnattach();
156 #endif
157 	}
158 
159 	if (device_is_a(self, "tegradrm")) {
160 		const char *video = get_bootconf_string(boot_args, "video");
161 		if (video)
162 			prop_dictionary_set_cstring(dict, "HDMI-A-1", video);
163 		if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi"))
164 			prop_dictionary_set_bool(dict, "force-dvi", true);
165 	}
166 
167 	if (device_is_a(self, "tegracec"))
168 		prop_dictionary_set_cstring(dict, "hdmi-device", "tegradrm0");
169 
170 	if (device_is_a(self, "nouveau")) {
171 		const char *config = get_bootconf_string(boot_args,
172 		    "nouveau.config");
173 		if (config)
174 			prop_dictionary_set_cstring(dict, "config", config);
175 		const char *debug = get_bootconf_string(boot_args,
176 		    "nouveau.debug");
177 		if (debug)
178 			prop_dictionary_set_cstring(dict, "debug", debug);
179 	}
180 
181 	if (device_is_a(self, "tegrapcie")) {
182 		const char * const jetsontk1_compat[] = {
183 		    "nvidia,jetson-tk1", NULL
184 		};
185 		const int phandle = OF_peer(0);
186 		if (of_match_compatible(phandle, jetsontk1_compat)) {
187 			/* rfkill GPIO at GPIO X7 */
188 			struct tegra_gpio_pin *pin =
189 			    tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT);
190 			if (pin)
191 				tegra_gpio_write(pin, 1);
192 		}
193 	}
194 }
195 
196 static void
197 tegra_platform_reset(void)
198 {
199 	tegra_pmc_reset();
200 }
201 
202 static void
203 tegra_platform_delay(u_int us)
204 {
205 	tegra_timer_delay(us);
206 }
207 
208 static u_int
209 tegra_platform_uart_freq(void)
210 {
211 	return PLLP_OUT0_FREQ;
212 }
213 
214 #ifdef SOC_TEGRA124
215 static const struct arm_platform tegra124_platform = {
216 	.devmap = tegra_platform_devmap,
217 	.bootstrap = tegra124_platform_bootstrap,
218 	.init_attach_args = tegra_platform_init_attach_args,
219 	.early_putchar = tegra_platform_early_putchar,
220 	.device_register = tegra_platform_device_register,
221 	.reset = tegra_platform_reset,
222 	.delay = tegra_platform_delay,
223 	.uart_freq = tegra_platform_uart_freq,
224 };
225 
226 ARM_PLATFORM(tegra124, "nvidia,tegra124", &tegra124_platform);
227 #endif
228 
229 #ifdef SOC_TEGRA210
230 static const struct arm_platform tegra210_platform = {
231 	.devmap = tegra_platform_devmap,
232 	.bootstrap = tegra210_platform_bootstrap,
233 	.init_attach_args = tegra_platform_init_attach_args,
234 	.early_putchar = tegra_platform_early_putchar,
235 	.device_register = tegra_platform_device_register,
236 	.reset = tegra_platform_reset,
237 	.delay = tegra_platform_delay,
238 	.uart_freq = tegra_platform_uart_freq,
239 };
240 
241 ARM_PLATFORM(tegra210, "nvidia,tegra210", &tegra210_platform);
242 #endif
243