1 /* $NetBSD: tegra_platform.c,v 1.7 2017/07/20 01:46:15 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_fdt_arm.h" 32 33 #include "ukbd.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.7 2017/07/20 01:46:15 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/bootconfig.h> 49 #include <arm/cpufunc.h> 50 51 #include <arm/nvidia/tegra_reg.h> 52 #include <arm/nvidia/tegra_var.h> 53 54 #include <arm/fdt/arm_fdtvar.h> 55 56 #if NUKBD > 0 57 #include <dev/usb/ukbdvar.h> 58 #endif 59 60 #include <dev/ic/ns16550reg.h> 61 #include <dev/ic/comreg.h> 62 63 #define PLLP_OUT0_FREQ 408000000 64 65 #define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET) 66 #define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE) 67 #define DEVMAP_ENTRY(va, pa, sz) \ 68 { \ 69 .pd_va = DEVMAP_ALIGN(va), \ 70 .pd_pa = DEVMAP_ALIGN(pa), \ 71 .pd_size = DEVMAP_SIZE(sz), \ 72 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 73 .pd_cache = PTE_NOCACHE \ 74 } 75 #define DEVMAP_ENTRY_END { 0 } 76 77 static const struct pmap_devmap * 78 tegra_platform_devmap(void) 79 { 80 static const struct pmap_devmap devmap[] = { 81 DEVMAP_ENTRY(TEGRA_HOST1X_VBASE, 82 TEGRA_HOST1X_BASE, 83 TEGRA_HOST1X_SIZE), 84 DEVMAP_ENTRY(TEGRA_PPSB_VBASE, 85 TEGRA_PPSB_BASE, 86 TEGRA_PPSB_SIZE), 87 DEVMAP_ENTRY(TEGRA_APB_VBASE, 88 TEGRA_APB_BASE, 89 TEGRA_APB_SIZE), 90 DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE, 91 TEGRA_AHB_A2_BASE, 92 TEGRA_AHB_A2_SIZE), 93 DEVMAP_ENTRY_END 94 }; 95 96 return devmap; 97 } 98 99 static void 100 tegra124_platform_bootstrap(void) 101 { 102 tegra_bootstrap(); 103 104 tegra124_mpinit(); 105 } 106 107 static void 108 tegra210_platform_bootstrap(void) 109 { 110 tegra_bootstrap(); 111 112 tegra210_mpinit(); 113 } 114 115 static void 116 tegra_platform_init_attach_args(struct fdt_attach_args *faa) 117 { 118 extern struct bus_space armv7_generic_bs_tag; 119 extern struct bus_space armv7_generic_a4x_bs_tag; 120 extern struct arm32_bus_dma_tag armv7_generic_dma_tag; 121 122 faa->faa_bst = &armv7_generic_bs_tag; 123 faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag; 124 faa->faa_dmat = &armv7_generic_dma_tag; 125 } 126 127 static void 128 tegra_platform_early_putchar(char c) 129 { 130 #ifdef CONSADDR 131 #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE) 132 volatile uint32_t *uartaddr = (volatile uint32_t *)CONSADDR_VA; 133 134 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 135 ; 136 137 uartaddr[com_data] = c; 138 #endif 139 } 140 141 static void 142 tegra_platform_device_register(device_t self, void *aux) 143 { 144 prop_dictionary_t dict = device_properties(self); 145 146 if (device_is_a(self, "tegrafb") && 147 match_bootconf_option(boot_args, "console", "fb")) { 148 prop_dictionary_set_bool(dict, "is_console", true); 149 #if NUKBD > 0 150 ukbd_cnattach(); 151 #endif 152 } 153 154 if (device_is_a(self, "tegradrm")) { 155 const char *video = get_bootconf_string(boot_args, "video"); 156 if (video) 157 prop_dictionary_set_cstring(dict, "HDMI-A-1", video); 158 if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi")) 159 prop_dictionary_set_bool(dict, "force-dvi", true); 160 } 161 162 if (device_is_a(self, "tegracec")) 163 prop_dictionary_set_cstring(dict, "hdmi-device", "tegradrm0"); 164 165 if (device_is_a(self, "nouveau")) { 166 const char *config = get_bootconf_string(boot_args, 167 "nouveau.config"); 168 if (config) 169 prop_dictionary_set_cstring(dict, "config", config); 170 const char *debug = get_bootconf_string(boot_args, 171 "nouveau.debug"); 172 if (debug) 173 prop_dictionary_set_cstring(dict, "debug", debug); 174 } 175 176 if (device_is_a(self, "tegrapcie")) { 177 const char * const jetsontk1_compat[] = { 178 "nvidia,jetson-tk1", NULL 179 }; 180 const int phandle = OF_peer(0); 181 if (of_match_compatible(phandle, jetsontk1_compat)) { 182 /* rfkill GPIO at GPIO X7 */ 183 struct tegra_gpio_pin *pin = 184 tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT); 185 if (pin) 186 tegra_gpio_write(pin, 1); 187 } 188 } 189 } 190 191 static void 192 tegra_platform_reset(void) 193 { 194 tegra_pmc_reset(); 195 } 196 197 static void 198 tegra_platform_delay(u_int us) 199 { 200 tegra_timer_delay(us); 201 } 202 203 static u_int 204 tegra_platform_uart_freq(void) 205 { 206 return PLLP_OUT0_FREQ; 207 } 208 209 static const struct arm_platform tegra124_platform = { 210 .devmap = tegra_platform_devmap, 211 .bootstrap = tegra124_platform_bootstrap, 212 .init_attach_args = tegra_platform_init_attach_args, 213 .early_putchar = tegra_platform_early_putchar, 214 .device_register = tegra_platform_device_register, 215 .reset = tegra_platform_reset, 216 .delay = tegra_platform_delay, 217 .uart_freq = tegra_platform_uart_freq, 218 }; 219 220 ARM_PLATFORM(tegra124, "nvidia,tegra124", &tegra124_platform); 221 222 static const struct arm_platform tegra210_platform = { 223 .devmap = tegra_platform_devmap, 224 .bootstrap = tegra210_platform_bootstrap, 225 .init_attach_args = tegra_platform_init_attach_args, 226 .early_putchar = tegra_platform_early_putchar, 227 .device_register = tegra_platform_device_register, 228 .reset = tegra_platform_reset, 229 .delay = tegra_platform_delay, 230 .uart_freq = tegra_platform_uart_freq, 231 }; 232 233 ARM_PLATFORM(tegra210, "nvidia,tegra210", &tegra210_platform); 234