1 /* $NetBSD: tegra_pinmux.c,v 1.2 2018/07/16 23:11:47 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2015-2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_pinmux.c,v 1.2 2018/07/16 23:11:47 christos Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/types.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/kmem.h> 42 43 #include <arm/nvidia/tegra_reg.h> 44 #include <arm/nvidia/tegra_var.h> 45 #include <arm/nvidia/tegra_pinmux.h> 46 47 #include <dev/fdt/fdtvar.h> 48 49 /* PINMUX fields */ 50 #define PINMUX_DRV_TYPE __BITS(14,13) 51 #define PINMUX_E_SCHMT __BIT(12) 52 #define PINMUX_E_OD __BIT(11) 53 #define PINMUX_E_IO_HV __BIT(10) 54 #define PINMUX_E_HSM __BIT(9) 55 #define PINMUX_LOCK __BIT(7) 56 #define PINMUX_E_INPUT __BIT(6) 57 #define PINMUX_PARK __BIT(5) 58 #define PINMUX_TRISTATE __BIT(4) 59 #define PINMUX_PUPD __BITS(3,2) 60 #define PINMUX_PM __BITS(1,0) 61 62 struct tegra_pinmux_softc { 63 device_t sc_dev; 64 bus_space_tag_t sc_bst; 65 bus_space_handle_t sc_bsh[2]; 66 const struct tegra_pinmux_conf *sc_conf; 67 }; 68 69 #define PADCTRL_WRITE(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[0], (reg), (val)) 71 #define PADCTRL_READ(sc, reg) \ 72 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[0], (reg)) 73 #define PINMUX_WRITE(sc, reg, val) \ 74 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[1], (reg), (val)) 75 #define PINMUX_READ(sc, reg) \ 76 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[1], (reg)) 77 78 static const struct of_compat_data compat_data[] = { 79 #ifdef SOC_TEGRA210 80 { "nvidia,tegra210-pinmux", (uintptr_t)&tegra210_pinmux_conf }, 81 #endif 82 { NULL } 83 }; 84 85 static const struct tegra_pinmux_pins * 86 tegra_pinmux_lookup_byname(struct tegra_pinmux_softc *sc, const char *name) 87 { 88 const struct tegra_pinmux_pins *pin_def; 89 u_int n; 90 91 for (n = 0; n < sc->sc_conf->npins; n++) { 92 pin_def = &sc->sc_conf->pins[n]; 93 if (strcmp(pin_def->name, name) == 0) 94 return pin_def; 95 } 96 97 return NULL; 98 } 99 100 static int 101 tegra_pinmux_lookup_func(const struct tegra_pinmux_pins *pin_def, const int phandle) 102 { 103 const char *func; 104 u_int n, valid; 105 106 func = fdtbus_get_string(phandle, "nvidia,function"); 107 if (func == NULL) 108 return -1; 109 110 for (n = 0, valid = 0; n < TEGRA_PINMUX_MAXFUNC; n++) { 111 if (pin_def->functions[n] == NULL) 112 continue; 113 ++valid; 114 if (strcmp(pin_def->functions[n], func) == 0) 115 return n; 116 } 117 118 if (valid > 0) 119 aprint_error("%s: pin %s does not support function %s\n", 120 __func__, pin_def->name, func); 121 122 return -1; 123 } 124 125 static void 126 tegra_pinmux_pin_config(struct tegra_pinmux_softc *sc, 127 const struct tegra_pinmux_pins *pin_def, const int phandle) 128 { 129 uint32_t cfg; 130 u_int val; 131 132 cfg = PINMUX_READ(sc, pin_def->reg); 133 const uint32_t ocfg = cfg; 134 135 const int func = tegra_pinmux_lookup_func(pin_def, phandle); 136 if (func != -1) { 137 cfg &= ~PINMUX_PM; 138 cfg |= __SHIFTIN(func, PINMUX_PM); 139 } 140 if (of_getprop_uint32(phandle, "nvidia,pull", &val) == 0) { 141 cfg &= ~PINMUX_PUPD; 142 cfg |= __SHIFTIN(val, PINMUX_PUPD); 143 } 144 if (of_getprop_uint32(phandle, "nvidia,tristate", &val) == 0) { 145 cfg &= ~PINMUX_TRISTATE; 146 cfg |= __SHIFTIN(val, PINMUX_TRISTATE); 147 } 148 if (of_getprop_uint32(phandle, "nvidia,open-drain", &val) == 0) { 149 cfg &= ~PINMUX_E_OD; 150 cfg |= __SHIFTIN(val, PINMUX_E_OD); 151 } 152 if (of_getprop_uint32(phandle, "nvidia,lock", &val) == 0) { 153 cfg &= ~PINMUX_LOCK; 154 cfg |= __SHIFTIN(val, PINMUX_LOCK); 155 } 156 if (of_getprop_uint32(phandle, "nvidia,io-hv", &val) == 0) { 157 cfg &= ~PINMUX_E_IO_HV; 158 cfg |= __SHIFTIN(val, PINMUX_E_IO_HV); 159 } 160 if (of_getprop_uint32(phandle, "nvidia,high-speed-mode", &val) == 0) { 161 cfg &= ~PINMUX_E_HSM; 162 cfg |= __SHIFTIN(val, PINMUX_E_HSM); 163 } 164 if (of_getprop_uint32(phandle, "nvidia,schmitt", &val) == 0) { 165 cfg &= ~PINMUX_E_SCHMT; 166 cfg |= __SHIFTIN(val, PINMUX_E_SCHMT); 167 } 168 if (of_getprop_uint32(phandle, "nvidia,drive-type", &val) == 0) { 169 cfg &= ~PINMUX_DRV_TYPE; 170 cfg |= __SHIFTIN(val, PINMUX_DRV_TYPE); 171 } 172 173 aprint_debug_dev(sc->sc_dev, "pin %s %08x -> %08x\n", pin_def->name, ocfg, cfg); 174 if (cfg != ocfg) 175 PINMUX_WRITE(sc, pin_def->reg, cfg); 176 177 /* 178 * Not yet supported (PADCTRL): 179 * nvidia,pull-down-strength, nvidia,pull-up-strength 180 * nvidia,slew-rate-rising, nvidia,slew-rate-falling 181 */ 182 } 183 184 static int 185 tegra_pinmux_set_config(device_t dev, const void *data, size_t len) 186 { 187 struct tegra_pinmux_softc * const sc = device_private(dev); 188 const struct tegra_pinmux_pins *pin_def; 189 int child; 190 191 if (len != 4) 192 return -1; 193 194 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 195 196 for (child = OF_child(phandle); child; child = OF_peer(child)) { 197 const char *pins = fdtbus_get_string(child, "nvidia,pins"); 198 if (pins == NULL) { 199 aprint_error_dev(dev, "skipping %s (no nvidia,pins property)\n", 200 fdtbus_get_string(child, "name")); 201 continue; 202 } 203 int pins_len = OF_getproplen(child, "nvidia,pins"); 204 205 for (; pins_len > 0; 206 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 207 pin_def = tegra_pinmux_lookup_byname(sc, pins); 208 if (pin_def == NULL) { 209 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 210 continue; 211 } 212 213 tegra_pinmux_pin_config(sc, pin_def, child); 214 } 215 } 216 217 return 0; 218 } 219 220 static struct fdtbus_pinctrl_controller_func tegra_pinmux_funcs = { 221 .set_config = tegra_pinmux_set_config, 222 }; 223 224 static int 225 tegra_pinmux_match(device_t parent, cfdata_t cf, void *aux) 226 { 227 struct fdt_attach_args * const faa = aux; 228 229 return of_match_compat_data(faa->faa_phandle, compat_data); 230 } 231 232 static void 233 tegra_pinmux_attach(device_t parent, device_t self, void *aux) 234 { 235 struct tegra_pinmux_softc * const sc = device_private(self); 236 struct fdt_attach_args * const faa = aux; 237 const int phandle = faa->faa_phandle; 238 bus_addr_t addr; 239 bus_size_t size; 240 int error, res; 241 int child; 242 243 sc->sc_dev = self; 244 sc->sc_bst = faa->faa_bst; 245 for (res = 0; res < __arraycount(sc->sc_bsh); res++) { 246 error = fdtbus_get_reg(phandle, res, &addr, &size); 247 if (error != 0) { 248 aprint_error(": couldn't get resource %d: %d\n", res, error); 249 return; 250 } 251 error = bus_space_map(sc->sc_bst, addr, size, res, &sc->sc_bsh[res]); 252 if (error) { 253 aprint_error(": couldn't map %#" PRIx64 ": %d", 254 (uint64_t)addr, error); 255 return; 256 } 257 } 258 sc->sc_conf = (void *)of_search_compatible(phandle, compat_data)->data; 259 260 aprint_naive("\n"); 261 aprint_normal(": Pinmux\n"); 262 263 for (child = OF_child(phandle); child; child = OF_peer(child)) 264 fdtbus_register_pinctrl_config(self, child, &tegra_pinmux_funcs); 265 266 fdtbus_pinctrl_configure(); 267 } 268 269 CFATTACH_DECL_NEW(tegra_pinmux, sizeof(struct tegra_pinmux_softc), 270 tegra_pinmux_match, tegra_pinmux_attach, NULL, NULL); 271