1 /* $NetBSD: tegra_pcie.c,v 1.26 2019/03/12 18:46:20 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_pcie.c,v 1.26 2019/03/12 18:46:20 jakllsch Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <arm/nvidia/tegra_reg.h> 52 #include <arm/nvidia/tegra_pciereg.h> 53 #include <arm/nvidia/tegra_pmcreg.h> 54 #include <arm/nvidia/tegra_var.h> 55 56 #include <dev/fdt/fdtvar.h> 57 58 /* Interrupt handle flags */ 59 #define IH_MPSAFE 0x80000000 60 61 static int tegra_pcie_match(device_t, cfdata_t, void *); 62 static void tegra_pcie_attach(device_t, device_t, void *); 63 64 #define TEGRA_PCIE_NBUS 256 65 #define TEGRA_PCIE_ECFB (1<<(12 - 8)) /* extended conf frags per bus */ 66 67 struct tegra_pcie_ih { 68 int (*ih_callback)(void *); 69 void *ih_arg; 70 int ih_ipl; 71 int ih_mpsafe; 72 TAILQ_ENTRY(tegra_pcie_ih) ih_entry; 73 }; 74 75 struct tegra_pcie_softc { 76 device_t sc_dev; 77 bus_dma_tag_t sc_dmat; 78 bus_space_tag_t sc_bst; 79 bus_space_handle_t sc_bsh_afi; 80 bus_space_handle_t sc_bsh_pads; 81 bus_space_handle_t sc_bsh_rpconf; 82 int sc_phandle; 83 84 struct arm32_pci_chipset sc_pc; 85 86 void *sc_ih; 87 88 kmutex_t sc_lock; 89 90 TAILQ_HEAD(, tegra_pcie_ih) sc_intrs; 91 u_int sc_intrgen; 92 93 bus_space_handle_t sc_bsh_extc[TEGRA_PCIE_NBUS-1][TEGRA_PCIE_ECFB]; 94 }; 95 96 static int tegra_pcie_intr(void *); 97 static void tegra_pcie_init(pci_chipset_tag_t, void *); 98 static void tegra_pcie_enable(struct tegra_pcie_softc *); 99 static void tegra_pcie_enable_ports(struct tegra_pcie_softc *); 100 static void tegra_pcie_enable_clocks(struct tegra_pcie_softc *); 101 static void tegra_pcie_setup(struct tegra_pcie_softc * const); 102 static void tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const, 103 uint, uint); 104 static void tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const, uint); 105 static void tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const); 106 107 static void tegra_pcie_attach_hook(device_t, device_t, 108 struct pcibus_attach_args *); 109 static int tegra_pcie_bus_maxdevs(void *, int); 110 static pcitag_t tegra_pcie_make_tag(void *, int, int, int); 111 static void tegra_pcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 112 static pcireg_t tegra_pcie_conf_read(void *, pcitag_t, int); 113 static void tegra_pcie_conf_write(void *, pcitag_t, int, pcireg_t); 114 static int tegra_pcie_conf_hook(void *, int, int, int, pcireg_t); 115 static void tegra_pcie_conf_interrupt(void *, int, int, int, int, int *); 116 117 static int tegra_pcie_intr_map(const struct pci_attach_args *, 118 pci_intr_handle_t *); 119 static const char *tegra_pcie_intr_string(void *, pci_intr_handle_t, 120 char *, size_t); 121 const struct evcnt *tegra_pcie_intr_evcnt(void *, pci_intr_handle_t); 122 static int tegra_pcie_intr_setattr(void *, pci_intr_handle_t *, int, 123 uint64_t); 124 static void * tegra_pcie_intr_establish(void *, pci_intr_handle_t, 125 int, int (*)(void *), void *, 126 const char *); 127 static void tegra_pcie_intr_disestablish(void *, void *); 128 129 CFATTACH_DECL_NEW(tegra_pcie, sizeof(struct tegra_pcie_softc), 130 tegra_pcie_match, tegra_pcie_attach, NULL, NULL); 131 132 static int 133 tegra_pcie_match(device_t parent, cfdata_t cf, void *aux) 134 { 135 const char * const compatible[] = { 136 "nvidia,tegra210-pcie", 137 "nvidia,tegra124-pcie", 138 NULL 139 }; 140 struct fdt_attach_args * const faa = aux; 141 142 return of_match_compatible(faa->faa_phandle, compatible); 143 } 144 145 static void 146 tegra_pcie_attach(device_t parent, device_t self, void *aux) 147 { 148 struct tegra_pcie_softc * const sc = device_private(self); 149 struct fdt_attach_args * const faa = aux; 150 struct extent *ioext, *memext, *pmemext; 151 struct pcibus_attach_args pba; 152 bus_addr_t afi_addr, cs_addr, pads_addr; 153 bus_size_t afi_size, cs_size, pads_size; 154 char intrstr[128]; 155 int error; 156 157 if (fdtbus_get_reg_byname(faa->faa_phandle, "afi", &afi_addr, &afi_size) != 0) { 158 aprint_error(": couldn't get afi registers\n"); 159 return; 160 } 161 if (fdtbus_get_reg_byname(faa->faa_phandle, "pads", &pads_addr, &pads_size) != 0) { 162 aprint_error(": couldn't get pads registers\n"); 163 return; 164 } 165 #if notyet 166 if (fdtbus_get_reg(faa->faa_phandle, 2, &cs_addr, &cs_size) != 0) { 167 aprint_error(": couldn't get cs registers\n"); 168 return; 169 } 170 #else 171 cs_addr = TEGRA_PCIE_RPCONF_BASE; 172 cs_size = TEGRA_PCIE_RPCONF_SIZE; 173 #endif 174 175 sc->sc_dev = self; 176 sc->sc_dmat = faa->faa_dmat; 177 sc->sc_bst = faa->faa_bst; 178 sc->sc_phandle = faa->faa_phandle; 179 error = bus_space_map(sc->sc_bst, afi_addr, afi_size, 0, 180 &sc->sc_bsh_afi); 181 if (error) { 182 aprint_error(": couldn't map afi registers: %d\n", error); 183 return; 184 } 185 error = bus_space_map(sc->sc_bst, pads_addr, pads_size, 0, 186 &sc->sc_bsh_pads); 187 if (error) { 188 aprint_error(": couldn't map pads registers: %d\n", error); 189 return; 190 } 191 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, 192 &sc->sc_bsh_rpconf); 193 if (error) { 194 aprint_error(": couldn't map cs registers: %d\n", error); 195 return; 196 } 197 198 tegra_pcie_conf_map_buses(sc); 199 200 TAILQ_INIT(&sc->sc_intrs); 201 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 202 203 aprint_naive("\n"); 204 aprint_normal(": PCIE\n"); 205 206 tegra_pmc_power(PMC_PARTID_PCX, true); 207 tegra_pmc_remove_clamping(PMC_PARTID_PCX); 208 209 tegra_pcie_enable_clocks(sc); 210 211 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 212 aprint_error_dev(self, "failed to decode interrupt\n"); 213 return; 214 } 215 216 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 217 FDT_INTR_MPSAFE, tegra_pcie_intr, sc); 218 if (sc->sc_ih == NULL) { 219 aprint_error_dev(self, "failed to establish interrupt on %s\n", 220 intrstr); 221 return; 222 } 223 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 224 225 tegra_pcie_setup(sc); 226 227 tegra_pcie_init(&sc->sc_pc, sc); 228 229 ioext = extent_create("pciio", TEGRA_PCIE_IO_BASE, 230 TEGRA_PCIE_IO_BASE + TEGRA_PCIE_IO_SIZE - 1, 231 NULL, 0, EX_NOWAIT); 232 memext = extent_create("pcimem", TEGRA_PCIE_MEM_BASE, 233 TEGRA_PCIE_MEM_BASE + TEGRA_PCIE_MEM_SIZE - 1, 234 NULL, 0, EX_NOWAIT); 235 pmemext = extent_create("pcipmem", TEGRA_PCIE_PMEM_BASE, 236 TEGRA_PCIE_PMEM_BASE + TEGRA_PCIE_PMEM_SIZE - 1, 237 NULL, 0, EX_NOWAIT); 238 239 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, 0, 240 arm_dcache_align); 241 242 extent_destroy(ioext); 243 extent_destroy(memext); 244 extent_destroy(pmemext); 245 246 if (error) { 247 aprint_error_dev(self, "configuration failed (%d)\n", 248 error); 249 return; 250 } 251 252 tegra_pcie_enable(sc); 253 254 tegra_pcie_enable_ports(sc); 255 256 memset(&pba, 0, sizeof(pba)); 257 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 258 PCI_FLAGS_MRM_OKAY | 259 PCI_FLAGS_MWI_OKAY | 260 PCI_FLAGS_MEM_OKAY | 261 PCI_FLAGS_IO_OKAY; 262 pba.pba_iot = sc->sc_bst; 263 pba.pba_memt = sc->sc_bst; 264 pba.pba_dmat = sc->sc_dmat; 265 pba.pba_pc = &sc->sc_pc; 266 pba.pba_bus = 0; 267 268 config_found_ia(self, "pcibus", &pba, pcibusprint); 269 } 270 271 static int 272 tegra_pcie_legacy_intr(struct tegra_pcie_softc *sc) 273 { 274 const uint32_t msg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 275 AFI_MSG_REG); 276 struct tegra_pcie_ih *pcie_ih; 277 int rv = 0; 278 279 if (msg & (AFI_MSG_INT0|AFI_MSG_INT1)) { 280 mutex_enter(&sc->sc_lock); 281 const u_int lastgen = sc->sc_intrgen; 282 TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) { 283 int (*callback)(void *) = pcie_ih->ih_callback; 284 void *arg = pcie_ih->ih_arg; 285 const int mpsafe = pcie_ih->ih_mpsafe; 286 mutex_exit(&sc->sc_lock); 287 288 if (!mpsafe) 289 KERNEL_LOCK(1, curlwp); 290 rv += callback(arg); 291 if (!mpsafe) 292 KERNEL_UNLOCK_ONE(curlwp); 293 294 mutex_enter(&sc->sc_lock); 295 if (lastgen != sc->sc_intrgen) 296 break; 297 } 298 mutex_exit(&sc->sc_lock); 299 } else if (msg & (AFI_MSG_PM_PME0|AFI_MSG_PM_PME1)) { 300 device_printf(sc->sc_dev, "PM PME message; AFI_MSG=%08x\n", 301 msg); 302 } else { 303 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_MSG_REG, msg); 304 rv = 1; 305 } 306 307 return rv; 308 } 309 310 static int 311 tegra_pcie_intr(void *priv) 312 { 313 struct tegra_pcie_softc *sc = priv; 314 int rv; 315 316 const uint32_t code = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 317 AFI_INTR_CODE_REG); 318 const uint32_t sig = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, 319 AFI_INTR_SIGNATURE_REG); 320 321 switch (__SHIFTOUT(code, AFI_INTR_CODE_INT_CODE)) { 322 case AFI_INTR_CODE_SM_MSG: 323 rv = tegra_pcie_legacy_intr(sc); 324 break; 325 default: 326 device_printf(sc->sc_dev, "intr: code %#x sig %#x\n", 327 code, sig); 328 rv = 1; 329 break; 330 } 331 332 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 333 334 return rv; 335 } 336 337 static void 338 tegra_pcie_enable_clocks(struct tegra_pcie_softc * const sc) 339 { 340 const char *clock_names[] = { "pex", "afi", "pll_e", "cml" }; 341 const char *reset_names[] = { "pex", "afi", "pcie_x" }; 342 struct fdtbus_reset *rst; 343 struct clk *clk; 344 int n; 345 346 for (n = 0; n < __arraycount(clock_names); n++) { 347 clk = fdtbus_clock_get(sc->sc_phandle, clock_names[n]); 348 if (clk == NULL || clk_enable(clk) != 0) 349 aprint_error_dev(sc->sc_dev, "couldn't enable clock %s\n", 350 clock_names[n]); 351 } 352 353 for (n = 0; n < __arraycount(reset_names); n++) { 354 rst = fdtbus_reset_get(sc->sc_phandle, reset_names[n]); 355 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) 356 aprint_error_dev(sc->sc_dev, "couldn't de-assert reset %s\n", 357 reset_names[n]); 358 } 359 } 360 361 #if 0 362 static void 363 tegra_pcie_reset_port(struct tegra_pcie_softc * const sc, int index) 364 { 365 uint32_t val; 366 367 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 368 val &= ~AFI_PEXn_CTRL_RST_L; 369 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 370 371 delay(2000); 372 373 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 374 val |= AFI_PEXn_CTRL_RST_L; 375 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 376 } 377 #endif 378 379 static void 380 tegra_pcie_enable_ports(struct tegra_pcie_softc * const sc) 381 { 382 struct fdtbus_phy *phy; 383 const u_int *data; 384 int child, len, n; 385 uint32_t val; 386 387 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 388 if (!fdtbus_status_okay(child)) 389 continue; 390 391 /* Enable PHYs */ 392 for (n = 0; (phy = fdtbus_phy_get_index(child, n)) != NULL; n++) 393 if (fdtbus_phy_enable(phy, true) != 0) 394 aprint_error_dev(sc->sc_dev, "couldn't enable %s phy #%d\n", 395 fdtbus_get_string(child, "name"), n); 396 397 data = fdtbus_get_prop(child, "reg", &len); 398 if (data == NULL || len < 4) 399 continue; 400 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 401 402 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index)); 403 val |= AFI_PEXn_CTRL_CLKREQ_EN; 404 val |= AFI_PEXn_CTRL_REFCLK_EN; 405 val |= AFI_PEXn_CTRL_REFCLK_OVERRIDE_EN; 406 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXn_CTRL_REG(index), val); 407 408 #if 0 409 tegra_pcie_reset_port(sc, index); 410 #endif 411 412 } 413 } 414 415 static void 416 tegra_pcie_setup(struct tegra_pcie_softc * const sc) 417 { 418 uint32_t val, cfg, lanes; 419 int child, len; 420 const u_int *data; 421 size_t i; 422 423 /* Enable PLLE control */ 424 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG); 425 val &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 426 val |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 427 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PLLE_CONTROL_REG, val); 428 429 /* Disable PEX clock bias pad power down */ 430 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PEXBIAS_CTRL_REG, 0); 431 432 /* Configure PCIE mode and enable ports */ 433 cfg = bus_space_read_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG); 434 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(0); 435 cfg |= AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(1); 436 cfg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG; 437 438 lanes = 0; 439 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 440 if (!fdtbus_status_okay(child)) 441 continue; 442 data = fdtbus_get_prop(child, "reg", &len); 443 if (data == NULL || len < 4) 444 continue; 445 const u_int index = ((be32toh(data[0]) >> 11) & 0x1f) - 1; 446 if (of_getprop_uint32(child, "nvidia,num-lanes", &val) != 0) 447 continue; 448 lanes |= (val << (index << 3)); 449 cfg &= ~AFI_PCIE_CONFIG_PCIECn_DISABLE_DEVICE(index); 450 } 451 452 switch (lanes) { 453 case 0x0104: 454 aprint_normal_dev(sc->sc_dev, "lane config: x4 x1\n"); 455 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_4_1, 456 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 457 break; 458 case 0x0102: 459 aprint_normal_dev(sc->sc_dev, "lane config: x2 x1\n"); 460 cfg |= __SHIFTIN(AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_2_1, 461 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG); 462 break; 463 } 464 465 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_PCIE_CONFIG_REG, cfg); 466 467 /* Configure refclk pad */ 468 const char * const tegra124_compat[] = { "nvidia,tegra124-pcie", NULL }; 469 if (of_match_compatible(sc->sc_phandle, tegra124_compat)) 470 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 471 0x44ac44ac); 472 const char * const tegra210_compat[] = { "nvidia,tegra210-pcie", NULL }; 473 if (of_match_compatible(sc->sc_phandle, tegra210_compat)) 474 bus_space_write_4(sc->sc_bst, sc->sc_bsh_pads, PADS_REFCLK_CFG0_REG, 475 0x90b890b8); 476 477 /* 478 * Map PCI address spaces into ARM address space via 479 * HyperTransport-like "FPCI". 480 */ 481 static const struct { uint32_t size, base, fpci; } pcie_init_table[] = { 482 /* 483 * === BEWARE === 484 * 485 * We depend on our TEGRA_PCIE_IO window overlaping the 486 * TEGRA_PCIE_A1 window to allow us to use the same 487 * bus_space_tag for both PCI IO and Memory spaces. 488 * 489 * 0xfdfc000000-0xfdfdffffff is the FPCI/HyperTransport 490 * mapping for 0x0000000-0x1ffffff of PCI IO space. 491 */ 492 { TEGRA_PCIE_IO_SIZE >> 12, TEGRA_PCIE_IO_BASE, 493 (0xfdfc000000 + TEGRA_PCIE_IO_BASE) >> 8 | 0, }, 494 495 /* HyperTransport Technology Type 1 Address Format */ 496 { TEGRA_PCIE_CONF_SIZE >> 12, TEGRA_PCIE_CONF_BASE, 497 0xfdff000000 >> 8 | 0, }, 498 499 /* 1:1 MMIO mapping */ 500 { TEGRA_PCIE_MEM_SIZE >> 12, TEGRA_PCIE_MEM_BASE, 501 TEGRA_PCIE_MEM_BASE >> 8 | 1, }, 502 503 /* Extended HyperTransport Technology Type 1 Address Format */ 504 { TEGRA_PCIE_EXTC_SIZE >> 12, TEGRA_PCIE_EXTC_BASE, 505 0xfe10000000 >> 8 | 0, }, 506 507 /* 1:1 prefetchable MMIO mapping */ 508 { TEGRA_PCIE_PMEM_SIZE >> 12, TEGRA_PCIE_PMEM_BASE, 509 TEGRA_PCIE_PMEM_BASE >> 8 | 1, }, 510 }; 511 512 for (i = 0; i < AFI_AXI_NBAR; i++) { 513 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 514 AFI_AXI_BARi_SZ(i), 0); 515 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 516 AFI_AXI_BARi_START(i), 0); 517 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 518 AFI_FPCI_BARi(i), 0); 519 } 520 521 for (i = 0; i < __arraycount(pcie_init_table); i++) { 522 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 523 AFI_AXI_BARi_START(i), pcie_init_table[i].base); 524 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 525 AFI_FPCI_BARi(i), pcie_init_table[i].fpci); 526 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 527 AFI_AXI_BARi_SZ(i), pcie_init_table[i].size); 528 } 529 } 530 531 static void 532 tegra_pcie_enable(struct tegra_pcie_softc *sc) 533 { 534 /* disable MSI */ 535 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 536 AFI_MSI_BAR_SZ_REG, 0); 537 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 538 AFI_MSI_FPCI_BAR_ST_REG, 0); 539 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 540 AFI_MSI_AXI_BAR_ST_REG, 0); 541 542 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 543 AFI_SM_INTR_ENABLE_REG, 0xffffffff); 544 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 545 AFI_AFI_INTR_ENABLE_REG, 0); 546 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, AFI_INTR_CODE_REG, 0); 547 bus_space_write_4(sc->sc_bst, sc->sc_bsh_afi, 548 AFI_INTR_MASK_REG, AFI_INTR_MASK_INT); 549 } 550 551 static void 552 tegra_pcie_conf_frag_map(struct tegra_pcie_softc * const sc, uint bus, 553 uint frg) 554 { 555 bus_addr_t a; 556 557 KASSERT(bus >= 1); 558 KASSERT(bus < TEGRA_PCIE_NBUS); 559 KASSERT(frg < TEGRA_PCIE_ECFB); 560 561 if (sc->sc_bsh_extc[bus-1][frg] != 0) { 562 device_printf(sc->sc_dev, "bus %u fragment %#x already " 563 "mapped\n", bus, frg); 564 return; 565 } 566 567 a = TEGRA_PCIE_EXTC_BASE + (bus << 16) + (frg << 24); 568 if (bus_space_map(sc->sc_bst, a, 1 << 16, 0, 569 &sc->sc_bsh_extc[bus-1][frg]) != 0) 570 device_printf(sc->sc_dev, "couldn't map PCIE " 571 "configuration for bus %u fragment %#x", bus, frg); 572 } 573 574 /* map non-non-extended configuration space for full bus range */ 575 static void 576 tegra_pcie_conf_map_bus(struct tegra_pcie_softc * const sc, uint bus) 577 { 578 uint i; 579 580 for (i = 1; i < TEGRA_PCIE_ECFB; i++) { 581 tegra_pcie_conf_frag_map(sc, bus, i); 582 } 583 } 584 585 /* map non-extended configuration space for full bus range */ 586 static void 587 tegra_pcie_conf_map_buses(struct tegra_pcie_softc * const sc) 588 { 589 uint b; 590 591 for (b = 1; b < TEGRA_PCIE_NBUS; b++) { 592 tegra_pcie_conf_frag_map(sc, b, 0); 593 } 594 } 595 596 void 597 tegra_pcie_init(pci_chipset_tag_t pc, void *priv) 598 { 599 pc->pc_conf_v = priv; 600 pc->pc_attach_hook = tegra_pcie_attach_hook; 601 pc->pc_bus_maxdevs = tegra_pcie_bus_maxdevs; 602 pc->pc_make_tag = tegra_pcie_make_tag; 603 pc->pc_decompose_tag = tegra_pcie_decompose_tag; 604 pc->pc_conf_read = tegra_pcie_conf_read; 605 pc->pc_conf_write = tegra_pcie_conf_write; 606 pc->pc_conf_hook = tegra_pcie_conf_hook; 607 pc->pc_conf_interrupt = tegra_pcie_conf_interrupt; 608 609 pc->pc_intr_v = priv; 610 pc->pc_intr_map = tegra_pcie_intr_map; 611 pc->pc_intr_string = tegra_pcie_intr_string; 612 pc->pc_intr_evcnt = tegra_pcie_intr_evcnt; 613 pc->pc_intr_setattr = tegra_pcie_intr_setattr; 614 pc->pc_intr_establish = tegra_pcie_intr_establish; 615 pc->pc_intr_disestablish = tegra_pcie_intr_disestablish; 616 } 617 618 static void 619 tegra_pcie_attach_hook(device_t parent, device_t self, 620 struct pcibus_attach_args *pba) 621 { 622 const pci_chipset_tag_t pc = pba->pba_pc; 623 struct tegra_pcie_softc * const sc = pc->pc_conf_v; 624 625 if (pba->pba_bus >= 1) { 626 tegra_pcie_conf_map_bus(sc, pba->pba_bus); 627 } 628 } 629 630 static int 631 tegra_pcie_bus_maxdevs(void *v, int busno) 632 { 633 return busno == 0 ? 2 : 32; 634 } 635 636 static pcitag_t 637 tegra_pcie_make_tag(void *v, int b, int d, int f) 638 { 639 return (b << 16) | (d << 11) | (f << 8); 640 } 641 642 static void 643 tegra_pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 644 { 645 if (bp) 646 *bp = (tag >> 16) & 0xff; 647 if (dp) 648 *dp = (tag >> 11) & 0x1f; 649 if (fp) 650 *fp = (tag >> 8) & 0x7; 651 } 652 653 static pcireg_t 654 tegra_pcie_conf_read(void *v, pcitag_t tag, int offset) 655 { 656 struct tegra_pcie_softc *sc = v; 657 bus_space_handle_t bsh; 658 int b, d, f; 659 u_int reg; 660 661 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 662 return (pcireg_t) -1; 663 664 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 665 666 if (b >= TEGRA_PCIE_NBUS) 667 return (pcireg_t) -1; 668 669 if (b == 0) { 670 if (d >= 2 || f != 0) 671 return (pcireg_t) -1; 672 reg = d * 0x1000 + offset; 673 bsh = sc->sc_bsh_rpconf; 674 } else { 675 reg = (d << 11) | (f << 8) | (offset & 0xff); 676 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 677 if (bsh == 0) 678 return (pcireg_t) -1; 679 } 680 681 return bus_space_read_4(sc->sc_bst, bsh, reg); 682 } 683 684 static void 685 tegra_pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 686 { 687 struct tegra_pcie_softc *sc = v; 688 bus_space_handle_t bsh; 689 int b, d, f; 690 u_int reg; 691 692 if ((unsigned int)offset >= PCI_EXTCONF_SIZE) 693 return; 694 695 tegra_pcie_decompose_tag(v, tag, &b, &d, &f); 696 697 if (b >= TEGRA_PCIE_NBUS) 698 return; 699 700 if (b == 0) { 701 if (d >= 2 || f != 0) 702 return; 703 reg = d * 0x1000 + offset; 704 bsh = sc->sc_bsh_rpconf; 705 } else { 706 reg = (d << 11) | (f << 8) | (offset & 0xff); 707 bsh = sc->sc_bsh_extc[b-1][(offset >> 8) & 0xf]; 708 if (bsh == 0) 709 return; 710 } 711 712 bus_space_write_4(sc->sc_bst, bsh, reg, val); 713 } 714 715 static int 716 tegra_pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 717 { 718 return PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM; 719 } 720 721 static void 722 tegra_pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, 723 int *ilinep) 724 { 725 *ilinep = 5; 726 } 727 728 static int 729 tegra_pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 730 { 731 if (pa->pa_intrpin == 0) 732 return EINVAL; 733 *ih = pa->pa_intrpin; 734 return 0; 735 } 736 737 static const char * 738 tegra_pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 739 { 740 struct tegra_pcie_softc *sc = v; 741 742 if (ih == PCI_INTERRUPT_PIN_NONE) 743 return NULL; 744 745 if (!fdtbus_intr_str(sc->sc_phandle, 0, buf, len)) 746 return NULL; 747 748 return buf; 749 } 750 751 const struct evcnt * 752 tegra_pcie_intr_evcnt(void *v, pci_intr_handle_t ih) 753 { 754 return NULL; 755 } 756 757 static int 758 tegra_pcie_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 759 { 760 switch (attr) { 761 case PCI_INTR_MPSAFE: 762 if (data) 763 *ih |= IH_MPSAFE; 764 else 765 *ih &= ~IH_MPSAFE; 766 return 0; 767 default: 768 return ENODEV; 769 } 770 } 771 772 static void * 773 tegra_pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 774 int (*callback)(void *), void *arg, const char *xname) 775 { 776 struct tegra_pcie_softc *sc = v; 777 struct tegra_pcie_ih *pcie_ih; 778 779 if (ih == 0) 780 return NULL; 781 782 pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP); 783 pcie_ih->ih_callback = callback; 784 pcie_ih->ih_arg = arg; 785 pcie_ih->ih_ipl = ipl; 786 pcie_ih->ih_mpsafe = (ih & IH_MPSAFE) != 0; 787 788 mutex_enter(&sc->sc_lock); 789 TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry); 790 sc->sc_intrgen++; 791 mutex_exit(&sc->sc_lock); 792 793 return pcie_ih; 794 } 795 796 static void 797 tegra_pcie_intr_disestablish(void *v, void *vih) 798 { 799 struct tegra_pcie_softc *sc = v; 800 struct tegra_pcie_ih *pcie_ih = vih; 801 802 mutex_enter(&sc->sc_lock); 803 TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry); 804 mutex_exit(&sc->sc_lock); 805 806 kmem_free(pcie_ih, sizeof(*pcie_ih)); 807 } 808